A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation

Keng-Jan Hsiao and Tai-Cheng Lee

National Taiwan University

Taipei, Taiwan

Outline

• Motivation

• System Architecture

• System Model

• Circuit Details

• Experimental Results

• Conclusion

2

Introductions

• Multiple-Phase Clock Generators– Time-Interleaved System– I/O Interface Circuits– DLL-Based Frequency Multiplier

• Issues– Phase Accuracy– Jitter Performance

3

Conventional DLL

• Only one output phase is monitored.

4H.-H. Chang et al, IEEE J. of Solid-State Circuits, May, 2006.

DLL with Phase Calibration Circuit

• Delay cell tuning.

• Output buffer tuning.5

Federico Baronti et all, IEEE J. of Solid-State Circuits, Feb., 2004.

H.-H. Chang et al, IEEE J. of Solid-State Circuits, May, 2006.

Jitter Accumulation

• Jitter accumulates along the delay line.

• More delay cells = Larger jitter.6

Distributed DLL(DDLL)

• All output phases are monitored.

• Reduce phase mismatch and jitter.

7

Locking Process of the DDLL

8

• Conceptual demonstration of the DDLL.

System Architecture

• Each delay cell is independently tuned.9

Closed-loop Characteristics

10

-1V/I ref

-1L

0.5+0.5 z K T

1-z C

• Lumped model:

Phase Relationship of Multiple-Phases

11

• Different clock tracks different Ref. edge.

System Model

-1

-1 -1 -1 -1p0 p1 p1 p2 p1-1

-1

-1 -1 -1 -1p0 p2 p2 p4 p1 p2-1

-1

-1 -1 -1p1 p3 p3 p0 p2 p3-1

-1

-1 -1 -1p3 p4 p4 p0

0.5+0.5 z K(z V -z V )-(z V -z V ) =V

1-z

0.5+0.5 z K(z V -z V )-(z V -z V ) +V =V

1-z

0.5+0.5 z K(z V -z V )-(z V -V ) +V =V

1-z

0.5+0.5 z(z V -z V )-(z V -V )

p3 p4-1

K+V =V

1-z

PD V/I ref D

L

K K T KK=

C

Open-loop Gain:

System Function:

12

Settling Behavior

• The simulation result matches the proposed model.

13

Stability Constraint

• The open-loop gain must reduce as the number of delay cells increases.

14

Sources of Jitter

• Vn,cell : Noise from delay cells.

• Vn,con : Noise from the control voltage.

15

NTF of the Noise of Delay Cells

• Noise at the last output clock, Vp4.16

NTF of the Common Noise

• Noise at all output phases , Vp1~Vp4.17

Pseudo-differential Delay Cell

• Pseudo-differential architecture.

• Differentially controlled.

• Output buffer isolates output loading.18

Phase Detecter

19

• Time Domain Voltage Domain

Voltage-to-Current Convertor

• Continuous-time common-mode feedback.

• Loop capacitors are realized on-chip.

20

Die Photo

Active Area = 0.03 mm2

21

Phase Mismatch @ 8GHz

22

Phase Mismatch @ 9.5GHz

23

8.5GHz Output Waveform

Conventional DLL Distributed DLL

RMS Jitter : 643.5fs RMS Jitter : 417.6fs

P-P Jitter : 5.67ps P-P Jitter : 4.22ps Contributed Jitter : 578.9fs Contributed Jitter : 308.1fs

RMS Jitter of Ref. Clk : 281.0fs24

10GHz Output Waveform

Conventional DLL Distributed DLL

RMS Jitter : 443.8fs RMS Jitter : 293.3fs

P-P Jitter : 3.18ps P-P Jitter : 2.04ps Contributed Jitter : 366.7fs Contributed Jitter : 153.4fs

RMS Jitter of Ref. Clk : 256.8fs

25

Performance Comparison

26

Conclusion

• The distributed DLL achieves low jitter and high phase accuracy.

• Linear model of the proposed distributed DLL is provided.

27

Backup Slides

Testing Setup

30