a linearization technique for a transconductor using vertical bipolar junction transistors in a cmos...

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 1, JANUARY 2013 195

A Linearization Technique for a TransconductorUsing Vertical Bipolar Junction Transistors

in a CMOS ProcessKuduck Kwon, Member, IEEE, and Ilku Nam, Member, IEEE

Abstract—In this paper, a linearization technique for a transcon-ductor using vertical NPN (V-NPN) bipolar junction transistors(BJTs) in a deep n-well CMOS process is proposed to achievehigh linearity performance without degrading power efficiencyand noise performance. The proposed transconductor consistsof a V-NPN BJT pseudodifferential transconductor (PDT) and aV-NPN BJT fully differential transconductor (FDT). The linearityof the proposed transconductor is improved by canceling thenegative peak value of in the FDT with the positive one in thePDT and by making overall of the proposed transconductorclose to zero. To verify the proposed linearization method, anRF amplifier and a first-order - low-pass filter adoptingthe proposed transconductor are designed and implemented ina 0.18- m deep n-well CMOS process. The implemented RFamplifier and - low-pass filter achieve 5.8- and 8.5-dBimprovements over conventional circuits in the output-referredthird-order intercept point, respectively.

Index Terms—CMOS, deep n-well, fully differential transcon-ductor (FDT), linearization technique, pseudodifferentialtransconductor (PDT), vertical bipolar junction transistor (BJT).

I. INTRODUCTION

A transconductor is a key building part in RF and analogcircuits, such as low-noise amplifiers, RF variable gain

amplifiers, active mixers, - filters, and baseband analog(BBA) circuits, because it has a great impact on the frequencyresponse, noise, and linearity of those circuits. Therefore, it isessential that the transconductor has high-performance charac-teristics, such as large transconductance , low noise figure(NF), and high linearity [1]–[4].To design transconductors with high performance for RF

and analog circuits, bipolar junction transistors (BJTs), whichare generally provided through a BiCMOS process, are pre-ferred since transconductors using BJTs have larger andlower low-noise performance than do transconductors usingMOSFETs [5]. Recently, deep n-well CMOS processes haveprovided vertical NPN (V-NPN) BJT as well as MOSFET

Manuscript received July 15, 2012; accepted October 18, 2012. Date of publi-cation November 30, 2012; date of current version January 17, 2013. This workwas supported by the Ministry of Education, Science and Technology under theBasic Science Research Program through the National Research Foundation ofKorea (NRF) (2012-0001956).K. Kwon is with the Samsung Electronics Company Ltd., Suwon 444-370,

Korea.I. Nam is with the Department of Electrical Engineering, Pusan National Uni-

versity, Busan 609-735, Korea (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TMTT.2012.2226602

devices [6], [7]. The availability of the V-NPN BJT in deepn-well CMOS has a great impact on analog circuit design.Transconductors using V-NPN BJTs inherently are expectedto have large and low low-frequency noise performance.However, the linearity of transconductors using V-NPN BJTsshould be improved before they are adopted in high-end sys-tems.Many BJT transconductor linearization techniques have been

published. One of the most famous linearization techniques is aform of series feedback by source degeneration, but it degradesthe noise performance [8]. The linearity of a transconductorcan also be improved through the use of an operational am-plifier (op-amp), though the loop gain of the op-amp mustbe high enough at the transconductor operating frequencies[9]. Another method is to construct the transconductor withmultiple differential pairs [10], [11]; however, this methoddegrades the power efficiency of the transconductor. That is,the overall of a transconductor with two differential pairsis 36% smaller than that of a conventional transconductorat the same power consumption. Another technique utilizesexponential third-order intermodulation (IM3) canceling byproper termination of the second-order products, but it is notsuitable for high integration due to passive inductors [12].With a transconductor linearization method in which V-NPN

BJTs are adopted, a high-performance transconductor can bedesigned with large , low-noise, and high linearity. In thispaper, a linearization method for a transconductor using V-NPNBJTs is proposed. The proposed method is verified by the ex-perimental results obtained for a transconductor implementedin a 0.18- m deep n-well CMOS process. In Section II, theproposed transconductor linearization technique is described indetail. The proposed method does not degrade the power ef-ficiency or thermal noise of the transconductor. V-NPN BJTtransconductors adopting the proposed linearization method foran RF amplifier and a - low-pass filter are presented inSection III. Section IV presents the measurement results for anRF amplifier and a first-order - low-pass filter that utilizethe proposed transconductor. Finally, Section V concludes thispaper.

II. NEW LINEARIZATION TECHNIQUE FOR ATRANSCONDUCTOR USING V-NPN BJTs

In this section, a new linearization method for a transcon-ductor using V-NPN BJTs is introduced, and a detailed analysisof the proposed method is presented. The power efficiency and

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196 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 1, JANUARY 2013

Fig. 1. CE amplifier.

noise characteristics of the proposed linearization technique arealso analyzed.

A. New Linearization Technique

Nonlinearity of a common emitter (CE) amplifier shown inFig. 1 mostly results from voltage-to-current conversion. Usinga Taylor-series expansion, the collector current of the CE am-plifier can be expressed as

(1)

where is a small-signal base-to-emitter voltage and in-dicates the th order derivative of with respect to . It iswell known that the coefficient of in (1) plays an importantrole in determining the IM3 distortion of an amplifier [13], [14].Hence, making the coefficient of close to zero is importantfor improving the linearity performance of the CE amplifier.A CE amplifier has the following – characteristic [15]:

(2)

where is an input small signal, is the base-to-emitterdc voltage, is the saturation current, and . Byusing a Taylor-series expansion, the collector current of the CEamplifier is given by

(3)

Fig. 2(a) presents a pseudodifferential transconductor (PDT)that consists of the CE amplifiers shown in Fig. 1. The totaloutput current of the PDT, , is given by

(4)

On the other hand, the output currents of a fully differentialtransconductor (FDT) shown in Fig. 2(b), and , are givenby

(5)

(6)

Fig. 2. (a) PDT. (b) FDT.

Fig. 3. Proposed transconductor that consists of a PDT and an FDT.

The output current of the FDT, , can be expressed asfollows using a Taylor-series expansion:

(7)

As can be seen from (4) and (7), the coefficients of the third-order terms of the PDT and FDT have opposite signs. Thismeans that combining these two topologies can make the third-order term close to zero, and then, the third-order nonlinearitydistortion can be cancelled. The transconductor employing thenew linearization technique is presented in Fig. 3. The outputcurrent of the proposed transconductor, , is given by

(8)

KWON AND NAM: LINEARIZATION TECHNIQUE FOR TRANSCONDUCTOR USING VERTICAL BJTs IN CMOS PROCESS 197

Fig. 4. (a) of the FDT, PDT, and combined FDT and PDT. (b) of theFDT, PDT, and combined FDT and PDT.

From (8), the second-derivative of transconductance, , canbe made close to zero when . From the intuitiveand simple dc analysis, it is obvious that the proposed methodcan improve the linearity performance of a transconductor usingV-NPNBJTs. Fig. 4 shows the simulated and of the PDT,FDT, and the combined PDT and FDT, respectively. By com-bining the PDT and FDT, the overall can be made close tozero, as shown in Fig. 4(b). In addition, Fig. 4(a) indicates thatthe linear input voltage range with a constant becomes widerwhen the proposed linearization method is applied.To prove that the proposed method works well at high

frequencies, the high-frequency nonlinearity of the proposedtransconductor is analyzed in detail using a Volterra series.Fig. 5 presents the small-signal models used to derive non-linearity equations for the PDT and FDT shown in Fig. 2.These models ignore the effect of the base–collector junctioncapacitance of . Inclusion of complicates theanalysis without adding any significant accuracy to the resultsin typical situations. is the voltage signal source. is thebase-charging capacitance of , which is linearly proportionalto the collector current and the forward transit time of .

is the base–emitter junction capacitance, which is assumedto be constant in this model. is the base current, which isequal to , where is the small-signal low-frequencycurrent gain of . is the impedance at the base of, which includes source resistance, base resistance of ,

shunt impedance of bias circuits or impedance of the matchingnetworks. is the impedance at the emitter of , which

Fig. 5. Small-signal models of the: (a) PDT and (b) FDT.

represents the wire-bonding inductor. Using a Volterra series,the output currents of the PDT can be expressed as follows:

(9)

(10)

where is th power of the voltage source signal andis the Volterra-series coefficient, which is a linear function offrequencies. The first three Volterra-series coefficients of the

PDT output currents are given by [16], [17]

(11)

(12)

(13)

where , is the bias current ofand , and is

(14)


Similar to the case of the PDT, the output currents of a FDT canbe expressed as

(15)

(16)

The first three Volterra-series coefficients of the FDT output cur-rents are given by [16], [17]

(17)

(18)

(19)

where is the bias current of and , and is

(20)

From (9), (10), (15), and (16), the output current of the proposedtransconductor is given by

(21)

The third-order intermodulation intercept point (IIP3) at fre-quency can be calculated by using the Volterra-seriescoefficient , and ensuring that , ,and . Typically, the frequency difference betweenand is so small that the following equality can be assumed:

. The IIP3 of the proposed transconductor is givenby

(22)

After complex mathematical analyses using (11)–(14) and(17)–(20), and are expressedas

(23)

(24)

where . When , the IIP3 at fre-quency can be shown in (25) at the bottom of this page.From (22), it is clear that should be close to 0 inorder to maximize the IIP3. Therefore, the proposed transcon-ductor has the maximum IIP3 when the condition shown in (26)at the bottom of the following page is met. At low frequencies,

, , , and , are represented as follows:

(27)

(28)

where is resistive components, and is inductivecomponent, which is bonding inductors

(29)

(30)

where

(25)


Fig. 6. Simulated OIP3 versus in the proposed RF amplifier whenmA.

Using (26)–(30), (25) can be simply given at the low frequencyby

(31)

where , sinceand are resistive components, which represents

the impedance at the base of , which includes source resis-tance, base resistance of , and shunt impedance of bias cir-cuits or impedance of the matching networks. The previous dcanalysis is the special case of (31) in the condition of

so . Equation (31) can be given by

(32)

Therefore, the IIP3 is maximized when , i.e.,.When is not 0 and , optimal

for maximum IIP3 is decreasing from 0.5. As the operatingfrequencies increase, the effects of the reactive components arenot negligible so optimum should be chosen after thoroughsimulation at operating frequencies.

B. Power Efficiency

In linearization techniques, the power efficiency of thetransconductor with linearization circuits, , is critical,where is the overall transconductance and is the totalcurrent consumption of the transconductor. Under the conditionof where linearity is maximized,and . Therefore, the power efficiency of the proposedlinearization technique is expressed as

(33)

When the conventional PDT has the same power consumptionas the proposed transconductor, the power efficiency of the con-ventional PDT is , which is the same as thatof the proposed transconductor. Therefore, the proposedmethodcan improve the transconductor linearity without degrading thepower efficiency of the transconductor.

C. Noise

The input-referred thermal noise voltage of the proposedtransconductor is expressed as

(34)where is the base resistance of , and is the transcon-ductance of . When , , and

, then , and hence, (34) can begiven by

(35)

which is the same as the input-referred thermal noise voltageof the conventional PDT with the same current consump-tion. It is obvious that the proposed method can improve thetransconductor linearity without degrading the thermal noiseperformance.

III. V-NPN TRANSCONDUCTORS ADOPTING THE

PROPOSED LINEARIZATION TECHNIQUE

To verify the proposed linearization method, an RF/IF ampli-fier and a - filter adopting the proposed transconductor aredesigned and evaluated, as described in this section.

A. RF/IF Amplifier

The proposed transconductor, which is shown in Fig. 3, canbe used for an RF amplifier. The gain of the proposed amplifieris given by

Gain (36)

The optimal condition of for the maximum output-referred third-order intercept point (OIP3) is simulated. Twotones of 200 and 205.5 MHz are considered. Fig. 6 shows thatthe proposed RF amplifier achieves the maximum OIP3 when

. For this simulation, the value of is 18 ps [7]. Due tothe effect of source resistance, frequency-dependent terms, andparasitic capacitance in (26), optimal is changed fromfrom dc analysis to 0.2. Fig. 7 presents the linearity compar-ison of the proposed amplifier with the conventional amplifiersadopting the PDT or the FDT. It is assumed that all amplifiershave the same current consumption. As can be seen in Fig. 7, the

(26)


Fig. 7. Simulated IIP3 of the conventional amplifiers and the proposed ampli-fier with the same current consumption.

Fig. 8. Simulated OIP3 of the proposed RF amplifier versus PVT variations.TT, SS, and FF stand for the typical, slow, and fast model of nMOS and pMOS,respectively.

proposed amplifier has better linearity performance than do theothers at the same power consumption. Fig. 8 presents the OIP3of the proposed RF amplifier and the conventional PDT withthe same power consumption with respect to process, voltage,and temperature (PVT) variations. As can be seen in Fig. 8, theproposed linearization technique works well even though PVTvariations exist. The RF amplifier is biased by the circuit basedon the current-mirror technique [18]

B. RF - Filter

Fig. 9 shows the first-order RF - low-pass filteradopting the proposed transconductor of Fig. 10. The combinedPDT and FDT is used as a voltage-to-current conversion device,and the output common-mode voltage level of the transcon-ductor is set to a constant value with a common-mode feedback(CMFB) loop, as shown in Fig. 10(a). An error amplifier, whichis shown in Fig. 10(b), senses the voltage difference between

and and feeds it back to the gates of the pMOSload transistors ( and ) in Fig. 10(a). For stabilizationof the two-stage CMFB loop, the gain of the CMFB loop isreduced by a source degeneration resistor and the loop’sphase margin is improved by the Miller capacitor .The transconductance of the proposed transconductor is

given by

(37)

Fig. 9. Schematic of the first-order - low-pass filter adopting the pro-posed transconductor.

Fig. 10. (a) Transconductor adopting the proposed linearization technique witha pMOS load. (b) Error amplifier in the common mode feedback loop.

The input-referred noise voltage of the proposed transconductoris expressed as

(38)

where is the base resistance of ; , the transconduc-tance of ; , the transconductance of ; , a process-dependent constant for noise; , the gate–oxide capaci-tance per unit area; , the width of ; , the length of ;and , a noise parameter.


Fig. 11. (a) Chip microphotograph of the RF amplifier. (b) Chip microphoto-graph of the first-order - low-pass filter.

Fig. 12. Measured frequency response of the RF amplifier adopting the pro-posed transconductor.

Fig. 13. Measured OIP3 of the RF amplifier adopting the proposed transcon-ductor.

IV. MEASUREMENT RESULTS

The RF amplifier and first-order - low-pass filteradopting the proposed transconductor were implemented in a0.18- m deep n-well CMOS process to prove the feasibility ofthe proposed linearization technique. Fig. 11 shows the chipmicrophotograph of the implemented RF amplifier and filter.The chip core size of the RF amplifier is 0.13 mm 0.1 mm.It draws 2.6 mA from a 1.8-V supply voltage. The measuredfrequency response of the RF amplifier is shown in Fig. 12.The gain of the RF amplifier is 15.1 dB. Fig. 13 shows themeasured OIP3 when two tones of 200 and 205.5 MHz are ap-plied. By adopting the proposed linearization technique, 5.8 dBof OIP3 improvement is achieved over the case where the

Fig. 14. Measured OIP3 of the RF amplifiers on various dies.

Fig. 15. Measured frequency response of the first-order - low-pass filteradopting the proposed transconductor.

Fig. 16. Measured OIP3 of the first-order - low-pass filter adopting theproposed transconductor.

amplifier using only a PDT with the same power consumptionis employed. Fig. 14 presents the OIP3 of the RF amplifiers onvarious dies. The proposed method can work well on variousdies.The chip size of the first-order - low-pass filter is

0.45 mm 0.3 mm. It draws 2.6 mA from a 1.8-V supplyvoltage. The measured frequency response of the filter is shownin Fig. 15. The cutoff frequency of the filter is 300 MHz. Asshown in Fig. 16, the measured OIP3 is 7 dBm when twotones of 300 and 305.5 MHz are applied. By adopting theproposed linearization technique, the - low-pass filterachieves 8.5 dB of OIP3 improvement with the same powerconsumption. Table I summarizes the performance of the RFamplifier and - filter. It is noted that the proposed method


TABLE IPERFORMANCE SUMMARY OF THE RF AMPLIFIER AND THE - FILTER EMPLOYING THE PROPOSED TRANSCONDUCTOR

Parameter values of these blocks are simulated.

can improve linearity without degrading other performancessuch as power efficiency and noise.

V. CONCLUSION

A linearization method using V-NPN BJTs in a deep n-wellCMOS process is proposed to improve the dynamic range of atransconductor. The proposed method makes the overall ofthe transconductor close to zero by combining a V-NPN BJTPDT and a V-NPN BJT FDT with the proper current ratio. Theimplemented RF amplifier and first-order - low-pass filterachieve 5.8- and 8.5-dB OIP3 improvements, respectively. Themethod can also be employed to active mixers and BBA cir-cuits. The proposed technique is especially beneficial for BBAcircuits in direct-conversion receivers (DCRs) and low-IF re-ceivers because it provides high linearity performance, as wellas low noise performance.

ACKNOWLEDGMENT

The authors would like to thank the reviewers for valuablecomments and advice.

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Kuduck Kwon (S’07–M’11) received the B.S.and Ph.D. degrees in electrical engineering andcomputer science from the Korea Advanced Instituteof Science and Technology (KAIST), Daejeon,Korea, in 2004 and 2009, respectively. His doctoralresearch concerned digital TV tuners and dedicatedshort-range communication (DSRC) systems.From 2009 to 2010, he was a Post-Doctoral

Researcher with KAIST, where he studied a surfaceacoustic wave (SAW)-less receiver and developedRF transceivers for DSRC applications. Since 2010,

he has been with the Samsung Electronics Company Ltd., Suwon, Korea,where he has been involved in the study of software receivers and developingsilicon tuners. His research interests are CMOS RF/analog integrated circuitsand RF system design for wireless communications.


Ilku Nam (S’02–M’06) received the B.S. degreein electronics engineering from Yonsei University,Seoul, Korea, in 1999, and the M.S. and Ph.D. de-grees in electrical engineering and computer sciencefrom the Korea Advanced Institute of Science andTechnology (KAIST), Daejeon, Korea, in 2001 and2005, respectively.From 2005 to 2007, he was a Senior Engineer with

Samsung Electronics, Gyeonggi, Korea, where hewas involved in the development of mobile digitalTV tuner integrated circuits (ICs). In 2007, he joined

the School of Electrical Engineering, Pusan National University, Busan, Korea,where he is currently an Associate Professor. His research interests are CMOSRF/mixed-mode IC and RF system design, and interfaces between RF andmodems.Prof. Nam was a member of the Technical Program Committee, 2011 IEEE

ASSCC.He is amember of the Technical ProgramCommittee, 2013 IEEEWire-less Symposium.

a linearization technique for a transconductor using vertical bipolar junction transistors in a cmos...

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