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Status of cogging December 4, 2013 Creig Drennan, Bill Pellico, Kiyomi Seiya, Kent Triplett, Alex Waller

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Status of cogging December 4, 2013 Creig Drennan , Bill Pellico , Kiyomi Seiya , Kent Triplett, Alex Waller. LLRF Room. G16-RR2-1. G14-RR5-1. G11-RR7-1. Cables to 48 correctors from LLRF room (K. Triplett, D. Dick). A OUT 1. A OUT 1. A OUT 2. A OUT 2. A OUT 3. - PowerPoint PPT Presentation

TRANSCRIPT

Status of cogging

December 4, 2013

Creig Drennan, Bill Pellico, Kiyomi Seiya, Kent Triplett, Alex Waller

+A INA

OUT 1

A OUT

2

A OUT

3

B OUT

1

BOUT

2

B OUT

3+B IN

+A INA

OUT 1

A OUT

2

A OUT

3

B OUT

1

BOUT

2

B OUT

3+B IN

1 2 3 4 6 7 85 1 2 3 4 6 7 85 1 2 3 4 6 7 85

1 2 3 4 6 7 85 1 2 3 4 6 7 85 1 2 3 4 6 7 8516

15 14 13

A IN

A OUT1

A OUT2B IN

BOUT1

B OUT2

6

7

5

4

8AOUT3

BOUT3

AOUT1

BOUT1

AOUT2

BOUT2

AOUT3

BOUT3

AOUT1

BOUT1

AOUT2

BOUT2

G16-RR2-1

G14-RR5-1

G11-RR7-1

G21-RR4-2

G24-RR4-1

G04-RR0-6G21-RR4

BACK PP-2 BACK PP-2 BACK PP-2FRONT PP

PP-DModule

BLLRF-4

BACK PP-2 BACK PP-2 BACK PP-2

H(S,L) 16 ~ 19V(S,L) 16 ~ 19

H(S,L) 12 ~ 15V(S,L) 12 ~ 15

H(S,L) 08 ~ 11V(S,L) 08 ~ 11

H(S,L) 20 ~ 23V(S,L) 20 ~ 23

H(S,L) 24 ~ 03V(S,L) 24 ~ 03

H(S,L) 04 ~ 07V(S,L) 04 ~ 07

West Gallery

East Gallery

LLRF Room

Cables to 48 correctors from LLRF room(K. Triplett, D. Dick)

Test stand at LLRF room(K. Triplett, T. Boes)

ADC

DAC

FPGA

DSP

MFC board (AD/LLRF)TCLK decoder on FPAG (AD/Control)

MFC board I/O (1)(C. Drennan)

4 channel outputs with 0-700mV

DIGITAL INPUTTCLK BdotBooster RF pulseMI RF pulseOAA

DIGITAL OUTPUTTrigger to nocher

DAC OUTPUTOffset to correctorRPOS

Buffer ampgain

offset

Digital I/OTo

Harting connector(LVDS)

RFTo

pulse

MFC board I/O (2)

Digital inputTo

Harting connector

RFTo

pulse

New Booster LLRF board(C. Drennan)

Booster cycle

Intensity

B field

1st pulse 2nd pulse

Notch @ 400msec @ 7msec

The notch was created at 7msec for the 2-12th pulse.Creating the notch at lower energy can reduce beam loss in the Booster.

35000000

40000000

45000000

50000000

55000000

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

rf f

req

uen

cy[H

z]

B[T

]

time[sec]

Total bucket counts during Booster cycle

The bending field in the Booster, injection energy, timing, rf feedback …..are changing from pulse to pulse and bucket position at extraction is not constant.

0

500000

1000000

1500000

2000000

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035In

teg

rate

d r

f b

uc

ket

[bu

cke

ts]

time [sec]

0

500000

1000000

1500000

2000000

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

-80

-60

-40

-20

0

20

40

60

80

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

B=a0-a1*cos(2*pi*freq_cyc+del_t)

dt=+0.1msecdt=+0.2msecdt=+0.5msecdt=-0.1msecdt=-0.2msecdt=-0.5msec

[bu

cket

s]

time[sec]

-80

-60

-40

-20

0

20

40

60

80

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

B=a0-a1*cos(2*pi*freq_cyc*(1+del_f))

freq+0.01%freq+0.02%freq+0.05%freq-0.01%freq-0.02%freq-0.05%

[bu

cke

ts]

time[sec]

Final bucket position

Difference of bucket count between reference cycle and a cycle with B field error.

∑𝑛=0

𝑁

(Bucket _current   cycle    – Bucket _ reference   )

∑𝑛=0

𝑁

∆𝐵𝑢𝑐𝑘𝑒𝑡

Turn Number

DAC output on $19

Beam study on $17$12 $17 $17 $17 $17

57 bucket /div

Fixed with RPOS feedback

Changed by dipole correctorDipole corrector: 0.009[T-m] @ 24.4[A]

B field error ~1% can be compensated.

Magnetic cogging

B+dB

Keeps the orbit centered and saves aperture. Has two feedback loops for frequency and RPOS .

(Assuming 10[A] change )

Beam study on $17(1)

w/o dipole corrector with

Beam study on $17(2)

Corrector current Orbit difference

Data on JAVA application(A. Waller)

4 array data from memory

Dbuckets compensation with RPOS cogging and Magnetic cogging

-5

0

5

10

15

20

-5

0

5

10

15

20

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035

RF cogging

Momentum cogging

[bu

ck

ets

/mm

/ms

ec

] [bu

ck

ets/A

/mse

c]

time[sec]

Plans

Beam studies on $17 and optimize gain.

Combine MCOG( before transition) and RCOG (after) on MFC board.

Creating the notch at 1msec.