a high step-up converter with voltage 2011

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Abstract-- A novel high step-up converter is proposed for a front-end photovoltaic system. Through a

voltage multiplier module, an asymmetrical interleaved high step-up converter obtains high step-up gain

without operating at extreme duty ratio. The voltage multiplier module is composed of a conventional

boost converter and coupled inductors. An extra conventional boost converter is integrated into the first

phase to achieve a considerably higher voltage conversion ratio. The two-phase configuration not only

reduces the current stress through each power switch, but also constrains the input current ripple, which

decreases the conduction losses of MOSFETs. In addition, the proposed converter functions as an active

clamp circuit, which alleviates large voltage spikes across the power switches. Thus, the low-voltage-rated

MOSFETs can be adopted for reductions of conduction losses and cost. Efficiency improves because the

energy stored in leakage inductances is recycled to the output terminal. Finally, the prototype circuit with a

40- V input voltage, 380- V output, and 1000- W output power is operated to verify its performance. The

highest efficiency is 96.8%.

Index Terms-- Photovoltaic system, voltage multiplier module, boost-flyback converter, high step-up.

I. INTRODUCTION

ENEWABLE sources of energy are increasingly valued worldwide because of energy shortage and

environmental contamination. Renewable energy systems generate low voltage output; thus, high step-up

dc/dc converters are widely employed in many renewable energy applications, including fuel cells, wind

power, and photovoltaic systems [1]-[8]. Among renewable energy systems, photovoltaic systems are

expected to play an important role in future energy production [9]-[17]. Such systems transform light

K. C. Tseng, C. C. Huang, and W. Y. Shih

A High Step-Up Converter with Voltage

Multiplier Module for Photovoltaic System

R



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energy into electrical energy, and convert low voltage into high voltage via a step-up converter, which can

convert energy into electricity using a grid-by-grid inverter or store energy into battery set. Fig. 1 shows a

typical photovoltaic system that consists of a solar module, a high step-up converter, a charge-discharge

controller, a battery set, and an inverter. The high step-up converter performs importantly among the

system because the system requires a sufficiently high step-up conversion.

Fig. 1. Typical photovoltaic system.

Theoretically, conventional step-up converters, such as the boost converter and flyback converter, cannot

achieve an high step-up conversion with high efficiency because of the resistances of elements or leakage

inductance. Thus, a modified boost-flyback converter was proposed [18]-[20], and many converters that

use the coupled inductor for a considerably high voltage conversion ratio were also proposed [21]-[25].

Despite these advances, conventional step-up converters with single-switch are unsuitable for high-

power applications given an input large current ripple, which increases conduction losses. Thus, numerous

interleaved structures and some asymmetrical interleaved structures are extensively used [26]-[33]. The

current study also presents an asymmetrical interleaved converter for high step-up and high-power

application.

Modifying a boost-flyback converter, shown in fig. 2(a), is one of the simple approaches to achieving

high step-up gain; this gain is realized via a coupled inductor. The performance of the converter is similar

to an active-clamped flyback converter; thus, the leakage energy is recovered to the output terminal [20].



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An interleaved boost converter with a voltage-lift capacitor shown in fig. 2(b) is highly similar to the

conventional interleaved type. It obtains extra voltage gain through the voltage-lift capacitor, and reduces

the input current ripple, which is suitable for power factor correction (PFC) and high-power applications,

[34].

(a) (b)

Fig. 2. High step-up techniques based on classical boost converter. (a) Integrated flyback-boost converter structure. (b)

Interleaved boost converter with voltage-lift capacitor structure.

In this paper, an asymmetrical interleaved high step-up converter that combines the advantages of the

above-mentioned converters is proposed, which combined the advantages of both. In the voltage multiplier

module of the proposed converter, the turns ratio of coupled inductors can be designed to extend voltage

gain, and a voltage-lift capacitor offers an extra voltage conversion ratio.

The advantages of the proposed converter are as follows:

1) The converter is characterized by a low input current ripple and low conduction losses, making it

suitable for high-power applications.

2) The converter achieves the high step-up voltage gain that renewable energy systems require.

3) Leakage energy is recycled and sent to the output terminal, and alleviates large voltage spikes on the

main switch.



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4) The main switch voltage stress of the converter is substantially lower than that of the output voltage.

5) Low cost and high efficiency are achieved by the low rDS(on) and low voltage rating of the power

switching device.

II. OPERATING PRINCIPLE DESCRIPTION

The proposed high step-up converter with voltage multiplier module is shown in Fig. 3(a). A

conventional boost converter and two coupled inductors are located in the voltage multiplier module,

which is stacked on a boost converter to form an asymmetrical interleaved structure.

(a) (b)

Fig. 3. (a) The proposed high step-up converter with voltage multiplier module. (b) Equivalent circuit of the proposed converter.

Primary windings of the coupled inductors with Np turns are employed to decrease input current ripple,

and secondary windings of the coupled inductors with Ns turns are connected in series to extend voltage

gain. The turns ratios of the coupled inductors are the same. The coupling references of the inductors are

denoted by „.‟ and „*‟ in Fig. 3.

The equivalent circuit of the proposed converter is shown in Fig. 3(b), where Lm1 and Lm2 are the

magnetizing inductors, Lk1 and Lk2 represent leakage inductors, S1 and S2 denote power switches, Cb is the



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voltage-lift capacitor, and n is defined as turns ratio Ns/Np .

The proposed converter operates in continuous conduction mode (CCM), and the duty cycles of the

power switches during steady operation are interleaved with a 180-degree phase shift; the duty cycles are

greater than 0.5. The key steady waveforms in one switching period of the proposed converter contains six

modes, which are depicted in Fig. 4, and Fig. 5 shows the topological stages of the circuit.

Fig. 4. Steady waveforms of the proposed converter at CCM.

Mode 1 [to, t1]:

At t=t0, the power switches S1 and S2 are both turned on. All of the diodes are reversed-biased.



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Magnetizing inductors Lm1 and Lm2, as well as leakage inductors Lk1 and Lk2, are linearly charged by input

voltage source Vin.

Mode 2 [t1, t2]:

At t=t1, power switch S2 is switched off, thereby turning on diodes D2 and D4. The energy that

magnetizing inductor Lm2 has stored is transferred to secondary side charging output filter capacitor C3. The

input voltage source, magnetizing inductor Lm2, leakage inductor Lk2, and voltage-lift capacitor Cb release

energy to output filter capacitor C1 via diode D2, thereby extending the voltage on C1.

Mode 3 [t2, t3]:

At t=t2, diode D2 automatically switches off because the total energy of leakage inductor Lk2 has been

completely released to output filter capacitor C1. Magnetizing inductor Lm2 transfers energy to secondary

side charging output filter capacitor C3 via diode D4 until t3.

Mode 4 [t3, t4]:

At t=t3, power switch S2 is switched on and all the diodes are turned off. The operating states of modes 1

and 4 are similar.

Mode 5 [t4, t5]:

At t=t4, power switch S1 is switched off, which turns on diodes D1 and D3. The energy stored in

magnetizing inductor Lm1 is transferred transfer to secondary side charging output filter capacitor C2. The

input voltage source and magnetizing inductor Lm1 release energy to voltage-lift capacitor Cb via diode D1,

which stores extra energy in Cb.

Mode 6 [t5, t0]:

At t=t5, diode D1 is automatically turned off because the total energy of leakage inductor Lk1 has been

completely released to voltage-lift capacitor Cb. Magnetizing inductor Lm1 transfers energy to secondary

side charging output filter capacitor C2 via diode D3 until t0.



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(a) (b)

(c) (d)

(e) (f)

Fig. 5. Operating modes of the proposed converter. (a) Mode 1 [to, t1]. (b) Mode 2 [t1, t2]. (c) Mode 3 [t2, t3]. (d) Mode 4 [t3,

t4]. (e) Mode 5 [t4, t5]. (f) Mode 6 [t5, t0].



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III. STEADY-STATE ANALYSIS

The transient characteristics of circuitry are disregarded to simplify the circuit performance analysis of

the proposed converter in CCM, and some formulated assumptions are as follows:

1) All of the components in the proposed converter are ideal.

2) Leakage inductors Lk1 and Lk2 are neglected.

3) Voltage VCb, VC1, VC2 and VC3 are considered to be constant because of infinitely large capacitance.

A. Voltage gain

The first phase converter can be regarded as a conventional boost converter; thus, voltage VCb can be

derived from

inCb V

DV

1

1 (1)

When switch S1 is turned on and switch S2 is turned off, voltage VC1 can be derived from

inCbinC V

DVV

DV

1

2

1

11

(2)

The output filter capacitors C2 and C3 are charged by energy transformation from the primary side. When

S2 is in turn-on state and S1 is in turn-off state, VC2 is equal to induced voltage of Ns1 plus induced voltage

of Ns2, and when S1 is in turn-on state and S2 is in turn-off state, VC3 is also equal to induced voltage of Ns1

plus induced voltage of Ns2. Thus, Voltages Vc2 and Vc3 can be derived from

2 3 (1 )1 1

C C in in

D nV V n V V

D D

(3)

The output voltage can be derived from

inCCCo V

D

nVVVV

1

22321

(4)

The voltage gain of the proposed converter is

D

n

V

V

in

o

1

22 (5)



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Equation (5) confirms that the proposed converter has a high step-up voltage gain without an extreme

duty cycle. The curve of the voltage gain related to turns ratio n and duty cycle is shown in Fig. 6. When

the duty cycle is merely 0.6, the voltage gain reaches 10 at a turns ratio n of 1; the voltage gain reaches 30

at a turns ratio n of 5.

Fig. 6. The voltage gain versus turns ratio n and duty cycle.

B. Voltage stresses on semi-conductor components

The voltage ripples on the capacitors are ignored to simplify the voltage stress analyses of the

components of the proposed converter.

The voltage stresses on power switches S1 and S2 are derived from

1 2

1

1S S inV V V

D

(6)

The voltage stresses on the power switches S1 and S2 related to the output voltage Vo and the turns ratio n

can be expressed as

inoSS VD

nVVV

1

1221

(7)

Equations (6) and (7) confirm that low-voltage-rated MOSFETs with low RDS-ON can be adopted for the

proposed converter to reduce conduction losses and costs. This feature makes our converter suitable for

high step-up and high-power applications. The voltage stresses on the power switches account for half of

output voltage Vo, even if turns ratio n is 0.



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The voltage stress on diode D1 is equal to VC1, and the voltage stress on diode D2 is voltage VC1 minus

voltage VCb. These voltage stresses can be derived from

inCD VD

VV

1

211

(8)

inCbCD V

DVVV

1

112

(9)

The voltage stresses on the diodes D1 and D2 related to the output voltage Vo and the turns ratio n can be

expressed as

inoD VD

nVV

1

21

(10)

inoD V

D

nVV

1

122

(11)

The voltage stresses on diodes D1 and D2 are close on power switches S1 and S2. Although the voltage

stress on diode D1 is larger, it accounts for only half of output voltage Vo at a turns ratio n one of 1. The

voltage stresses on the diodes are lower as the voltage gain is extended by increasing turns ratio n.

The voltage stresses on diodes D3 and D4 both equal the VC2 plus VC3, which can be derived from

inDD V

D

nVV

1

243

(12)

The voltage stresses on the diodes D3 and D4 related to the output voltage Vo and the turns ratio n can be

expressed as

inoDD VD

VVV

1

243

(13)

Although the voltage stresses on the diodes D3 and D4 increase as the turns ratio n increases, the voltage

stresses on the diodes D3 and D4 are always lower than the output voltage.

The relationship between the voltage stresses on all the semi-conductor components and the turns ratio n

is illustrated in Fig. 7.



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Fig. 7. The voltage stresses on semi-conductor components versus turns ratio n.

C. Analysis of conduction losses

Some conduction losses are caused by resistances of semi-conductor components and coupled inductors.

Thus, all the components in the proposed converter are not assumed to be ideal, except for all the

capacitors. Diode reverse recovery problems, core losses, switching losses, and the ESR of capacitors are

not discussed in this section. The characteristics of leakage inductors are disregarded because of energy

recycling. The equivalent circuit, which includes the conduction losses of coupled inductors and semi-

conductor components, is shown in Fig. 8, in which rL11 and rL21 are the copper resistances of primary

windings of the coupled inductor; rL12 and rL22 are the copper resistances of secondary windings of the

coupled inductor; rDS1 and rDS2 denote the on-resistance of power switches; VD1, VD2, VD3, and VD4 denote

the forward biases of the diodes; and rD1, rD2, rD3, and rD4 are the resistances of the diodes.



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Fig. 8. The equivalent circuit including conduction losses of coupled inductors and semi-conductor components.

Small-ripple approximation was used to calculate conduction losses. Thus, all currents that pass through

components were approximated by the DC components. The magnetizing currents and capacitor voltages

are assumed constant because of the infinite values of magnetizing inductors and capacitors. Fig. 9 shows

the PWM signals of S1 and S2. The equivalent operation states, including the four modes, are shown in Fig.

10.

Fig. 9. PWM signal of the S1 and S2.

Mode 1 [0, (D-0.5)]:

In this mode, power switches S1 and S2 are turned on, and diodes D1, D2, D3, and D4 are turned off. The

equivalent circuit is shown in Fig. 10(a), and the following equations can be derived:



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11111 )( LmDSLLmin VrrIV

(14)


(15)

Mode 2 [(D-0.5), 0.5]:

In this mode, power switch S2 is turned off, and diodes D2 and D4 are turned on. The equivalent circuit is

shown in Fig. 10(b), and the following equations can be derived:

111141 )()( LmDSLDLmin VrrnIIV

(16)

12

222142

)()(

CCbD

LmDLDLmin

VVV

VrrnIIV

(17)

4

422214213

)()(

D

DLLDLmLmC

V

rrrIVVnV

(18)

Mode 3 [0.5, D]:

This mode is similar to mode 1. The equivalent circuit is shown in Fig. 10(c), and the following equations

can be derived:


(19)


(20)

Mode 4 [D, 1]:

In this mode, power switch S1 is turned off, and diodes D1 and D3 are switched on. The equivalent circuit

is shown in Fig. 10(d), and the following equations can be derived:

221

22132

)(

)(

DSLmLm

LmLDLmin

rII

VrnIIV

(21)

CbDDSLmLm

LmDLDLmin

VVrII

VrrnIIV

1221

111131

)(

)()(

(22)

3

322213122

)()(

D

DLLDLmLmC

V

rrrIVVnV

(23)

The average currents that pass through diodes D1, D2, D3, and D4 can be derived by capacitor charge

balance.



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In modes 1 and 3, both switches are turned off, and the average current that passes through output filter

capacitors C1, C2, and C3 are

o

oCCC

R

VIII 321

(24)

In mode 2, the average currents that pass through output filter capacitors C1 and C3 are

o

oDC

R

VII 21

(25)

o

oDC

R

VII 43

(26)

In mode 4, the average currents that pass through output filter capacitor C2 are as follows:

o

oDC

R

VII 32

(27)

The average currents that pass through diodes D2, D3, and D4 can be derived from

o

oDDD

RD

VIII

)1(432

(28)

In mode 2, ICb is equal to ID2; in mode 4, ICb is equal to the negative of ID1. Thus, the average current that

passes through diode D1 can be derived as follows:

o

oD

RD

VI

)1(1

(29)

In mode 4, the average value of ILm1 can be derived thus:

o

oDDLm

RD

VnnIII

)1(

)1(311

(30)

In mode 2, the average value of ILm2 can be derived by

o

oDDLm

RD

VnnIII

)1(

)1(422

(31)

The voltage conversion ratio with conduction losses can be derived from

)1(

])21[(

)1(

)12()1(1

)(1

1

22

2

2

2

4321

DR

rrn

DR

rDn

VVVVVD

n

V

V

o

YX

o

X

DDDD

in

in

o

(32)



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where

22L21L12L11LX rrrrr

4321

2112222111

)(2

DDDD

DSDSLLLLY

rrrr

rrrrrrr

Because the turns ratio and copper resistances of the secondary windings of the coupled inductors are

directly proportional, the copper resistances of the coupled inductors can be expressed as

21221112 ; LLLL rnrrnr

Efficiency is expressed as follows:

)1(

])21[(

)1(

)12()1(1

)()22(

)1(1

2

2

2

4321

DR

rrn

DR

rDn

VVVVnV

D

o

YX

o

X

DDDD

in

(33)

(a) (b)



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(c) (d)

Fig. 10. Equivalent operating modes with conduction losses states. (a) Mode 1 [0, (D-0.5)]. (b) Mode 2 [(D-0.5), 0.5]. (c) Mode

3 [0.5, D]. (d) Mode 4 [D, 1].

On the basis of (33), we infer that the efficiency will be higher if the input voltage is considerably higher

than the summation of the forward bias of all the diodes, or if the load is substantially larger than the

resistances of coupled inductors and semi-conductor components.

The calculated voltage gain and efficiency with different copper resistances are shown in Fig. 11, and

rL11 and rL21 is defined as rL. The other parameters in (33) are set as follows

1) Input voltage Vin : 40V

2) Turns ratio n :1

3) Load Ro : 200 ohm

4) On-resistances of switches rDS1 and rDS2 : 0.021ohm

5) Resistances of diodes rD1, rD2, rD3 and rD4 : 0.01ohm

6) Forward bias of diodes VD1, VD2, VD3 and VD4 : 1V

7) Copper resistances of secondary windings of coupled inductors rL12 and rL22 = rL at a turns ratio n of 1.

Fig. 11 reveals that efficiency and voltage gain are affected by the various coupled inductor winding

resistors and duty cycle, and that efficiency is decreased by the extreme duty ratio.



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This chapter provides important information on voltage gain, voltage stresses on semi-conductor

components, and analysis of conduction losses, which indicates the relationship among duty cycle, turns

ratio, and components. The proposed converter for each application can be designed on the basis of

selected turns ratios, components, and other considerations.

Fig. 11. Calculated voltage gain and efficiency with different copper resistances.

D. performance comparison

For demonstrating the performance of proposed converter, the proposed converter is compared with

other high step-up interleaved converters introduced in [30], [33] as shown TABLE I.

The high step-up interleaved converter introduced in [30] is also suitable as a candidate for high step-up,

high power conversion of the PV system, and the other high step-up interleaved converter introduced in

[33], which is an asymmetrical interleaved structure as proposed converter, is favorable for DC-Microgrid



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applications. Both of converters use coupled inductor and voltage-doubler to achieve high step-up

conversion.

TABLE I.

Performance conparison of interleaved high step-up converters

For the proposed converter, the step-up gain is highest and the voltage stress on switch is the lowest, as

converter introduced in [30]. Under the turns ratio n designed as less than 2, the highest voltage stress on

diodes of proposed converter is the lowest among the compared converters. In addition, the quantities of

diodes are the least as converter introduced in [33]. Because the components of proposed converter are the

least among the compared converters, the reliability is higher and the cost is lower. Thus, the proposed

converter is suitable for high step-up, high power applications such as PV system.



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IV. DESIGN AND EXPERIMENT OF PROPOSED CONVERTER

A prototype of the proposed high step-up converter with a 40-V input voltage, 380-V output

voltage, and maximum output power of 1 kW is tested. The switching frequency is 40 kHz, and the

corresponding component parameters are listed in Table II for reference.

TABLE II

Converter components and parameters

The design consideration of the proposed converter includes components selection and coupled

inductors design, which are based on the analysis presented in the previous chapter. In the proposed

converter, the values of the primary leakage inductors of the coupled inductors are set as close as

possible for current sharing performance. Due to the performances of high step-up gain, the turns

ratio n can be set 1 for the prototype circuit with a 40- V input voltage, 380- V output to reduce cost,

volume and conduction loss of winding. Thus, the copper resistances which affect efficiency much

can be decreased.

The value of magnetizing inductors Lm1 and Lm2 can be design based on equation of boundary

operating condition, which is derived from

2

( )

(1 )

2( 1)(2 2)

om critical

s

D D RL

n n f

(34)

Where Lm(critical) is the value of magnetizing inductors at boundary operating condition, fs is the

switching frequency, and Ro is load. How to suppress the voltage ripple on the voltage-lift capacitor



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Cb to an acceptable value is the main consideration. The equation versus the voltage ripple and the

output power or output current can be derived by

o ob

o s Cb s Cb

P IC

V f V f V

(35)

Where Po is the output power, Vo is the output voltage, fs is the switching frequency, and △VCb is

the voltage ripple on the voltage-lift capacitor Cb.

Fig. 12. Control strategy for the proposed converter.

In control strategy of proposed converter is implemented by microchip dsPIC30F4011 as shown

in Fig. 12. PV module and battery set are the main input power source, which can be seen as an

equivalent voltage source for the proposed converter, and the MPPT algorithm is employed by

referring [35]. The battery management system (BMS) for Charge/Discharge controller is not the

main priority in this paper thus the related designed is not implemented in the paper.

The output voltage is changed as load shift and the detected feedback signal is processed via

proportional-integral (PI) controller, and the internal comparator generates interleaved PWM with a



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180-degree phase shift. Due to the insufficient voltage of PWM, the PWM are supported by

TC4420 to control power switches, and EL50P1 is a hall sensor to detect the input current for over-

current protection (OCP). The input voltage Vi supplied by PV module and battery set is very nearly

40 V even if the load shift. Thus, the efficiency of the proposed converter under constant input

voltage/constant output voltage can be measured.

(a) (b)

(c) (d)

Fig. 13. Measured waveform at Po=1 kW. (a)Vgs1, Vgs2, iLk1 and iLk2. (b)Vds1, Vds2 and iLs. (c) Vgs1, Vgs2, iD1 and iD2. (d) Vgs1,

Vgs2 , iD1 and iD2.

Fig. 13 illustrates the measured waveforms of Vgs1, Vgs2, iLk1, iLk2, Vds1, Vds2 and iLs at Po = 1kW. In

Fig. 13(b), the switch voltage is clamped at 90 V, which is much smaller than the output voltage

380V. Figs. 13(c) and 13(d) illustrates the measured waveforms of Vgs1, Vgs2, iD1, iD2, iD3 and iD4 at

Po = 1 kW. The measured waveforms are consistent with the steady-state analysis.



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(a) (b)

Fig. 14. Simulation and experimental result of high-voltage storage of capacitor. (a) Simulation result. (b) experimental

result.

Fig. 14 shows the simulation and experimental result of voltage on all capacitor to illustrate the

high voltage storage and theoretical analysis. VC1 is equal to VCb plus output voltage of boost

converter, and VCb is equal to output voltage of boost converter. Thus, VC1 is double of VCb. VC2 is

equal to VC3, both are nearly VCb because turns ratio n is set 1.

6.5

(a) (b)

Fig. 15. Performance of current sharing and dynamic response. (a) Input current ripple, iLK1 and iLK2 at 1000W. (b)

Dynamic response under step load variation between 100 W and 500W.

Fig. 15(a) shows the input current-ripple iin and the currents iLK1 and iLK2 of the primary side of

the coupled inductors at Po=1kW. The peak-to-peak current ripple is about 2A (6%), which

confirms that the input current ripple is very low even if at high-power operation because the

proposed converter has an asymmetrical interleaved structure. Fig. 15(b) shows the dynamic



23

response due to the step load variation between 100 W and 500 W, and the output voltage is 380 V.

Fig. 16. Measured efficiency of proposed converter.

Fig. 17. Prototype photo of the proposed converter.

Fig. 16 shows the measured efficiency of the proposed converter. The maximum efficiency is

96.8% at PO = 400W. At maximum output power, the conversion efficiency is about 96.1%. Fig. 17

shows the prototype photo of the proposed converter.

V. CONCLUSION

This paper has presented the topological principles, steady-state analysis and experimental

results for a proposed converter. The proposed converter has been successfully implemented an

efficiently high step-up conversion without an extreme duty ratio and a number of turns ratios

through the voltage multiplier module and voltage clamp feature. The interleaved PWM scheme



24

reduces the currents that pass through each power switch and constrained the input current ripple by

approximately 6%. The experimental results indicate that leakage energy is recycled through

capacitor Cb to the output terminal. Meanwhile, the voltage stresses over the power switches are

restricted and are much lower than the output voltage (380 V). These switches, conducted to low

voltage rated and low on-state resistance MOSFET, can be selected. Furthermore, the full-load

efficiency is 96.1% at Po =1000 W, and the highest efficiency is 96.8% at Po = 400 W. Thus, the

proposed converter is suitable for PV systems or other renewable energy applications that need high

step-up high-power energy conversion.

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