A Front-end Circuit for Full-duplex Transmission over Coaxial Cable

Rajeevan Mahadevan

A thesis submitted in confonnity with the requirements for the degree of Master of Applied Science

Department of Electrical and Cornputer Engineering University of Toronto

O Copyright by Rajeevan Mahadevan 1999

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A Front-end Circuit for Full-duplex Transmission over Coaxial Cable

Rajeevan Mahadevan Deparanen t of Electrical and Cornpu ter Engineering

University of Toronto Degree of Master of Applied Science, 1999

Abstract

The main impairment in full-duplex transmission is the near-end echo. To remove this echo, a fine driver

with good Linearity and a high-speed analog-to-digital converter with good tesolution are required. Analog

echo cancellation can reduce the linearity and resolution requirements. However, the choice of a voltage-

mode or current-mode Iine driver affects both the implementation and effectiveness of analog echo cancel-

Iation for high-speed applications. This research proposes a front-end with a current-mode line driver and

embedded analog echo canceliation. A wide-band differential Line driver for transformer-coupled coaxial

cabtes is designeci in standard 0.35~ CMOS. It achieves 160MHz bandwidth and no loss in implementing

the cable termination. The Line driver operates at 3.3V supply and exhibits a -50dB THD for a I .6VPP sig-

nal across a 75 ohm load- Automaticaliy tuned termination and a voltage gain independent of process and

load impedance variation are provided by the architecture. In addition, the front-end achieves better than

15dB of analog echo cancellation up to 20MHz.

Acknowledgments

1 would iike to thank my supervisor, Dr. David Johns, for his guidance and support throughout this work.

His ability to provide time regardless of his busy schedule has aiways k e n well appreciated.

I would also like to thank Dr. Ken Martin and Dr. John Long. I thank Dr, Martin for his valuable comments

and for reviewing rny conference paper submission. 1 thank Dr, Long for the interesting discussions, both

technical and nontechnical, and for his assistance in obtaining test equipment.

1 am in debt to Gennum Corporation for assisting me in obtaining the NSERC Industrial Postgraduate

Scholarship. In particular, 1 would like to express my gratitude to David Lynch for his quick action in

securing funding for this work. Also, my thanks to Atul Gupta for encouraging me to pursue graduate stud-

ies.

To my colleagues in EA104, 1 want to thank you for providing a stimulating work environment. Tbanks

Amir, Anas, Angus, Anthony, Bahram, Cameron, Dickson, Khoman, James, Sebastian, Shahriar, Steve,

Takis, and Vasilis. Cameron and Steve, it has been good to share the experience with you guys over the

past two years. Khoman, thanks for your help in both technicd and nontechnical matters. Takis, thanks for

your friendship and for ail the interesting discussions.

Two other people in my iife have k e n instrumental in accompiishing this endeavor- My parents have made

numerous sacrifices to ensure that I had the opportunity to get an education. It is for them that 1 dedicate

this work and thank them for al1 that they have done for me. Finaily, 1 wish to thank my nephews and

nieces for reintroducing this world in a delightful way and for making me realize how far 1 have corne.

iii

CHAPTER 1 . Motivation and State of the Art ...................................................................................................... 1.1 Introduction and Motivation 1

1.2 State of the Art ........................................................................................................................... ..4

i . 3 Thesis Outline ........................................................................................................................ ......5

CHAPTER 2 . System Modeling 2 . i htroduction .................................................................................................................................. 6

2.2 Cable Modeling .......................................................................................................................... ..6

.............................................................................................................. 2.3 Transformer ModeIing 11 .................................................................................... 23.1 Ideal Transformer Roperties 11

............................................................................................... 2.3.2 Practical Transformer 13

2-4 Echo Path Transfer Function ..................................... .... .................................................... 19

................................................................................................................................. 2.5 Conclusion 23

CHAPTER 3 . Front-end Architecture 3.1 Introduction ................................................................................................................................ 24

.......................................................................................................................... 3.2 Cable Coupling 24

3.3 Line Driver Topology ................................................................................................................. 25 3.3.1 Voltage-mode Line Driver ........................................................................................ S5

........................................ 3.3.2 Current-mode Line Driver ................................... .... 27

............................... .............................................*...................*....................... 3.5 Conclusion .............. 31

CHAPTER 4 . Circuit Integration ................................................................................................................................ 4.1 Introduction 32

4.2 Line Driver ................................................................................................................................. 33 4.2.1 Half-circuit Design ................................................................................................ -37

................................................................................................. 4.2.2 Current Gain Tuning 42 .................................................................... 4.2.3 Output Cornmon-mode Tuning Circuit 43

4.3 Tuning Circuit ............................................................................................................................ 46 4.3.4 Transconductor Design ............................................................................................. 48

........................................................................... 4.35 Differencer and Bandpass Filter - 3 1 4.3.6 Comparacor ........................................................................................................... ....53 4.3.7 Digital Circuits ........................................................................................................ -55

.......................................................................................................................... 4.3.8 DAC 56 4.3.9 Simulation ................................................................................................................. 56

4.4 Bias Circuit ................................................................................................................................ 57

4 5 Layout and Pac kaging Considerations ....................................................................................... 58

................................................................................................................................. 4.6 Conclusion 61

5 . 1 Introduction ................................................................................................................................ 62

.......................................................................................................... 5.2 Line Driver Performance 62

....................................................................................................... 5.3 Tuning Circuit Performance 70

CHAITER 6 . Summary and Future Research 6.1 Summary and Conclusions ......................................................................................................... 73

6.2 Suggestions for Future Research ................................................. ... ............... 74

Appendix A . Distortion in Half-Circuit A . 1 Introduction ............................................................................................................................... 76

A.2 Distortion Analysis .................................................................................................................... 76

References .......................................................................................................................................................... 80

CHAPTER Motivation and State of the Art

1.1 Introduction and Motivation

An area receiving significant attention both from academia and industry is data communication over wired

channels such as coaxial and twisted-pair cables. Great effort is being placed at pushing data transmission

rates over these channels to near the Shannon limit- This has been in response to the growing demands for

greater information throughput The proliferation of computer local area networks (LANs), for example,

has been one of the major contributors for the explosion in the demand for high speed communication.

Some specific application examples in networking, where distances are typically limitai to 100 meters of

twisted-pair (TP) cables, include Token ring (full-duplex 16Mbps over 4 wire TP), Fast Ethernet (full-

dupIex up to IOOMbps over 4 wire TP), ATM-UNI (asynchronous transfer mode user-network interface,

fuil-duplex 25- 155Mbps over 4 wire TP), and FDDI (fiber distributed data interface, fuil-duplex I25Mbps

over 4 wire TP). However, these existing systems are reaching saturation with today's high throughput

intensive applications iike imaging, real-time video, video conferencing, and multimedia This need for

higher data throughput is the reason why the Gigabit Ethemet standard was recently introduced. This stan-

dard calls for full-duplex transmission of up to lOOOMbps over 8 wire TI? Another application area is the

transmission of serial digital video over coaxial cable in broadcast studios. Here, up to 622Mbps is

required (half-duplex) over a single 300 meter coaxial cable. Even in this application, the recent introduc-

CHAPTER 1 - Motivation and Statu of the Art

tion of High-Definition Television (HDTV) format has placeci demand for 1SGbps over lû0m of coaxial

To meet these demands transmission schemes have been developed that require sophisticated transceiver

circuits. The main blocks of a generic full-duplex transceiver are shown in Figure 1.1 [Johns 97bl. The

transmit digital-to-anaiog converter (DAC) is used to convert digital levels to a suitable analog signal. A

Line driver is used to supply the necessary power gain to drive the cable, The 2-4 wire hybrid performs the

initial directional separation between the transmitted signai and the received far-end signai. However, pprac-

tical hybrid circuits only partiaIly remove the transmitted signal. As a result, the received signal (Rx) is

heavily compted with the transmitted echo signal- The receive analog-to-digital converter (ADC) converts

this signal to a digital signal- A digital echo canceler is used to eiiminate the residual transmit signal on the

receive path due to the non-ided hybrid- Finally, ciock-recovery and equalization is performed on the

received signal to detennine the correct timing information and remove inter-symbol interference.

Although the impfementation varies depending on the application, some or most of the common blocks

shown exist in al1 systems.

+ cable

echo 2 4 wire, canceler hybrid

d

receive equaiization k 4

receive ADC

. 4

transmit (1 of N levels)

I '

Figure 1.1: The main blocks of a full-duplex transceiver

One of the main impairments in this architecture is the near-end echo due to the non-ideal hybrid. This

echo heavily compts the received signai. To successfully achieve the required signal-to-noise ratio, the

number of bits required for the ADC must be larger than in the case when there is no echo. At high speeds,

ADCs have to use the flash or interpolating/folding architectures. As a result, each additional bit requires a

7 T x line

ciriver transmit

DAC *

CHAPTER 1 - Motivation and State of the Art

doubling in the power and area of the ADC. In addition, a digital echo canceling circuit is required. This is

typicdly implemented as a fi nite impulse rsponse (FJR) filter (30-60 taps). Since this is a linear filter, it

can only cancel the linear cornponents in the echo. Any non-linearities inaoduced in the echo path cannot

be removed. This places stringent requirements on the linearity performance of the blocks in the echo path.

The blocks that must meet these requirernents are the DAC, line driver, hybrid, and receive ADC. Among

these blocks, the line driver is the prirnary source of non-iinearity. It must produce large output signais (up

to 2Vpp) from a low supply voltage (3.3V) while maintainhg high bandwidth and good lineacity. This

makes the design of this btock a chaltenging task especidly in a CMOS technology.

The focus of this thesis is the design of a CMOS front-end, namely the line driver and hybnd. Approaches

for improving the echo loss prior to the ADC (called the transhybrid loss) will be explored. One technique

is to use an analog echo canceler as shown in Figure 1.2. An anaiog adaptive Nter is used to match the

echo path transfer function better and hence irnprove the transhybrid loss. The benefits of improving the

transhybrid loss by analog echo cancellation are significant in the ideal case. First, if sufficient echo can be

removed, the number of bits in the ADC can be reduced Ieading to significant power savings. In addition,

the line driver linearity requirernents can be reduced. This reduction occurs because the anaiog echo can-

celer sarnples the output of the line driver including any non-linearities and subtmcts these terms out prior

to the receive ADC. However, in practice, the choice of the line dnver topology, voltage-mode or current-

mode, affects both the implementation and effectiveness of analog echo cancellation. These issues wiil be

Figure 1.2: The concept of analog echo canceilation

transmit ( 1 of N levels) transmit DAC

w r - = - T w

I

-b

cable , O

line driver

I

2 4 wire hybrid

echo canceler

I Analog 1 1 echo 1 1 canceter 1

,,,ive equdization 2 L - ~ - J Rx

, Tx

- c-04 4

m 4

re=

CHAPtER 1 - Motivation and State of îhe Art

explored in this thesis. Based on this analysis, a state of the art line driver topology with embedded echo

canceilation will be presented, The target application for the work presented is the serial digitai vidw

transmission of up to 622Mbps over a 30m coaxial cable using a multilevel carrierless AM/PM (CAP)

modulation scheme, However, the concepts presented can be modifieci for use in the emerging Gigabit

Ethemet applications.

Current solutions for serial digital video are multi-chip solutions in 5V Bipolar or BiCMOS processes

using NRZI (non-retum to zero inverted) signailing [Genlinx 99][Comlinear 993. These solutions are haif-

duplex and conform to the SMPïE 259M and 292M (The Society of Motion Pictnre and Television Engi-

neers) standards [SMFïE 931 [SMFE 961. The main thmst for a CMOS implementation is the reduction

of cost due to higher integration. in addition, full-duplex transmission can be obtained with the sophisti-

cated digital signal processing available in CMOS. However, the existing standards do not address these

issues. With this in min& this thesis assumes the use of a multilevel CAP modulation scheme Werner 921

[Abdolhamid 981. A multilevel modulation scheme is a key requirement for achieving the required speeds

in CMOS. The advantage of using a CAP modulation scheme is that the frequencies used can be shifted

away from DC to help with echo cancellation as discussed in Chapter 2.

1.2 State of the Art

In this section, we review the recent contributions to the area of line cirivers, hybrids, and analog echo can-

cellation. The discussion is focused mainly on CMOS implementations.

In pveritt 981, a 0.35~ CMOS current-mode iine driver for Fast Ethernet applications is described. Two

large comrnon-source transistors are used to drive the cable differentiaüy in a class-A configuration. A

fixed extemal resistor is used for termination. The driver is able to produce 2Vpp across a 1ûûQ load. No

other specific performance resuits are given as the driver is part of a bigger transceiver chip.

In Daum 981, an adaptable fine driver in 0-3Sp CMOS witb no loss in the termination is presented. A tun-

able output impedance and voltage gain are also provided by the driver. It is able to produce I.2Vpp across

7 5 a with less than -50dB total harmonic distortion (THD). The achîeved bandwidth is 130MHz However,

the presented architecture is for DC-coupled loads and is single-ended.

CHAPTER 1 - Motivation and State of the Art

In pabanezhad 991, a voltage-mode fine driver in 0 . 4 ~ CMOS is describeci. A current-feedback amplifier

along with a class-AB output stage is used to produce NPp across lOOQ from a 3.3V supply. A bandwidth

of 107MHz and a -45dB THD are acbieved, The dnver is for Ethemet and Fast Ethernet applications,

The majority of the remaining line drivers are reported in a variety of vendor data sheets ~roadcom 981

D v e l One 981, where design details are not disclosed, However, most of the implementations use a cur-

rent-mode output stage with an extemal parallel resistor for termination.

In medey 981 and Wvi 991, a magnetic hybrid and a resistive hybrid are proposed to improve echo loss

for Gigabit Ethernet The magnetic hybrid uses a comptex transformer arrangement to cancel the near-end

echo. The resistive hybrid reiies on an impedance balancing bridge to perfonn the canceuation. No perfor-

mance data are given as these are proposais.

In [Pecourt 991, an integrated adaptive analog hybrid for Asymmetrical Digital Subscriber Loop (ADSL)

modems is presented. A second order analog adaptive filter is used to match the echo path transfer function

over al1 cable variations. Integrated in O.6p BiCMOS, the filter achieves 26dB of echo cancellation and

reduces the resolution needed in the ADC by more than 2bits. A multiple input, multiple f d b a c k 3-

opamp biquad with discrete tuning using a 5bit DAC is utiiized for the filter- The bandwidth required for

this application is Iess than 4ûûkHz. However, a distortion better than 80dB is achieved.

1.3 Thesis Outtine

Chapter 2 provides some background information needed to mode1 the coaxial cable and transformer.

Based on this theory, the echo path transfer function is modeled and analyzed-

Chapter 3 considers the front-end architecture. In particular, the advantages of different Iine dnver topolo-

gies and their impact on analog echo cancellation are considered. Finaiiy, a front-end topology with analog

echo cancellation is proposed.

In Chapter 4, the circuit integration of the proposed front-end is described. The design of an adaptive tine

driver for transformer-coupled channels is described and the various trade-offs are anaiyzed.

Chapter 5 presents the experimental results for the prototype front-end.

In Chapter 6, a summary of the thesis contributions is given and suggestions are made for M e r research.

CHAPTER System Modeling

- - - -

2.1 Introduction

This chapter presents the theory used to mode1 the echo path aansfer function. To consider ways of maxi-

rnizing the transhybrid loss, the echo path ûansfer function must be well undentood. The transfer function

is affecteci by the input impedance of the cable and by the parasitics of the transformer used for AC-cou-

pling. The cable can be modeled by transmission Line theory and this is presented in Section 2.2. An equiv-

dent circuit cm be developed for the transformer by considering its consaiction and this is presented in

Section 2.3. In addition, the properties of a center-tapped transformer are reviewed as these wiil be used

extensively in the design of the front-end in subsequent chapters.

2.2 Cable Modeling

A coaxial cable consists of an inner conductor and a coaxial outer conducting sheath separated by an insu-

lating layer (dielectric medium) as depicted in Figure 2.1. The outer conductor is often much thicker than

the inner conductor and the entire structure is covered with a jacket for mechanical strength and isolation.

This coaxial structure has the important advantage of confining the electric and magnetic fields entirely

within the dielecûic region. No stmy fields are generated and little external interference is coupled into the

line. Some common materials used for the dielectric iayer are Polyethylene, Polypropylene, and Tefion.

The Belden 828 1 precision analog and digital video coaxial cable considered in this thesis uses copper con-

CHAPTER 2 - Systern Modeling

ductors and Polyethylene dielectric material. Some of the cable's characteristics

2.1 iBeIden 981.

are summarized in Table

Jacket

Outer Conductor

Inner Conductor

Dielectric

Figure 2.1: Cross section of a coaxial cable

Table 2.1: Belden 828 1 cabte characteristics

P-ter Dimensions

Dielectric Roperties

Since the coaxial cable can be up to 300m in length, it consists of many wavelengths of the transniitred sig-

nal and hence must be modeled as a transmission Line. A transmission Line is a disûibuted-parameter net-

work and is described by circuit parameters that are distnbuted throughout its length. A differentid leneh

segment (dz) of a transmission line c m be described by the following four parameters:

Value

r,=0.39mm r b = 2 5 5 m ~ rp2.83mm

PoIyethy lene

R, resistance per unit length (both conductors), in W m

L, inductance per unit length (both conductors), in Wm

G, conductance per unit length, in Slm

C, capacitance per unit length, in F/m

Figure 2.2 shows the equivalent electric circuit of such a line segment [Cheng 891. These four parameters

can be obtained h m the material properties and their dimensions. The inductance per unit length of a

CHAPTER 2 - System Moâeling

Rdz Ldz

. dz z Figure 2.2: Equivalent circuit of a differential length dz of a transmission line

coaxial transmission Iine with a center conductor of radius r, and an outer conductor of inner radius rb is

given by

where is the permeability of Polyethylene. The capacitance per unit length is

where E is the permittivity of Polyethylene. The conductance per unit length i s given by

where tan 6 is the loss tangent of Polyethylene. The loss tangent is a measure of the power loss in the

dielectnc. For this dielectric, the variation as a function of frequency in capacitance and inductance is

sIight and can be assumed to be constant for practical cases. These parameters are also essentiaüy constant

with respect to magnitudes of voltage and current. As a result, the system is linear and there is no interac-

tion among voltages and currents of different frequencies.

The resistance per unit length, R, is the sum of the resistances due to each of the conductors (% and %).

This resistance exists due to the finite conductivity of copper. At low frequencies, current flows uniformly

across the conductor, and

CHAPTER 2 - System Moâeling

where O, is the conductivity of copper. At high frequencies, there is a non-uniformity of the current density

caused by time-varying magnetic flux within the conductors. This effect is known as the skin effect- R

becomes complex and is given by

where p, is the permeability of copper- This high frequency asymptote is often used in anaiysis but it does

not model the transition region, This region occurs in the frequency band of interest(100kHz to lMHz for a

300m coax). R can be modeled accwately by solving Maxwell's equations with boundary conditions. This

is an involved process and is given in detail in wagnusson 921. The result of this analysis is that R c m be

modeled as

where J,(.) is the Bessel function of the first kind and ELv(@) is the modified bessel function. Both of these

functions are available witfiin MATLAB and can be used to accurately model R over the entire frequency

range Nadab 921.

Along with the primary constants above, the secondary constants, consisting of the characteristic imped-

ance and the propagation constant, are also important. The characteristic impedance is defined as the

impedance seen when looking into an infinitely long cable (with no reflections). It is given by

This is plotted in Figure 2.3 for the Belden cable using the parameters in Table 2.1. At low frequencies, the

characteristic impedance is capacitive and becomes resistive at high frequencies with a value of 75f2 This

implies that when terminating the cable, impedances around 75R should be used.

When properly terminated, the transfer function of a coax cable is modeled by

O = : 7 : : : : . ;;;;:. - . . . . . . . - - .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 0-

. . . . . . , 10- 1 o3 1 0'' 1 O-. 1 o0 1 O' 1 O= 1 O=

Frequency <MHz>

Figure 23: Characteristic impedance of Belden 828 1 cable

H(4 = e"@ = ed-"e4'~' (28)

where H(d,o) is the ûansfer function of the cable, d is the cable length in meters, Ho) is known as the

propagation constant, a is known as the attenuation constant (in units of nepersfm), and is known as the

phase constant (in units of ndiadm). The propagation constant y(a) is given by

y ( o ) = a ( w ) + jp(o) = J(R + joL)(G + jwC) (29)

The attenuation is ploned in Figure 2.4 for a lOOm cable. The measured Belden 981 and simulateci attenu-

ation match to within 0.5dB.

Frsquency (MHz)

Figure 2.4: Attenuation of lOOm of coaxial cable

CHAPTER 2 - Sysîem Modeling

2.3 Transformer Modeling

It is often required chat the voltage in one branch of a circuit induce a voltage in another selected branch

and at the same time isolate the branches- The center-tapped transformer is the widely used means to

accomplish this end. The properties of an ideai transformer and the Limitations of a practical transformer

wil1 be explored in this section.

2.3.1 ldeal Transformer Properties

11 13 + N:I + v3p3 vz - -

12 Figure 25: A center-tapped transformer

Consider the ideal transformer of Figure 2.5 with a N:l turns ratio between each half of the primary and

sccondary winding. Since the transformer is ideal [Smith 981,

I3 = -EJ(I, + 4) (2-1 1)

To evaiuate the properties of this ideal transformer, a 4-port analysis can be done using the configuration

show in Figure 2.6. The three current-Ioop equations are

Figure 2.6: A circuit for analysis of a center-tapped transformer

CHAPTER 2 - System Modeling

E3 = 1 3 5 + V3 Substituting in (2.14) into (2.12) and (2-13), we cm rewrite in matrix fonn as

It is possible to select the impedances (Z1 to &) so that there is isolation beiween selected ports. Often,

port 4 (the center-tap) is isolated from & (secondary side). To do this, the cumnt in Z4 should be zero in

response to E3. The currents II and I2 in response to E3 are given by

where detA is the determinant of matrix A. The current through Z4 in response to E3 is

The center-tap will be isolated if Z I = q and an applied voltage E3 will not develop a voltage across Zq-

Similarly, it is easy to show that ports 1 and 2 are isolated h m each other if

It can also be shown that for maximum power transfer from port 3 [Smith 981

where Z~ * is the complex conjugate of ZI.

In summary, if in an ideal transformer circuit of Figure 2.6

ports 1 and 2 (primary inputs) will be isolated from each other and sirnilarly ports 3 and 4 wiii be isolated

from each other. In addition, ail ports wilt be matched for maximum power transfer. Another important

property of a transformer in this corlfiguration is the current/voltage relationship from ports 1 and 2 to port

3 and port 4. Consider the response I3 to the appiied voltage El and Es. The cumnt I3 is found by substitut-

ing (2.21) and (2.22) into (2.15) and solving to obtain

I3 = - (E, - E*)N Z, + 22,

Similarly, I4 in response to El and & is given by

It is important to note chat the current in the secondary side is propottional to the difference of the primary

input signals while the current in the center-tap is proportional to the sum of the two input signais. This

ability to combine or subtract signals is used extensively in many communication circuits. The usefulness

of the center-tapped transformer arises from its ability to isolate ports and, at the same time, to match

impedances between the ports. In this thesis, a transformer is used to combine a differential signal to pro-

duce a single-ended signal and this wilt be discussed in detail when considering the line driver design in

subsequent chapters.

2.3.2 Practical Transformer

Up to now, the discussion assumed the transformer to be ideal with no mutual coupling between the two

sections. The derivations above describe ideal circuit behavior, but do not fully describe the Limitations

encountered in a practicaf circuit. Figure 2-7 shows a simpiified transformer with pnmary and secondaq

windings of turns ratio lm. The primary applied voltage VI causes a cumnt Il to flow in the primary wind-

ing. The current gives nse to a core flux 4) which induces a voltage across the secondary winding V2 and a

current 12. Physical construction of the transformer creates some important non-idealities. These non-ideal-

ities a i se from the finite perrneability of the cote, resistances of the wires, leakage flux, distributed capac-

CHAPTER 2 - System Modeling

FLUX path Length=P Figure 2.7: A practical transfonner

itance, and inter-winding capacitance. An equivalent circuit can be developed to mode1 these effects N o r

983 (Cheung 981.

Finite permeability

If permeabiiity, p, is finite, it can be shown using Ampere's Law that

where P is the flux path length. Solving for 1,

The term 1, is called the core rnagnetization current and represents the current necessary to support the

magnetic field within the core itself- This current is in phase with the prirnary coil current and can be rep

resented in equivaient circuit by placing an inductance L, in parallel with an ideal transfonner as

shown Figure 2.8.

Figure

Vl 3 L, Ev2 1:n

Equivalent circuit including core magnetization current

An important property of L, is that it varies with the amount of DC current flowing through the prirnary

coil due to a phenornenon known as core saturation. The material pemeabiiity, p, relates the magnetic flux

CHAPTER 2 - Systsm Modeling

density B and the magnetizing force H through the formula B=@X p is only constant in the case of f k e

space. For other magnetic materials, the B-H rdationship foilows the general fonn s h o w in Figure 2.9. As

H increases, p s w to decrease from its maximum and eve~tuaLly approaches zero at the saturation point.

As the bias current increases, p decreases due to core saturation resulting in an increase in 1,. This can be

modeled by decreasing &.

Figure 2.9: The B-H relationship for magnetic materials

Winding resistances

The wire which is used to wind the transformer coils has a non-zero resistance which causes ohmic Iosses

in each of the windings. Inciuding this effect in the equivalent circuit simply requires senes resistance to be

added to each coil as shown in Figure 2-10. The magnitude of the winding resistance is afTected by the

diameter of the wire and the number of turns.

1:n- Figure 2.10: Equivdent circuit including winding resistance

Leakage flux

In the ideal case, al1 the flux generated in one coil is transferred completely to the other coil. In reality, not

al1 the flux completely Links both coils and there is some leakage. This results in an additional inductance

in series with the coils. This effect is included in the equivalent circuit as shown in Figure 2.1 1. Factors

affecting the magnitude of leakage inductance include winding technique and core geometry.

CHAPTER 2 - System Modeling

Figure 1:n-

: Equivalent circuit including leakage flux

Distributed and inter-winding capacitance

There exists several sources of parasitic capacitance in a real transformer winding. The distrïbuted winding

capcitance is the capacitance that appears across a winding due to coupling between the coil wire and îbe

transformer core. The size of this capacitance depends on the winding geometry and the dielectnc con-

stants of the core material and other packaging materials. This capacitance can be modeled by adding a

lumped capacitor (CDP CDS) across each ideal coil in the transformer equivalent circuit, The proximity of

primary and secondary windings also gives rise to a capacitance between the windings (C-). Usually this

capacitance is small in comparison with the transformer inductance, and its effect wiil only be seen at high

Figwe 2.12: Equivalent circuit including parasitic capacitances

Core losses

There are losses in the core due to hysteresis loss and eddy current Ioss. Loop currents generated in the

core results in power loss due to the finite resistance of the core. This loss can be modeled as a resistance

R, in parailel with the primary winding.

Complete equivalent circuit

Combining d l the non-ideal factors, a generai equivdent lumped-element circuit can be obtained for a cen-

ter-tapped transformer as shown in Figure 2.14. This simplified mode1 is usehl for hand analysis and for

Figure 2.13: muivalent circuit including core loss

SPICE simulations. The numeric values for the components in the equivaient circuit can be extracted h m

s-parameter measurements of a signai transformer. Some measurements for a sample transformer using a

network anaiyzer are shown in Figure 2.15 and Figure 2.16. in Egure 2.1 5. the measured input impedance

(S 11) is shown at different DC bias currents in the primary coi1 while the secondary is tenninated in 75S2

Figure 2.16 shows the transfer function (S21) as the DC cumnt is varïed. From these measurements, the

equivalen t circuit parameters were extracted for the 26m.A DC-bias case. The predicted input impedance

and the measured input impedance are shown in Figure 2.17. It is clear fiom the figure that reasonable

accuracy can be obtained from the equivaient circuit.

c,

Lwar Figure 2.14: Transformer equivalent lumped-element circuit

CHAPTER 2 - System Modeling

Input Impadinca va Biaa Curront . . . . . . . 400 7 . . . . . . m - 7 7 7 7 : . . . . . . . . . . . . . . . . . . . . . . r z I i i l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - - . - - . . . . . . . . . . . . . . . - * - . -

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - - . - - - . - . . . . . . . . . . - . - . - . . - . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . .... ZlO0- . . . . . - . . - . - ......- . . . - . . . . . . . . - . ...-........ . - . - - - * . . . . . . . . . . . . . . . . . - * - - - . - - . - - . . - - . - . . . . . . . . . . . . . . . . . - . - - * - . . . . . . . . . . . . . . . . . : -F-. -:. F- ;- - . . . . . . . . . . . - - - - - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . - . . - . . . . . . . . . . . . . . . . . . . . . . . . . . . - . - . - . . . . . . . . . . - . - - - 0 - 1 O-' 10- 10. 1 of 1 O=

. -- 1 O-' 1 o0 1 O' 1 of

Froquancy <MHz)

Figure 2.15: Measured input impedance (primary side)

10' 1 0' Frsquency (MHz)

Figure 2.16: Measured transfer fùnction (S21)

CHAPTER 2 - Systern Moôuling

Eauivalent ci-it vs Moaaurod

2.4 Echo Path Transfer Function

In a full-duplex system, transmission occurs simultaneously in both directions using a single coaxial cable.

Frequency division multiplexing, time division muhiplexing and directiond separation can all be utilized

for bi-directional transmission. Currently, the most common technique is directional separation where both

the near-end and the far-end signais overlap in time and frequency. In the receiver, the near-end component

(called the echo) that is superimposed on the received signal is removed using an adaptive circuit The

echo component has a frequency dependence and hence must be modeIed well for good cancellation. To do

this, consider the typical full-duplex scheme shown in Figure 2.18. A voltage source dong with the series

termination resistor represents the transmit-sidc. At the receive side, an adaptive filter is used to remove

the component of VT that appears dong with the far-end signai. The echo path transfer function is defined

as

100f

50

s 0 -

$! -50

-1 00

This can be derived using transmission line theory. The input impedance of a coaxial cable of length d (m)

terminateci on the other side by ZF is given by [Cheng 891

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . . . . . . . . . . . . . . . . . . . . . . . . . ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . a - . -- - .'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . - ....... -

-:, I : : I : : : : . - . - - . - - - . . . . . . . . . . . . . . . . . . - - - - - - - - . . . . . . . . . . . . . . . . - . - - - - A .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . : - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , - . . - - - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . . . -;. ........ -. - . . -..- - . . . . . . . . . . . . . " ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - - - . - - , . . ' L -;-:. 1 O-' 1 oO 10' t O== 1 O=

Fraqurncy (MHz>

Figure 2.17: Measured and predicted input impedance

d=3ûûm

Figure 2.18: A typicai fullduplex scheme

where Z, is the characteristic impedance of the cable and T, is the far-end reflection coefficient

For the case s hown in Figure 2.1 8, the far-end termination is

1 ZF = -+RF SC,

(2-30)

Using the properties of the Belden 8281 cable, the predicted and measured input irnpedance for a 300111

cable are shown in Figure 2.19. Notice the slight oscillations in both the magnitude and phase between

100kHz and 1MHz. These are not an artifact of modeljng but are real since they exist in the measured

results as well. These are due to the cable transition from low frequency behavior to transmission tine

behavior. These oscillations will manifest themselves in the echo path m s f e r function as well due to its

dependence on Zi,. The echo path transfer function is given by

w here

-- ~

Prsdicted and measurod Input impadrncr

. . . . . . . . - . . . . . . . 10 . . . . . . . i . . . . . . I . . . . . . . . . . . . . . . . . . . . r ? - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . . . . . . . . . . . . - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . .......................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- - - . - - .---- - - - . - - - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . - - - - - - - - O - - - . - . - . . -- .- . - - - - - - . . . . . . . . . . . . . . . . . . - . - - - -.-.. - - - - --.- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - - - - - - - - - - - - . - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : : : : : : : : 1 : : :::: L . . . : . .:. :.::::<:. . z . . > .:.: ::= . - - - - . . - - . . - - - - - - - . . - - . . . . . . . . . . . . -

10- 10- 1 O-' 1 O-' t 0" 10' 1 O= 1 O= Froquency <MUz>

Figure 2.19: Measured and predicted q,

This transfer hnction is plotted in Figure 2.20. To match this H(s) with reasonable accuracy, a second

order echo canceiiing filter, C(s), is required. The required transfer function is

The achievable echo loss with C(s) is shown in Figure 2-21. It is quite difficult to match H(s) within the

transition region with a low order filter. However, notice that the echo path transfer function converges to

0.5 beyond lMHz and can be easily matched accurately by C(s) with a simple variable attenuation (a sin-

gle tap). it is conceivable then to simplifv the echo canceling filter by transmitting and receiving signals

beyond M H z thereby eliminating the need to match H(s) below 1MHz This is straightforward to do with

a CAP modulation scheme since it is a passband scherne where the lower frequency edge cm be adjusted

to be beyond 1MHz. By using this technique, the echo cancellation filter can be considerably simplifieci.

The above analysis assumed capacitive coupiing of the cable for simplicity of the anaiysis, However, it

will be s h o w in the next chapter that transformer coupling is required to achieve the best dynamic range

and noise immunity for the ûansceiver circuit. Using the transformer quivalent circuit developed in this

chapter, the echo path transfer function can be computed and is shown in Figure 2.22. Once again, it is ben-

eficial to transmit above 1MHz. However, the parasitics of the transformer affects the response at high fre-

quencies. A higher order filter can be used to improve the echo loss in this range.

CHAPTER 2 - System M-ling

Echo Path Tranrfortunction

Figure 2.20: Echo path transfer function H(s) and second order fit C(s)

Figure 2.21: Echo loss with second order fit C(s)

CHAPTER 2 - System Modeling

Echo Path tmnrfor Functlon - T r a n s t o r m œ r couplhg

. . . . . . . . . . - - . . . . . . . . . . . . . . . . . i : i 2 . . . . . . . . . . . . . . . . . . . l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 . . - . T i . . : . i - . - 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............i........................... . . . .......!' ".....".......-.~.~. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- . . . . . . . . . . . . . . . . . - . . . . . . . . . . . . . . . . . - - . - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . . . . m . - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . , . . . . , .................. ..-:.- . - - - - - - - . - . . - - - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 '

10- 10- 1 O-' 1 o0 10. 1 O= 1 os Frsqusncy (MHz)

Figure 2.22: Echo path transfer function for transformer-coupting

2.5 Conclusion

In this chapter, the theory needed to mode1 the behavior of a coaxial cable and a center-tapped transformer

were presented. Using this theory, the echo path transfer function was derived and this showed that shifting

the signal spectrum beyond lMHz greatly simplifies the echo cancellation circuits. For the CAP modula-

tion scheme used in this thesis, this frequency shifi is suaightforward to achieve.

CHAPTER

Architecture

3.1 Introduction

The design trade-of's involved in the selection of the front-end architecture are explored in this chapter. In

particular, the choice of a voltage-mode or current-mode iine driver affects the implementation and perfor-

mance of the analog echo canceliation circuit. Upon considering these issues, the design choices for the

proposed Front-end are discussed.

3.2 Cable Coupling

Coaxial cable must be either capacitive-coupled or transformer-coupled to the transceiver circuits. AC-

coupling is required to avoid ground loops. When a long cable is connected between two distant transceiv-

ers, it is not guaranteed that the reference ground will be at the same potentiai for both traasceivers. If the

ground potential is significantly different, large transient currents can flow through the coaxial cable. If

sufficiently large current flows, it can darnage the cable as well as the sensitive transceiver circuits. With

the use of AC-coupling, each received signal is referenced to a local ground and ground loops are elimi-

nated. Present solutions use capacitive-coupiing [Genlinx 991. However, capacitive-coupling inherently

requires the cable to be driven single-endedly. This is acceptable for the multi-chip bipolar solution in

present use. However, it is not a good choice for a CMOS implementation. The main advantage of a

CMOS implementation is the single-chip solution due to higher integration. Due to this integration, trans-

CHAPTER 3 - Frontsnd Architëcture

ceiver chips have a smail analog fiont-end d o n g with a large digital back-end with the potential for large

logic sections to switch simultaneously. This cm lead to significant substrate and supply noise injection

which must be rejected. The best way to do this is to drive the cable differentially. In addition, the low sup-

ply voltage of modern CMOS processes rnakes it challenging to achieve large signal swing and low distor-

tion. Differential circuits are beneficiai since each haif-circuit needs to generate only haif the requirsd

signal swing. Finaiiy, the square-law nature of a MOSFET produces circuits that have high second-oder

distortion. By keeping the circuits differential, this distortion component can be reduced and hence further

improve the dynamic range, To drive the coax cable differentiaily, however, a transformer m m be used.

One disadvantage of transformer-coupling over capacitive-coupling is the increased parasitics of the tram-

former as discussed in the last chaptet Another disadvantage is the increased cost and area of a transformer

as compared to a capacitor. However for a single chip solution, good supply and common-mode rejection

as well as high dynamic range are key requirements. To achieve this, differential dnving is required. As a

result, transformer coupiing was chosen for the proposed front-end.

3.3 Line Driver Topology

The design of the tine driver circuit cannot be considered separately from the design of the analog echo

cancellation circuit since the choice of the line driver topology affects both the implementation and effec-

tiveness of analog echo cancellation. Two traditional architectures for line drivers are the voitage-mode

approac h and the current-mode approac h.

3.3.1 Voltage-mode Line Driver

Figure 3.1 shows a front-end with a voltage-mode line driver and analog echo cancellation. A line driver

with low output impedance is used to drive the temination resistors and the cable. The voltage at node 1 is

the transmit signal VT dong with any nonlinear components introduced by the line driver. Node 2 consists

of the superposition of the echo and the far-end signal. At the receive side, an adaptive filter, C(s). is used

to subtract the echo component, Because the fiiter samples the output of the line driver (node l), any non-

linear components introduced by the line driver are also subtracted before reaching the receiver. This

reduces the linearity requirements of the line driver. It is important for the echo path to have good linearity

since this determines the achievable echo removai at the receive side.

Figure 3.1: Voitage-mode topology

The line driver resembles a voltage source and hence the cable must be tenninated with series resistors

(RT) to achieve good renirn loss performance, For a full-duplex system. good retum loss is important since

a poorly tenninated line can produce reflections that will appear as echo and hence complicate the echo

removal process. However, due to the loss in the series termination resistors, donbie the desired voltage

signaf must be genecated by the line driver. With the Iow supply voltage used in modem CMOS processes,

a rail-to-rail output stage is requireâ to do this. A hi@-speed rail-to-rail output stage is shown in Figure 3.2

Pabanezhad 991. Here a current feedback amplifier with a class-AB output stage is used. Although the A

AA A T V

R2 Figure 3.2: High-speed voltage-mode line driver

approach is very power efficient due to the dass-AB stage, feedback must be employed to achieve the

required Iinearity and low output irnpedance. However, as the loop gain decreases at high îrequencies, the

output impedance cises from its low closed loop value to approach its open loop value of r k (the output

impedance of MOSFETs). The simulated output impedance of this circuit is shown in Figure 3.3- The dis-

advantage of this approach is not only the poor return loss performance but also the non-optimum conver-

gence of the adaptive filter, C(s). if the output impedance of the fine driver is low, then the voltage at node

1 will only be the transmit signal VT However, if the line driver presents significant output irnpedance,

CHAPTER 3 - Front-end Architecture

then part of the far-end signal at node 2 will also appear at node 1 due to resister division with RF This cor-

rupts the output of this filter (it now has a component proportional to the far-end signai) and leads to non-

optimum convergence of the tuning algorithm. Another issue with this circuit is its low input irnpedance

which is only 30022 (2RI)- This can lead to significant loading of the preceding block Because of these

problems, the voltage-mode approach is not popular for high-speed line drivers.

E Y e R

Ohms *

Figure 33: Simulated output impedance of voltage-mode Line driver

3.32 Current-mode Line Driver

A current-mode topology is shown in Figure 3.4. Due to the high output impedance of the line driver, a

parallel termination resistor is used. As a result, the Line driver needs to only generate the same voltage as

that across the cable. This makes the approach attractive for low supply voltage operation- However, the

echo cancellation filter must sample the input of the line driver since the output node contains both the

near-end and the far-end signal. This means that any nonlinear components generated by the Iine driver are

not subtracted and hence the linearity reduction obtained in the voltage-mode case is not present in the cur-

rent-mode case. in addition, the line driver must have enough headroom at the output to accommodate the

received far-end signai.

A typical implementation of a current-mode line driver is shown in Figure 3.5 wveritt 981. Two large com-

mon-source transistors are used to drive the cable in a class-A configuration, For tennination, a fixed exter-

na1 resistor is utilized. This approach is quite common in most commercial Fast Ethemet transceivers. The

CHAPTËR 3 - Front-end Architecture

Figure 3.4: Current-mode topology

advantage of this configuration is that since only a single transistor is used to drive the cable, the available

output headroom is maximized. However, it is inefficient since double the desired signal current needs to

be generated due to the loss in the parailel texmination resistor. The fixed nature of this extemal resistor

wiII also cause poor return Ioss performance if the characteristic impedance of the cable varies signifi-

cantly frorn its nominal value. Trimming is required to set the output currents accurately over process cor-

ners, but this still will not account for inaccurate transmit-levels due to load impedance variation from

+ Figure 3.5: Cunent-mode Line driver

3.4 Proposed Front-end

The proposed front-end is shown in Figure 3.6. A self-terminating line driver is used to drive the cable.

The developed line driver topology has no loss in the termination and provides a tunable voltage gain and

CHAPTER 3 - Front-end Aichitsct~m

output impedance. A tuning loop is used to autornatically adjust the voltage gain to unity at low frequen-

cies regardless of process, temperature, and cable impedance variations. Due to the circuit strucnire, the

output impedance is also adjusted to equai the cable impedaace by this tuning process. As a resuIt, this

architecture achieves robust performance regardless of variations. It should achieve superior retum loss

performance due to its adaptable output impedance and since there is no loss in the tennination, it can be

more efficient than other current-mode approaches.

Figure 3.6: Proposed fiont-end topology

Since the voltage gain is tuned to unity by the tuning loop, echo canceuation can be achieved by simply

subtracting the line driver input from its output. wth this technique, good echo cancellation can be

achieved above lMHz where the cable input impedance converges to its chanctenstic impedance. How-

ever, the echo loss will degrade at higher frequencies due to the magnitude roll-off and phase shift of the

line driver as weli as due to the parasitics of the transformer. Echo loss can be improved in this range by

including filter C(s) to match the echo transfer function better. Depending on the performance require-

ments, a fixed or adaptive second order Nter can be use&

The concept of analog echo cancellation has received some attention recentiy in the context of Gigabit

Ethernet. Two approaches, the magnetic hybrid and the resistive bridge, have been proposed to reduce the

amount of near-end echo and are shown in Figure 3.7 wealey 981 mazavi 991. The magnetic hybrid uses

flux cancellation to remove the echo but requires the complex transformer anangement shown. This

increases the parasitics and hence the frequency response and retum loss both suffer. It is also sensitive to

component mismatches. In addition, the hybrid has an insertion loss of 3.5dB to 5dB resuiting in an

increase in the signal that must be generated by the line driver. The resistive bridge relies on balancing

CHAPTER 3 - Frontand Architecture

impedances to perform the cancellation. However this approach is highly ineficient due to 6dB of signal

loss associateci with the resistors fonning the bridge. This loss is in addition to the ddB that is lost in imple-

menting the termination- Also, the solution is not integrated and requires severai off-chip components. As

a result, it is sensitive to component tolerances. Correspondingly, the amount of echo loss will depend on

the closeness of the matching. In contras& the proposed approach offers advantages because it does not

incur any losses in implementing echo cancellation and is accordingly more efficient. Since it is adaptive,

it is also insensitive to cable irnpedance variations.

ID AC

2k

- - - - - - - -

(a) Magnetic Hybrid (b) Resistive Bridge

Figure 3.7: Proposeci approaches for improving echo canceliation in Gigabit Ethemet

In this thesis, the proposed front-end will be designed with C(s)=l to sirnplify the design. With a straight

difference between the output and input, the achievable echo cancellation wiil be limited at hi& frequen-

cies. The key blocks in this circuit are the adaptable line driver and the tuning circuit which will be pre-

sented in the next chapter. The preliminary target specification for the design is s h o w in Table 3.1.

Because a new system architecture is k ing considered in this research, there are n o specific guidelines for

the design. Everything is open to considerations. As a result, the specifications were derived by looking at

similar systems such as Gigabit Ethemet and using some intuition on what is achievable.

CHAPTER 3 - Frontand Architecture

1 (with C(s)=I) 1 quencies I

Parameter

Bandwidih

Swing

Distortion

Retum Ioss

Echo Cancellation

Table 3.1: Target specifications

Value

> 1 2 5 m

1 AVpp, 75R

<-&dB IO*, 75Q

<- 15dB

> 2 W at Iow fre-

3.5 Conclusion

In this chapter, the architectural issues involved in the design of a frontend circuit were discussed. The

deficiencies of existing approaches were described and a front-end circuit that addresses some of these

deficiencies was proposed.

CHAPTER Circuit I ntegration

4.1 Introduction

The integration of the proposed CMOS front-end circuit is discussed in this chapter. The system block dia-

gram is shown in Figure 4.1. A tunabIe Line driver is used to drive the Beiden 828 1 coaxial cable differen-

tially through a surface mount signal transformer. The voltage gain of the iine driver is tuned to unity

regardless of process, temperature, and load impedance variations by a tuning circuit- Extemal termination

resistors are not used as the topology provides automatic termination of the line in addition to the lack of

signal Ioss in the termination. A bias circuit is used to generate the required reference voltages and currents

for the Iine driver and tuning circuit, The circuit topology selection and design choices are descnbed and

simulation results are presented.

Figure 4.1: Front-end circuit block diagram

CHAPTER 4 - Circuit întegration

4.2 Line Driver

+ Figure 4.2: Circuit for driving low resistive loads

A tunable seIf-tenninated Iine driver with increased efficiency was presented recently in Fauta 981 and

described brieily in Chapter 1- It proves to be a Likely candidate to meet the requirements for the proposed

front-end and must be revisited. It is shown conceptuaIly in Figure 4.2. An ideal transconductance ceU,

G , ,, is used in Figure 4.2a to drive a resistive load to obtain a voltage gain and output impedance given by

If a second transconductance cell, Gd, configure. as an active resistor is placed as shown in Figure 4.2b,

If Gml and Gd are tunable and are set to GmL=Gm2=l/RL then

CHAPTER 4 - Circuit Integration

With unity gain, the differential input voltage to the G*-cell is zero and it produces no output signal cur-

rent in realizing the tennination. As a result, tennination has been achieved without incumng any loss. In

addition, a tunable output impedance is obtained

In terms of the circuit realization, the transconductor can be implemented as shown in Figure 4 2 . The

input voltage is copied across RI using an opamp. The resulting current is amptified by the current amplifi-

cation factor, N, and produced at the output. The current amplification depends on the size ratio between

Ml and M2 ( h m now on referred to as M) and the values of the source degeneration resistors b1 and h2. N, and hence the transconductance of the circuit, is tuned by varying which is realized by a transistor in

triode. If N is chosen to be large, then the power consumption of the supporting circuitry can be minimized

and rnost of the power will be consumed at the output consisting of M 2 and the load. The addition of Gd

is equivalent to placing R2 as shown in Figure 4.2d. In the ideal case, the output impedance is given by

In the design process, RI and R2 are chosen to be

Ri = N a , , R ~ n o m R2 = ( N n o m + 1)R~norn v (4.5)

where N,,, and RLnom are the nominal value of N and RL respectively. A tuning circuit is then used to

force V,=Vi by changing N to account for the variation in RI and RL- This is achievable since the voitage

gain is given by

This tuning only accounts for variation in RI and RL- However, the matching between RI and R2 is very

good inside an integrated circuit and the output impedance will also be set correctly by this tuning process.

The basic approach is a single-ended circuit that is suitable for DC-coupied channels. However, in this

application, the coaxial cable is AC-coupled using a transformer to avoid ground loops and reject com-

mon-mode signais. The iine driver circuit must also be differential to obtain the best dynamic range and

noise immunity as discussed earlier. To investigate the use of the presented circuit in this environment,

consider the center-tapped transformer driven by a differeatial current source as shown in Figure 4.3. Let I I

Figure 43: Center-tapped transformer

L, and 1- be

3 3 1- = IDC - a l + allac - a31,, , (4-8)

where IDc is the DC current and i, is the ac signal current al, a*, and a3 are the coefficients of the s e n a

expansion (Le. fiat, second, and third order hamonic components). In Chapter 2, it was shown that the

center-tap current in a transformer, I, is the sum of I+ and 1- while the secondary side cumnt, IL, is pro-

portional to the difference between L, and 1.. As a result, the DC voltage at the positive input terminal is

given by

V + w = ~ R C M * D C ~

while the odd components of the AC voltage is given by

RL 3 V- = y(" 1 iac + a3f.c) (4.1 O)

Notice that the DC voltage is determined by the resistance at the center-tap while the AC voltage is deter-

rnined by the load resistance. Herein Lies the key to modiwng this circuit for use in a transformer-coupled

environment. For there to be no loss in the termination, the circuit requires both the DC and AC voltages

across R2 to be identical. This is assured by tuning N if the DC and AC load impedances are identical as in

a DC-coupled load. For a transformer, this must be simulated by using a variable center-tap resistor (b) as in Figure 4.4. Two single-ended circuits are used to drive the transformer differentially. A variable resis-

CHAPTER 4 - Circuit Integraîion

tor is used at the center-tap and adjusted to ensure that the DC and AC impedance seen by each

is identical. To perform this adjustment automatically. a tuning loop is necessary.

- - - - Figure 4.4: Modified circuit for use with transformer

The complete differential tine driver circuit is shown in Figure 4.5. The center-tap cesistance and tunhg

loop is formed by Mdc, C, and OTAc. The capacitor C, is used to improve the common-mode rejection

of the transformer by providing a low impedance path for the even order hamionic components that appear

at the center-tap. Transistors Ms 1, Ms2, and Ms3 dong with hl form the variable resistor hl used to hme

the current gain, N. The design trade-offs for each of these blocks will now be considered.

CHAPTER 4 - Circuit Intagration

42.1 Haif-circuit Design

Figure 4.6: Hdf-circuit for hand aoalysis

To understand the trade-offs involved in the design of uiis line driver circuit, some hand analysis is

required. Since the differential circuit consists of two identicai half-circuits, it is sufficient to analyze the

half-circuit shown in Figure 4.6. The parameters that affect the swing, bandwidth, and Linearity perfor-

mance of the half-circuit must be considececi- To keep the analysis tractable and useful, simple models for

the transistor must be used. The relationship between the output current and input voltage for a MOSFET

transistor is a noniinear function- In the most simple case, it is a quaciratic function [Johns 97a). When sec-

ond-order effects are included, these relationships become quite complex and require computer simulation.

The disadvantage of simulation is that it is sometimes quite difficult to get insight into the behavior of the

circuit- By using a square-law mode1 and simplifications to the circuits where possible, the trade-offs can

be anaiyzed by hand ailowing one to make educated choices for the design parameters. This is the objec-

tive of the following analysis- Although the accuracy of the analysis is no& high, general trends can be

observed and utilized to make good design choices.

Swing Requimments

The line driver needs to generate l.6Vpp across the cable. As a result, each half-circuit must generate

W.4V at the drain of M2. Since the line driver is k i n g used in a full-duplex environment, up to H-4V of

far-end signal cari be superimposeci at the output node. Althougb each half-circuit must generate S . 4 V

signal, it must be able to have headroom to handle W.8V signals at the drain of M2. To handle this, the

common-mode voltage at the output must be 0.8V. As a result, the maximum drain-tesource voltage, Vds2.

for M2 is

where 0.5V has been allocated as the maximum h p for the source degeneration resistor. This sets a limi-

tation on the maximum effective gate-source voltage, VenZ=VSG2+Vtp, that can be used while ensuring M2

is in active mode. The peak Vefa must be Iimited to less than 1.2V in this case for M2. This is also tme for

M l since the gate of Ml and M2 are tied together.

Frequency Response

One of the main factors a c t i n g the frequency response of this circuit is the need to maintain good phase

margin for the feedback loop consisting of Ml and the operaiional eransconductance ampliner (0TA)-

With reference to Figure 4.6, the dominant pole in this loop is given by

where r, is the output impedance of the OTA and (M+l)Cgsl is the total gate-to-source capacitance a t node

1. The non-dominant poles in the loop are due to the time constant at node 2 and due to the equivalent non-

dominant pole of the OTA itself. For typical cases, the equivalent non-dominant pole of the OTA domi-

nates. As a result, it is important to maximize the location of this pole to improve frequency response. The

OTA needs to drive a large load capacitance and hence requires a large transconductance. This increases

the sizes of the transistors within the OTA resulting in a lower non-dorninant pole. Reducing the load

capacitance helps to maximize this pole to some extenr However, to R ~ U C ~ Gel, (WL), must be reduced

and this can be done by increasing Vefii. The maximum VeEl is limited by the required headroom for the

signal swing. As a result, there is a trade-off between the achievable swing and bandwidth.

Distortion

The signal levels in this circuit are large and this results in distortion due to the nonlinear characteristics of

the devices. These non-linearities produce unwanted frequency components at the output which must be

kept to a minimum. The factors affecting the distortion components can be examined by simplifieci hand

analysis. It is shown in Appendix A that the second and third order harmonic distortion components for

this half-circuit can be approximated by

CHAPTER 4 - Circuit Integradon

where Il is the peak signal current in Ml and hl is the quiescent @C) current in Ml. A represents the

voltage gain of the opamp at low frequencies. VeffiQ is given by

(4-1 5)

and represents the quiescent effective gate-source voltage of Ml. A sqnare-law mode1 for the MOSFET M

saturation and low frequency of operation, well below the 3dB bandwidth of the circuit, has k e n assumed

in this analysis. Since II cc hl, equation (4.1 3) and (4.14) show that the second order distortion is much

larger than the third order distortion. Both components can be significantiy reduced by ensuring the gain of

the opamp is high. htuitively, this is what one wouid expect for this circuit- These equations also show that

for a given quiescent current IQi and peak signal current Il, the distortion can be Rduced by reducing

Vetrql However. to reduce Ve-fQl, the transistor size must be increased leading to lower fkqueIIfy

response due to the increased capacitance. Therefore, there is a trade-off between iineatity and bandwidth.

Note that although the second order distortion dominates for this half-circuit, it is the third order distortion

component that will determine the tinearity performance of the differential iine driver. Since two haif-cir-

cuits are used to form the differential circuif the second order components will be cancelled at the output

assuming good matching.

Another important distortion design consideration is the connection of the body node of Ml and M2- The

body of a PMOS transistor can be connected to its source to eliminate the body effect leading to improve-

ment in the distortion performance. However, in this case M2 is a very large transistor(1440fO.7 as wiil be

discussed next). As a result, signifiant nodinear well capacitance wiil appear at the source. This nonlinear

capacitance wiii lead to degradation in the linearity performance. Therefore, the overall benefit in this case

is not very clear. Simulations, however, showed that the third order distortion performance was worse by

1dB with the source connected to the body.

Design Choices

M, the size ratio between M2 and Ml, was chosen to be 40. increasing M decreases the power dissipation

in the branch consisting of Ml but decreases tunabiiity since a larger spread in is required for the same

CHAPTER 4 - Circuit Integrnon

tuning range. A value of 4û is a good compromise. Wi th this value of M and each balf-circuit seing a load

of 37SQ RI and R2 should nominally be 1500 and 1537.5R From the hand aaalysis, it is obvious chat the

size of M 1 must be chosen by considering the swing, bandwidth, and Iinearïty trade-offs. If Ml is made

large (hence Ves1 small). the swing and linearity performance improve while the bandwidth performance

suffers. Subsequentiy, a (WIL) I=36/0.7 was found to be a good compromise to meet the specifications for

this design. This choice limits the peak VeE1 to 1V ensuring aii devices remain in the active region over

process variations. With the chosen M, the size of M2 is (W/L)2=1440/0.7 leading to a total capacitance of

3pF for the opamp. To dnve ttiis load and keep the gain high for low distortion, a current-rnirror opamp

topology was chosen. A current-mirror opamp has superior slew rate and bandwidth performance over

folded-cascode opamps [Johns 97a]. The designed opamp is shown in Figure 4.7.

casc-p+

casc-p

out

Figure 4.7: Current-rnirror opamp

Simulation Results

The open-loop response of the feedback loop consisting of the opamp and Ml (with M î present) is shown

in Figure 4.8. A phase margin of 63O is achieved. The main limitation in the performance is the non-dom-

inant poles of the opamp reducing the achievable phase margin. A high phase margin is required to ensure

no overshoot in the step response. The closeci loop response of the entire half-circuit when driving a 37SR

load is shown in Figure 4.9. A summary of the simulated half-circuit performance is given in Table 4-1.

CHAPTER 4 - Circuit Integradon

Figure 4.8: Half-circuit open-loop response u n ~ r - C X R C U ~ T C L O ~ E O L O O P R E E P O N C C

L O - O P E N - N O U S O L rrP

Figure 4.9: Half-circuit closed loop response

Vdue

Swing 1 O.Sv,, @ 37.522 1 L I - -

-3dB Bandwidth 206MHz

Distortion I

1 Power I 74mw I --

Table 4.1: Haif-circuit simulated performance

CHAPTER 4 - Circuit Integmîion

42.2 Current Gain Tuning

In tbis circuit, the current gain factor, N, represents the current gain between M l and M2- This current gain

must be variable to compensate for variations in R1 and R2 as well as the characteristic impedance of the

cable. For the resistors in this process a +3-9% variation can be expected. The Belden 8281 cable has a

charactenstic impedance variaaon of 32% pelden 981. As a result, the tuning range for N must be greater

than 350%. This tuning can be performed by varyhg the resistor connected to the source of Ml with

respect to Rs2, the resistor connected to M2. When the voltage drop across QI and h2 are idenacal, the

current gain is equaI to the si= ratio M. When is increased ta increase its voltage drop, the current gain

increases from M. Solving for a closed form equation relating to N results in a set of transcendental

equations. As a result, computer simulations can be used to obtain the required variation in &1 to get

B O % tuning range. Simulation showed that a variation from IOOR to 900Q achieves this tuning range

while keeping the maximum voltage drop to less than 0.5V (the aliocated headroom for Rsr). The nominai

value of &l can be chosen to be 500R with k400Q variation, This means that RQ must be 12.5R (500/40)-

The variable resistor can be implemented with a triode transistor (Msl) in parallel with a fured resistor

(%l) as shown in Figure 4.5. The advantage of this choice is that it allows the overall resistance kI to

keep track with changes in k2 over process. This ceduces the drift in the mid point of the tuning range due

to process variation of Rs2- The maximum drain-to-source voltage drop for the triode transistor is O.Sv

Therefore, the minimum VefF was chosen to be 0.8V to ensure the transistor remains in triode over process

corners. This means that the available gate tuning voltage is fkom O to 1.8V (3.3-0-8-0.7). &1 as a function

of this tuning voltage is shown in Figure 4.10. The minimum achievable resistance is around 50052 Addi-

tional triode transistors are needed in parallel with Msl to extend the tuning range- This is the purpose of

Ms2 and Ms3. These transistors are switched in using the additionai switches that either tum the transistor

off by connecting its gate to Vdd or connect the control voltage to the gate. Once the end of a tuning range

is detected, the next triode transistor is switched in while the control voltage is reset and swept again- Note

that overlap between the tuning ranges must be ensured to avoid gaps in the tuning range. Gaps in the tun-

ing range c m cause problems with the tuning algorithm [Kamra 961.

It will be shown in Section 4.3 that a DAC is needed to produce the control voltage for current gain tuning.

The issues involved with the selection of the number of bits for the DAC w i U now be exploceü, At low fie-

quencies, the error in achieving unity gain for the line driver determines the amount of echo canceilation

CHAPTER 4 - Circuit Integration

Figure 4.10: Variation of Rs 1 with gate control voltage

that is possible. To ensure good echo cancellation regardless of variations, it was decided at design tirne to

keep the gain error to less than 40dB. To achieve this, it is straighrforward to show that N must be tuned to

within f0.8 of the tnie required value. From simulations, it was found that the rate of change of N with R,

variation is 0-03375lR As a result, the required variation in F& is a.8/0.0337k!2452. This means that

the minimum separation between consecutive resistance value changes is 48R The variation of the resis-

tance with the gate control voltage was shown in Figure 4.10. This is a highly nonlinear fùnction whose

maximum slope of 6 6 6 W occurs near the top end of the control voltage. Therefore, the maximum separa-

tion between control voltage levels is given by 48/666=72mv Since the control voltage range is 1.8V, 25

levels are required to achieve a gain e m r less than 40d.B. As a result, a 5-bit DAC was chosen. The current

gain as a hnction of the controf bits for the entire tuning range is shown in Figure 4.1 1. Notice that the

dope is much lower at the lower end of the control voltage. As a result, larger than the 72mV separation

can be used in this range while keeping the variation in N to less than kû.8. If the DAC topology dlows for

nonuniform output levels, then the DAC bits can potentially be reduced to 4 bits by increasing the level

separation at the lower end of the control voltage and hence reducing the total number of levels.

4.2.3 Output Common-mode Tuning Circuit

As mentioned at the beginning of this chapter, a circuit is required to set the output DC voltage (Le. corn-

mon-mode voltage) at the drain of M2. Conceptually, this can be done by connecting a variable resistor at

the center-tap and adjusting it with a tuning loop to equd the load impedance so that the AC and DC

CHAPTER 4 - Circuit tntegmdon

Currenf galn vu DAC blts

D A C blts

Figure 4.U: Current gain tuning range

impedance seen by the half-circuits are identical. In practice, a tuning loop to directly implemeat this is dif-

ficult since the exact value of the load resistance is unknown. But the fundamental need for this tuning Loop

is to ensure that there is no DC voltage chop across R2 so that there is no loss in implementing the tennina-

tion. This can aitematively be done by detecting the output common-mode and forcing it quai to the com-

mon-mode of the input signals to the line driver by adjusting the center-tap resistance. This is shown in

Figure 4.12. Here, the variable resistor is irnplemented by a transistor Mdc in triode. The opamp compares I I

Figwe 4.12: Comrnon-mode tuning loop

the output common-mode with the common-mode reference (Vm& to obtain an error signal that is inte-

grated by the tuning capacitor C, to produce the gate voltage for Mdc. This adjusts the resistance which

then forces the output common-mode to Vmr. For this technique to work, the inputs to the line driver

must also have their common-mode equal to V-J. This can be easily accomplished in a ûansceiver chip

since the preceding circuit (a pulse shaping filter or a DAC for example) will have a common-mode feed-

CHAPTER 4 - Circuit Integration

back circuit (CMFB) forcing its output common-mode. Vmfcan be passed as the reference to this CMFB

and thus ensuring identical common-mode voltages.

There are many circuits for detecting the common-mode of a differential signal. One simple method is to

realize that the transformer itseif performs the common-mode detection. The center-tap voltage WU q u a 1

the output common-mode and hence can be sampled d i t l y by the opamp- This simplifies the imptemen-

tation considerably. However, as has been shown, practical tramformers have up to few ohms of series

resistance. Since large DC currents are flowing through the transformer and package pins, the ohmic loss

in the package and transformer cm be as large as O.1SV. This creates an error between the Crue output com-

mon-mode and that seen at the center-tap. If this error c m be tolerated, then this is a simple technique to

force the output cornmon-mode. Altematively, traditionai common-mode detection circuits such as two

large summing resistors or PMOS buffers with summing resistors can be used [Johns 97a].

For this particular application, an aitemate method can be used. The line driver is designed for use with a

CAP modulation scheme where the differential input signals have negligibie fiquency content below

1MHz. This impiies that the output node can be directly sampled by the opamp and used to set the com-

mon-mode as in Figure 4.5- This c m be done as long as C, is large enough to ensure that the unity gain fre-

quency of the loop is well below 1 M E Only one of the output nodes needs to be sampled due to the

symmetry of the circuit. Sampiing the output node directiy eliminates the need for common-mode detec-

tion circuitry and aiso takes into account any ohmic loss in the transformer and package parasitics.

For this circuit, the size of the triode transistor Mdc must be chosen such that there is enough variation in

resistance to handle worst case currents. In the typical case, the 0.8V output common-mode causes 42.6mA

to flow in the transistor. The worst case current occurs when resistor RI is lower by 29% and the current

gain, N, is at its nominal value of 40- in this case a maximum current of up to 61mA must be tolerated. To

accommodate this, the size s h o w in Figure 4.5 wâs selected. The opamp shown uses a curent-mirror

topology. The tramconductance of the opamp was kept smal1 and a 470pF extemal tuning capacitor was

used to obtain rt unity gain frequency of 6- and a phase margin of 80° for the feedback loop. This Iow

unity gain frequency is sufïicient to ensure that the loop does not follow the differential sigaal. The high

phase margin aiso ensures good loop dynamics. The simulated step response is shown in Figure 4.13.

CHAPTER 4 - Circuit Integmtion

Figure 4.13: Common-mode loop step response

, . =..... .. ..................................................................... - - - O C - E T C P - T R O - . ... - c m v * o u -. ............. > . . .~~... . . . .~.~..~... .~... . . . . .~... . . . . . . .~.~... . . . .~... . . . . .~ * - - - = ='='--Tm'= 8 C O - O m =.. ............................................. ................- . . . . . . . . . . . . - - - - - - .................................... O . a u -. ..... ........-"... .... .".'..'.... . . . . . . . .- - - - - - - - -............ ................................ .....-.............- - - - - - -

4.3 Tuning Circuit

w 0 o o . o m 7--- O -

. L =- T - , L - L N - a m g -

- -

A tuning circuit is required for this line driver to function properfy. An opampforcing approach was used

in [Nauta 981. While the approach has the benefit of simplicity, it is unsuited for an AC-coupled channel. T t

is shown conceptually in Figure 4.14. An opamp dong with a large tuning capacitor are used to ensure

high gain at low frequencies while the loop becomes inactive at higher fiequencies. However, the Iow fre-

quency content between the output and input of the AC-coupled line driver is not identical due to the hi@-

pass nature of the transformer and comparison cannot be made over these fiequencies. In addition, for a

full-dupIex application, the output node is the superposition of the near-end and far-end signal. Therefore,

a direct comparison between the input and output of the line driver cannot be perfonned. A tuning dgo-

rithrn that overcornes these deficiencies is required. One suc h algorithm is the sgn-sgn least-mean-square

(SS-LMS) algorithm.

v i - - .............. 5...........74...............L................5............. z - / i - . . . . . . . . . . . . . .g. . . . / . . . . . . . i . . . . . . . . . . . . . . .+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - -

I / ..............>...............................!................$............. 2 - /i -

. . . /..! . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ................ ; ............. z - ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Among the many possible algorithms, the SS-LMS algorithm is widely used in adaptive circuits due to its

hardware implementation simplicity. It allows for a sarnpled-time reaiization of the adaptive algorithm

using rnostly digital circuitty. Minimizing analog circuiay is important in the tuning circuit due to DC off-

sets. Unwanted DC offsets are inherent in analog circuits and cause the algorithm to converge to a non-

optimum solution, It has been shown that SS-LMS algorithm in the presence of DC offsets bas much better

, -0 ; i. ' - - - - - O " -........ .................................... 2 ...-..... ..... - - - - -

7 C O - 5 .............. :.................................................................- - - - - - ,--..-. ..... ---: ..... .............................. -.... .......-........... ..- - - - - - r a O - =" ....... ................................................ ...................- - - - ..... 7 0 0 - O u r... ......... 5-.-i-.-L...I.......i...l .......,-.. i ..-..-.-. . . . .-i.--L-...-.-.-~

;È O U Y . O U S - O U 0 - o u O . T X M E C L I N 3 1 o . O U

CHAPTER 4 - Circuit fntegmtion

Figure 4.14: Opamp-forcing tuning loop

performance than the other LMS variants [Shoval95]. Using this a lgor i th , the required control voltage

(VdaC-& for the line driver is

where p is the adaptation constant and V&) represents the superposition

(4.1 6)

of the output signal due to Vi(t)

and the far-end signal VF(t). For this algorithm to converge, thece should be no correlation between the far-

end signal VF(t) and near-end signal Vi(t)- This is ensured in a full-duplex system where scrambling cir-

cuits are used to make the two data streams uncorrelateci.

In terrns of circuits, the algorithm can be realized as shown in Figure 4.15. The sign operation is perfonned

by clocked comparators. The multiplication of the sign of two numbers is equivalent to the XOR operation.

The integration is performed by the up/down counter combined with the DAC. This realization causes the

adaptation constant to be proportional to the clock frequency [Shoval 9 11. By reducing the clock fre-

quency, the adaptation constant can be reduced and hence reducing the excess mean-squared e m r after

convergence. Based on the tuning requirements, a 5-bit DAC was chosen. In the 7-bit counter, the two

most significant bits are used to select one of three tuning ranges. The bandpass filters in this scheme are

required to ensure comparison only takes place at mid-frequencies, above the lower corner frequency of

the line driver. The presence of the transformer induces a highpass response causing the output to be

unequal to the input at very low frequency- At high frequency, the roll-off of the line driver transfer func-

tion causes unequal input and output, As a result, comparison can only be made at mid-frequencies. The

bandpass fiIters do not have to be very accurate. Their main purpose is to Limit the signal power used for

tuning to mid frequencies. This simpfifies their design. The e m r signal, Vi(t)-V,(t), is generated by using

transconductors to perform the continuous-time difference, This operation is dso required to perform ana-

log echo cancellation as discussed previously. Hence, the two operations can be done using the same cir-

cuit.

Vdacout

C1k Figure 4.15: Sgn-sgn LMS tuning circuit

4.3.4 Transconductor ûesign

A transconductor is required to implement the continuous-tirne difference and the bandpas filters. A

transconductor produces an output current that is linearly related to the input voItage by its transconduc-

tance, G,.

Figure 4.16: A transconductor

There are a number of ways to design transconductors in CMOS [Johns 97al. A topology with low distor-

tion is shown in Figure 4.17 [Kwan 911 ~ii l ingham 931 wjns 961. This architecture employs servo feed-

back to force the differential input voltage across the degeneration triode transistor M 13 irrespective of the

exact gate voltages of the PMOS input transistor. The feedback is perfonned by M3 and M4 which act as a

gain stage and force the input devices to conduct a static current 12. AS a result, the input devices have con-

stant gate-to-source voltages and hence constant transconductances. Consequently, the differential input

voltage is seen directly acmss the triode resistance formed by Ml 3. The current generated in this resistance

CHAPTER 4 - Circuit Integmtion

flows through M3 and M4 and is mirrored to the output by M5 and M6. Multiple outputs can be obtained

by simply connecting additional transistors to the gate of M5 and M6. The transconductance is hence given

by m j n s 961

1, G,=-= 1 - 1 =- 2 = gm13 r (4-17)

vi r&13 +

13

g,*(l +A,)

where the small signal open loop gain, A,, is the product of the transconductance of M3 and the impedance

seen at the gate of M3.

The input devices are chosen to be p-channel devices to accommodate the required input common-mode

range and to eliminate the body effect by connecting the N-well to the source of the device. Eiiminating the

body effect not oniy provides greater input signal swing due to Iower threshold voltage but also provides

improved distortion performance. A common-mode feedback circuit is required to set the output common-

mode voltage. The control voltage from this circuit (V,,,,l) is connected to M9 and M l 0 t o adjust the

output common-mode. The compensation capacitors, Cc, in this figure are used to improve the phase

response of the transconductor at high frequencies. A small signal frequency analysis of this circuit shows

that the transfer function has some high frequency zeros which cause phase lead and magnitude boost at

high frequencies mllingham 931. The addition of this capacitor allows the dominant pole location to be

adjusted so as to d u c e the effect of these teros, The frequency response of the output current is s h o w in

CHAPTER 4 - Circuit Integrution

Figure 4.18 with and without the compensation capacitor. As shown, this capacitor improves the perfor-

mance at high kquencies.

. . . . . . . . . . . . . ............................ . ...... ............. a - - J O O O U ,.. "........ - . utput Current - W I T W C C . ~ C O - - - ,.. ................. " " . ................................................... - I C V N ~ P I

- - -4-2 % 1 T H O U T C C . P t - ...... ......... ......... ......... . . . . . . . . . . . . . . . . . . . . . . 1 C V N I t l

- o u -.. I j i ; 1 . . . . . . . . 1 . i ~ ----- - d - - i . ; ........ r.. ........ ........................... j .......... - ......... i...L; - - ; 1 1: - - I - ; ........ i ..................................... : ........ *.: ......... :-.; .... i r - ................ . o u ; ............................ C - ii - ... , . C... ..i.iaii.l.. c r ~ . r u L . ..a. i . . i s . I . . L , a i u J . . ,. ...riuil . . .L ,.a. ..,naL . . r . i . r r . r u L . .r .&.id

B o ----.-.----------------..---------.-. ................................... ......- - - - - - . . . . . . . . - . . . . . . . . S . . . . . . . . ........ ...... ... - W L T H E C - P C O ,, , ,. .!.. .;. . i . .;. t . . ..i. -, - - - - -/

o . - - . ....... ............. . . . .................. -2s -........ : " . > ' . ' . . . " .""i

E - .................... ; . . . . . . . . . i ......... j ......... & ...... - - - . .................................................................. - 7 5 =. - - ...... .................... . 0 0 ........ : .......... .. . . . . .....,... < *: ....... - .- - . . O - - - - ................................................................ = .. . . , O

. O E..- ..LUlk . .- -.. ... . ~ . . i . .... ,..UJi. .. , ..a.ui.. .L l~.......i - * _._& ; O 0 - 0 L - o r 1 0 - 0 5 l O O ~ O U 1 ~ 0 X I O - 0 % L O O - O X

1 0 . 0 H E R T Z C L O C 3 1 - 0 s

Figwe 4.18: Transconductor fkequency response with and without Cc

The common-mode feedback circuit used in this design is shown in Figure 4.19 fWhatly 861 [Duque 931.

The inputs to the CMFB circuit are the outputs from the transconductor and the output of the CMFB drives

the gates of transistor M9 and M l 0 in the transconductor. In this design a common-mode voltage of 1.2V is

used. The circuit operates as follows. Consider if V, is at some voltage higher than 1.2V than V, is below

it (Le. a cornmon-mode voltage higher than 1.2V), then there will be less current flowing through M6 and

more through M5. This means that VmmEI will increase causing the output PMOS current sources to

decrease their current in the transconductor. This will cause the common-mode voltage to decrease back to

M8 bias-p + 1 M 10 1 = v ~ a i

M7 M9 --P -4 1

I

- VcmRr

V , - ( ~ M * M2 N M3 M4$-V*

- ( 1

- casc-n+ M l 2

t - I

- 4 - Figure 4.19: ~ornrn&node feedback circuit for transcondktor

CHAPTER 4 - Circuit Integmtion

the reference level. To ensure the stability of the CMFB and confirm its operation. the circuit in Figure

4.20 was simulated.

+ Figure 420: ~on&&at ion for CMFB stability analysis

-.. ...................-..................... . = C W 1 - L O O - - T a 0 - - - - . . ............... = V C X F I L T - C M P ~ -...... - ; - * - ..................,.............. ..................- - - - - - - - ...... ...................... ..- - - - CM step

..................... .................... : ..................... 2 i.. .......- - - - - - > ..................... ..................... .................. . - - ! < . - . . . - * . - - - - - -

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .........- - - - - *. :. ..................... ..................... - * - - - - - - ................. -. .....- - - - - - - ..... 5- . . * . . . . . . . . . . . . . . . . . L ..... r . . . J i ..... 1 ..... r ............... . _ S . . .-..... 2

- ............,..... . . . . . . ... .. . . . . -. i - . . .. -.. ... . i . . ...-............. . . j . . .,... S 2 0 0 - O N * O 0 . O N C O 0 . O N

O - T I M E C L f N 3 P O O - O N

Figure 4.21: CM).% step response

t n 1 , L O O P . T R O X F L L T . C W P

d V X P - -----

A step was applied to the output nodes of the transconductor thereby increasing the output common-mode.

The results are shown in Figure 4.21. The soiid iines represent the voltage at nodes V, while the dashed

lines represent the voltage at nodes O+. As can be seen, the comrnon-mode output returns to the desired

level with no overshoot,

The transient step response of the entire eransconductor including the CMFB is shown in Figure 4.22 and

demonstrates the large signal stability of the circuit and its lack of hidden monances. Simulations with a

bdanced 3.2Vpp input signais also indicate the distortion components for a 1OMHz input are below -40dB.

4.3.5 Differencer and Bandpars Fiiter

A bandpass transfer function has the f o m

CHAPTER 4 - Circuit Integration

......... 7 s 0 - O" --.." ......... ......-.................-.......... ...- - - Outpet Current - C;H,s-r izP - r R o - - - 1 C V P - -

Figure 4.22: Tmsconductor transient response

where o, is the center frequency, Q is the quality factor and G is the gain at the center fkequency. For this

tuning application, a center fiequency of 3MHz and a quality factor of 0.45 with a gain of 0.5 was chosen.

This choice ensures that the BPF is weli above the lower corner frequency of the line driver with enough

bandwidth for tuning circuit to function properiy. A gain of 0.5 was chosen to keep the signals within the

filter to a reasonable swing and prevent clipping. The inputs to the fiiters have quite large voltage swing

and by keeping internai nodes to reasonabte swings better distortion performance can be obtained.

Figure 4.23: A G,-C bandpass filter

CHAPTER 4 - Circuit Integrstion

This bandpass transfer function can be implemented using a Gm-C topoIogy as shown in Figure 4.23

[Johns 97aI. The transfer function of this circuit is given by

Now, choosing Gma=G2--Gml and CASB=2pF, the required transconductance values to realize the

desired filter are

Using the transconductors discussed, the simulateci filter response is shown in Figure 4.24. Here, the

response due to sIow (SS) and fast 0 processes are shown to see the variation over process. B a N O P P s E C t L f E R r R E o U E N C 7 UESf=ONSE

Figure 4.24: Bandpass filter response

The entire differencer and bandpass filters are s h o w in detail in Figure 4.25. Some transconductor redun-

dancy has been eiiminated by using additional outputs h m the transconductor used for differencing as

inputs to the bandpass filter.

4.3.6 Comparator

The purpose of the comparator in this application is to obtain the sign of a signal. For this case, the speed

of the comparator is not critical but its accuracy is very important since offsets c m affect the convergence

CHAPTER 4 - Circuit Integration

Figure 4.25: Differencer and bandpass filters

property of the tuning algorithm. To minimize errors due to input-offset voltage and clock-feedthrough

errors, a two-stage fùlly differential comparator with capacitive coupling is used in Figure 4.26 [ J o b

97aI. During the reset phase (qI), the inputs to the first preamplifier are connected directly to the common-

mode reference voltage (1.2V). The second preamp is connected in a unity gain configuration using

switches MS5 and MS6. This stores any offset voltage of the first stage on the capcitors. When the com-

parator is taken out of reset phase, then the effect of the clock-feedthrough of MS5 and MS6 on the input

resolution is divided by the gain of the first stage which is about 19dB. The overall gain of the two preamps

is about 34dB. The outputs of the prûamps are passed to a latch with no static power dissipation [Song 951

to obtain the voltage levels needed to drive the digital circuitry that follow. The simulated overdrive recov-

ery is shown in Figure 4.27. Here, the input is changed from its maximum value of 0.4V to a minimum of

1mV in consecutive cornparison cycle. The comparator correctly detennines the sign of the input as

shown.

CHAPTER 4 - Circuit Integmtion

Figure 4.26: Comparator circuit

Figure 4.27: Simuiated overdrive recovery

4.3.7 Digital Circuits

The digital logic was synthesized using SYNOPSYS, The key circuit is a 7-bit up/down counter with satu-

ration logic protection. Saturation logic ensures that once the counter reaches its maximum (or minimum)

it stops incrementing and does not colt-over. This is important to ensure that there is no oscillations if for

some reason the optimum solution lies outside the tuning range. Minimum area constraint was used in the

synthesis since the speed of the logic circuits is not critical.

4.3.8 DAC

A 5-bit DAC is required for the tuning loop. The s p e e d of the DAC is not critical but it is important to keep

the power dissipation low. A themorneter-code DAC topology consuming l a s than 2SmA was selected

and is shown in Figure 4.28 [Colles 881. A binary-to-themorneter code converter was synthesized and

incorporated with the rest of the logic circuits to produce the logic signais bl to bX. A reference current is

generated using the feedbadc loop formed by Rmfi Mref and the opamp. This current is then mirrored to the

output by 3 1 c u m n t sources. The output swings fiom OV to 1.8V as required for the tuning triode resistor

in the line driver.

- A 5-bit DAC

4.3.9 Simulation

To test the functionaüty of the tuning loop, it was simulated dong with the line driver when driving a

1.6Vpp, 3MHz sine-wave. The clock frequency for the SS-LMS circuit was set to 2.5MHz. Figure 4.29

shows the tuning performance. Here, the output of the DAC (Vdac - ou3 and the error between the output

and input of the fine driver mm) are shown. At the beginning of the simulation, Vdac - out was purposely set

to 1.8V by resetting the counter and the SS-LMS circuit was enabled. This causes V,, to be large at thïs

point. If tuning is ideal, the error should be reduced by adjusting the DAC output to its nominal value of

232mV. As shown, the tuning circuit does converge to this value and rattles around it due to the excess

mean-squared error of the algorithm. This variation can be reduced by reducing the d o c k frequency

(which reduces the adaptation constant) at the expense of increased convergence time. A high d o c k fre-

quency was chosen here to reduce the simulation time. M e r convergence, the absolute error between the

input and output of the line driver is reduced to l e s than 1OmV.

CHAPTER 4 - Circuit Integdon

Figure 4.29: Tuning loop performance

4.4 Bias Circuit

A circuit is required to generate the reference voltages and currents for the chip. A popular bias circuit in

CMOS is the constant-g, bias circuit, in which transistor transconductances are matched to the conduc-

tance of an extemai resistor [Steininger 901. As a result, to a f h t order approximation, the transistor

transconductances are independent of power-supply voltage as well as pmcess and temperature variations.

The designed circuit is shown in Figure 4.30. At the cote of the circuit is the two back-to-back current mir-

rors and resistor Rb. It is straightforward to show that if (W/L)1=4(W/L)3 then

1 gm3 = -

R b (4-21

Lf second order effects such as body effect on Ml are considered, then the equation will be modified

slightly [Hartman 971. If better accuracy is needed then a complementary design with Rb connected to a

PMOS can be used. This configuration elirninates the body effect since the body of the PMOS can be con-

nected to it source. An altemate stable state exists for this circuit where al1 currents are zero- To avoid this

state a start-up circuit consisting of MIS-Ml8 is used.

One problem with this circuit is that it is prone to osciiiations if not designed carefully. The two current

mirrors fonn a positive feedback loop with gain less chan unity at low frequencies. At high frequencies, the

gain can become greater than unity due to the pad and pin capacitance at the source of MI shorting out Rb.

CHAPTER 4 - Circuit Integration

O bias-p M 15 - --P

r bias-n

- - f

Figure 430: Constant g, bias circuit To avoid this, part of the extemal resistance is placed on chip [Cheng 981. Also, IpF MOS capacitors am

connectai to each of the bias voltage nodes to help stabilize the circuit and decouple high frequency noise.

4.5 Layout and Packaging Considerations

Due to timing consaaints, a decision was made to fabricate only the f ne &ver and the DAC. This allows

the tuning scheme to be implemented externally using discrete circuits. The key cornponent in the Line

dri ver is the haif-circuit. Its layout is shown in Figure 4-31. Common techniques used for analog OPAMP RI &R2

circuit

Figure 4.31: Half-circuit layout

CNAPTER 4 - Circuit Integration

tayouts c m be observed [O'Leary 911 waloberti 941. The input differential pair for the opamp uses a com-

mon-centroid layout to minimize offsets. A Collection of unit-sized transistors and dummy devices at the

edges are used to improve transistor rnatching, Since the matching between resistors RI and R2 is impor-

tant, an interleaved layout is used. P+ difision layer is used for these resistors mainly because of its lower

process variation, +29%, as opposed to +40% for Polyl- In this process, Polyl layer bas only 10Q/square

while P* difision has 129Rlsquare. For the resistance values used, P+ diffusion has significantiy lower

parasitic capacitance and hence is used. (Often in double Poly processes, Poly2 layer has higher resistivity,

40Wsquare, than Poly 1 and can be used instead of P+ difisiou. However, the process information manu-

als provided did not characterize resistors in PoIy2 and no information regafding the resistivity, matching

etc. was given.) In this circuit, M2 is the main power dissipation element and as such will cause tempera-

ture gradients around it. As a result, matched elements near this device must be laid out symrnetric to it so

as to have the same gradient and hence maintain good matching. For this reason the opamp and resistors

are oriented symmetric witb M2, In addition, M 1 and M2 are laid out with the same unit sized transistor to

improve matching. Special attention is also paid to the layout of M2. It carries large currents and hence the

metal interconnect must be wide enough to accommodate this cumnt and avoid electromigration. For

added protection, Metai 2 and Metal 3 are tied together and used to form the interconnects for the source

and drain.

The Iayout of the entire chip is shown in Figure 4.32. It occupies an area of 1 5 0 0 ~ 1 5 ~ h i m ~ . A conservative

layout style is used mainly to ensure first-time f'unctionality for the prototype. In a commercial design, a

more aggressive layout to reduce area can be used. The two half-circuits are placed close together and

symmetric about the Line AA' to maintain good matching. The DAC is placed away from the half-circuit

and guard rings are used to prevent noise injection by the digital circuitry from reaching the analog cir-

cuitry. It must be noted that al1 the pads used in this design bave ESD protection. The line driver is the final

stage of a ûansceiver and must be able to drive al1 the parasitics seen in a manufacturing environment

Finally, for testing purposes, probe pads and additionai devices for characterization are included.

Early in the design, it was identified that up to 28pins would be required. As a result, the BNR 28/44

ceramic quad flat package was chosen. This package has a low profiIe and few layers of ceramîc which

results in smalIer parasitics which are more unifonn over the various signal paths. in addition, 16 of the 44

pins are strategically grounded to maximize signal isolation. The parasitic mode1 for one quadrant of the

CHAFTER 4 - Circuit Integrdon

bias circuit

ESD Protection y \ Test devices

Figure 432: Chip layout

CHAPTER 4 - Circuit Integnîion

package is shown in Figure 4.33. This mode1 combined with the bondwire mode1 aUow simulation up to

the pins of the package. Simulations with these models showed up to 0.15V drop in Vdd in the package. To

minimize this, multiple Vdd and Vss pins were used as shown in the layout- This die is rather small com-

pared to the cavity size of the package and hence long bond wires are required to make connections. As a

further precaution, aii the critical signal paihs were placed on one side of the chip and a request was made

to keep the bond wires on this side as short as possible.

Figure 4.33: Package parasitic mode1

4.6 Conclusion

This chapter described the integration of the proposed front-end circuit. An adaptable iine driver suitable

for transformer-coupling was designed. Also, the design of a LMS tuning circuit was presented.

CHAPTER Experimental Verif ication

5.1 Introduction

In this chapter, experimental results for the prototype are provided. These results include performance

measurements of the fine driver and a discrete implementation of the tuning algorithm. The photomicro-

graph is shown in Figure 5.1. The integrated circuit area is 1Smm x lSmm, while the active area of the

line driver, CM-loop, and DAC is 0.210mmz. The chip was tested in a custom printed circuit board with

controiied 50R and 75Q lines for the AC signal lines.

5.2 Line Driver Performance

The test setup is shown in Figure 5.2. To convert from single-ended signals (test equipment) to differential

signais (line driver topology) 50Q 180° power splitters were used. Bias-Ts were also used to setup the

common-mode for the input signals. At the output, a surface mount signal transformer was used to perform

the AC-coupiing. Since the output impedance of the system is 75Q a 75R-to-50R converter was used to

connect to test equipment, The schematic of this converter is shown. This is a wide-band matching circuit

and has a 7SdB voltage loss h m the 75 ohm side to the 50 ohm side.

Upon powering the chip, it was discovered that this particuIar process had its cesistors higher by 22%

resulting in the differential voltage gain k i n g lower than unity. The DAC was manually adjusted to ensure

the gain is unity at low frequencies (at 3MH.z). The power dissipation was found to be 155mW. The smaii-

Figure 5.1: Chip photomicrograph

Surface

. DAC V C I I ~ ~

- - - -

5-bits

Figure 5.2: Setup used to test line driver

signal bandwidth performance is shown in Figure 5.3. The chip achieves an upper bandwidth of 160MHz.

The distortion performance when driving l.6Vpp at lOMHz and 30MHz are shown in Figure 5-4, A total

hannonic distortion (THD) of better than -5OdB is achieved for a 1.6Vpp, 1OMHz signal. Some time wave-

fonns showing the chip driving sinusoid, pulse, and PN-sequence signais are show in Figure 5.5.5.6, and

5.7. For the PN-sequence signals, the low frerluency content was removed pnor to the line driver inputs.

Notice that there is a 7.5- loss between the actual output and that s h o w on the oscilloscope due to the

75Q-to-5052 converter. The retum loss performance of the line driver is s h o w in Figure 5.8. A rehim loss

better than -20dB is achieved at low frequencies due to the tunable nature of the termination. Finally, the

step response of the output common-mode loop is shown in Figure 5.9 and indicates the good dynamics of

this loop (no overshoots). The measured performance summary is given in Table 5-1

-12 1 1 I l O 50 100 1 5 0 200 260

Frequency <MHz>

0 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 1 . . . . . L . . . . . . . .:. . . . . . . i . . . . . . . . . . i . . . . . . . . .:. . . . . . . . . . . . . - . . . . . . . . - :. .:. . . . . . . . . . . . . . . . . : . . . . . . . . . . . . . . . . . - . . . . . . . : . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . - . . . . . . . . . . . . . . . . - . . .. , . . - - - - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . < . . . . - . -

-25 1

O 0.05 0.1 0-1 5 OS OS5 0.3 0 -35 0.4 0.46 0-6 Frequency <MHz>

Figure 5.3: Small-signal bandwidth performance

Dlrtonlon for 1 .sVpp output ' O f 1

. . . . . . . . . . . . . . . 1 - . - . . . . . . . . . . . . . . . . . 0 - . . - . . . . . . . . . . . . . . . . . . . . . -

..

. . . . . . . . . . . . . . . . : . . . . . . . . - . . . . . . . . . . . . . . . . . . . . . . . . . . -

. . . . . . . . . . . . . . . . - . . . . A . ......................

- - -

O IO 20 30 40 X ) eo 70 eo eo 100 Frequency <MHz>

. . . . . . . . . . . . . . -

-80

-70 O 50 100 1 S O

Frequency <MHz>

Figure 5.4: Distortion for L .6Vw across 75R

TEK Running: Normal 4

Ch1 Pk-Pk 660mV

Chi Freq 10 .OO4MHZ

Ch1 Pk-Pk s22rnv

Ch1 Freq 100.03MHz

Figure 55 : Sine-wave output at IOMHz and 1 OOMHz

TEK Running: Normal

!

Figure 5.6: Pulse response at lOMHz

Ch1 Pk-Pk 662mV

ch1 Freq 10.005MHZ

TEK Running: N o r ~ a l

TEK Runninq: Normal

Ch1 Pk-Pk 694tTlV

Ch1 Pk-Pk 682mV

Figure 5.7: PN-sequence response at 62-SMHz and lOOMHz

CHAPTER 5 - Experimental VefificaUon

Tek Run: 250kS/s Average 1

Cl H i g h 816mV

Cl LOW 636mV

Figure 5 9 : CM-loop step response

CHAPTER 5 - Expeiimentai VerHiCaron

Parameter 1 Experimental Value 1 ~orgct due

THD 1 .6Vpp, 10- 75R 1 -50.8dB

- 1

Output Voltage

-3dB Bandwidth

Supply Voltage (Vdd)

Idd (Static)

3.3V

4.6rnA

1 .6Vpp

7251rHz ~ 1 6 û M H z

1 .6Vpp. ~OMHZ, 7551

Return Loss

Table 5.1: Experimental resdts

1 -6Vpp

> 1 25MHz

Full Swing Power Dissipation

Active A r a

Technology

Noise (0.2- 100MH.z)

Dynarnic Range

Supply Rejection

5.3 Tuning Circuit Performance

-46-0dB

-27.6dB @ 1 OMHZ

155rnW

0.2 10mm2

0 . 3 5 ~ CMOS, 3AL, 1PS

62ctV-

8 1d.B

33dB @ lMHz

<- 15dB

Figure 5.10: Tuning circuit setup

v&c-ouc To PC

To determine the practicality of the proposeci tuning scheme, a discrete implernentation was constructed

w osaiio- 1 - - RC-filter - scope I - - RC-filter -

and chamcterized with the iine driver. A block diagram of the setup is shown in Figure 5.10. The bandpass

G P ~ B BIS

fiiters were implemented as passive RC-networks with high input impedance so as not to load the line

1.- q"y (5-bit output) HP Voltage

- - - J- source

driver- A khanne1 oscilloscope was used as a comparator to sample the signals and obtain their sign. A

cornputer, running LABVIEW, was used to implement the up/down counter and logic. It was also used to

control a DC source which generated the 5-bit control voltage to tune N. 2 I 1 8 1 v I 1 I 1

. . . . . . . . . . . . . . . . . . . . . . . 1-8 - . . . . . . . . . . . . - . . . . . . . -

. . . . . . . . . . . .

o.=-.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .........................-......-

O - f I * I I a 1 I * 5 10 i5 20 25 30 35 40 45 60 55 60

Ireration

Figure 5.U: Experimental trajectory

The counter was initialized to its nominal value of 1 10001 1 (the expected value for a typical process) and

ailowed to converge accordingly for a wideband input signal, The experimental trajectory is shown in Fig-

ure 5-11. For this particular process run, resistors RI and R2 were higher by 22%. To obtain unity gain, N

must be increased h m its nominal value to compensate for the increase in RI. This is accomplished by

increasing the control voltage. As shown, this is exactl y the action of the tuning circuit. After convergence,

the bandpass filtered input and output of the line driver are shown in Figure 5.12. The error ktween the

two has been decreased to less than IOmV.

To determine the echo loss as a function of frequency, the DAC output was frozen afkr convergence, and

the line driver input signal frequency was swept. The echo loss is shown in Figure 5.13. Echo loss is

defined as

where V, is a complex variable representing both magnitude and phase. As expected, the echo loss

approaches 40dB at low frequencies. The echo loss can be improved at higher fkquencies by using a

higher order echo canceling circuit than the simple differencing used as discussed previously.

CHAPTER 5 - E ~ m r i ~ r n l VMCaron

Bandpass f i l torec i widrrband signal

<n d -

-0.4 O 50 1 0 0 150 200 250 300 360 400 460 600

Figure 5.12: Bandpass filtered signals after convergence

1 O' Fmquoncy (MHz)

Figure 5.13: Measured echo loss

CHAPTER Summary and Future Research

-.

6.1 Summary and Conclusions

This research has focused on the issues involved in the design of a CMOS front-end, namely line driver

and hybrid, for full-duplex transmission. Traditional fùliduplex architectures rely on a digital echo cancel-

ing circuit to remove the near-end echo. However, these reaiizations require large number of bits for the

ADC and a highly iinear echo path. Chapter 1 showed that the resolution of the ADC and the tinearity

requirement of the tine driver can be reduced by improving the transhybrid loss. To achieve this improve-

ment, an adaptive analog echo canceting circuit was proposed to better match the echo path transfer func-

tion. The theory needed to model this transfer function was provided in Chapter 2. The developed model

showed that keeping the transmit spectrum above lMHz greatly simplifies the echo cancellation circuitry

for a 300m cable.

Chapter 3 considered the system level implementation issues of the malog echo canceling circuit. It was

shown that the choice of the line driver topology, voltage-mode or current-mode, affects the effixtiveness

of analog echo cancellation. Based on this analysis, a front-end circuit consisting of an adaptable line

driver and echo canceting filter was proposed. The architecture provides echo reduction but does not pro-

vide the linearity reduction advantage of analog echo cancellation. The circuit integration details were pro-

vided in Chapter 4. The major contribution is the development of an adaptable current-mode CMOS line

driver, Based on a single-ended approach suitabk for DC-coupied channels presented earlier, a differential

CHAPTER 6 - Summary and Future Remarch

topology for transformer-coupled c hannels was developed. In addition, a tuning circuit sui table for fuil-

duplex applications was developed to tune the voltage gain of the line driver to unity regardless of process,

temperature, and Ioad impedance variations.

A prototype of the line driver circuit was fabcicated and characterized- The tuning circuit was implemented

using discrete circuits as descnbed in Chapter 5. The line driver achieved a l6OMHz bandwidth and better

than -50dB total hannonic distortion for a 1*6Vpp signal acmss 75 ohms. in addition. it provided superior

return Ioss performance and better than 15dB of analog echo cancellation up to 20MHz. This echo cancel-

lation was achieved using a simple difference between the input and output of the iine driver.

6.2 Suggestions for Future Research

In this work, the tuning circuit was not integrami. This circuit should be integrated and characterized. In

particular, a modification can be made to sirnpii@ the circuit. ïnstead of ushg G,-C bandpass filters, a

buffer dong with passive RC filters can be used. Since the accuracy of these filters is not very important,

an RC realization is feasible. A passive implementation will also elirninate any DC offsets that may exist in

active realizations. This wili help ensure optimum convergence for the tuning circuit.

Echo canceIlation was implemented as a simple difference between the input and output of the tine driver.

This produced good performance at low frequencies. However, a higher order filter is required to match

the phase shift and magnitude roll-off of the line driver at high frequencies for better performance. Prelim-

inary work showed that a second order filter can provide good performance. This should be explored fur-

ther.

The proposed analog echo cancellation achieves only echo reduction but not linearity reduction, This is

because the echo canceling filter sarnples the input of the line driver which does not contain the nonlinear

components generated by the iine driver. However, it has k e n s h o w that at Iow frequencies the tinearity

of the entire line driver is dictated by the distortion in the drain current of Ml. If an additional matched

half-circuit consisting of Ml, R1, and OTA is used, the output of this can be sampled by the filter. The

drain of M l in this matched circuit will contain the nonIinear components generated in the line driver.

Hence, it may be possible to cancel these nonlinear tems partially.

Finally, the line driver uses a class-A output stage in this work. As a result, it is not very power efficient

since large DC currents must be used at the output- It may be feasible to implement this topology using

CHAPTER 6 - Summary and Future Research

transconductors with class-AB output stage. This can significantiy irnprove the power efficiency. However,

it is unlikely that high linearity can be obtained due to crossover distortion in class-AB stages. In applica-

tions where only moderate linearity is required (for NRZ type modulation schemes), this implementation

can produce a very efficient adaptive line driver. This should be exploreci further in future research.

A.l Introduction

This section describes the details of the distortion andysis for the Line driver haif-circuit. in particular, ana-

lyticai expressions for the second harmonic distortion (HD2) and third harmonic distortion (HD3) compo-

nents will be developed. To keep the analysis tractabte and thereby useful for hand calculations, the square-

law mode1 for the MOSFET in saturation is useci:

Id = P(vgs - vW)' * (kl)

where P=pC,,(W/L) and other quantifies are as defined conventionally [Johns 97al. Although the square-

law mode1 is inaccurate for short-channel MOSFETs, it is valuable for qualitative insight. Among the tran-

sistor behaviors that are ignored are body-effect, channel-length modulation, mobility degradation, and

velocity saturation effects. Analysis also assumes low frequencies where the reactive components in the

circuit are neglected. This makes the analysis valid at frequencies weil below the 3dB frequency of the cir-

cuit,

A.2 Distortion Analysis

The circuit used for this analysis is shown in Figure A. 1. Here, VQ represents the input quiescent voltage

and V represents the amplitude of the input signai. This generates in Ml a quiescent Iq and a signal current

jRi Figure A.l: ~alf-circuiifor distortion analysis

1. The opamp voltage gain is assumexi to be A- For this f d b a c k circuit, anticausa1 analysis and harmonic

predistortion cm be used to compute the distortion components wllingham 931. First consider VG

Also,

Equating (A.2) and (A.3)

Now by definition when V=û, I=O

Subtracting (AS) from (A.4),

Rearranging (A.6) we get

This equation relates the input, V. in terms of the output 1. The harmonic predistortion components, the dis-

tortion required on the input to obtain an ideal non-distorted output, is given by pll ingham 931

Appendix A - Distortion in Haîf-Circuit

It can also be shom that the harmonic distortion components can be derived fiom the harmonie predistor-

tion as [Wiiüngham 931

HD2 = -HP2 HD3 = 2 ~ ~ 2 ~ - HP3 E -HP3 for low HP2 (A-10)

Taking the denvatives of (A.7) and evaluating at 150 gives

where VeRQ is the quiescent effective gate voltage of Ml and is given by

Substituting these into (A.8) and (A.9) and using (A-IO), the harmonic distortion components are given by

For reasonable values of A, 21QRlA term dominates giving

Appendix A - Distortion in Half-Circuit

This equation gives the distortion for the current in MI but additionai distortion in the output is caused by

the current in M2. However, under nominal conditions, the gate-to-source voltage and drain-to-source volt-

age (both DC and AC) are identical for M l and M2. This implies that M2 will not introduce signifiant

additional distortion and the distortion of the entire circuit is teasonably given by (A.17) and (A.18). In

practice, there will be mismatches in geometry and in threshold voltages which will increase the distortion

slightly. Simulations verified that M2 indeed does not introduce any significant distortion and the circuit

distortion is detennined by Ml and the opamp at low frequencies.

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