a fpga design of aes core architecture for portable hard disk.doc

A FPGA Design of AES Core Architectu re for Portable Hard Disk AIM: The main aim of the project is to design and implement “A FPGA Design of AES Core Architecture for Portable Hard Disk! A"S#$AC#: This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of !bps "#S$%&'(& )e proposed the *+ bits data path of two different AES ar chitectures design, $asic -terative AES, which reuses the same hardware for all the ten iterations and , .ne Stage Sub ipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely *+ bits data path architecture that different from the previous public paper& The implementation result on the targeted 0!A, the basic iterative AES encryption can offer the throughput of %& !bps at %'' 12z and one stage sub pipelined AES can offer the throughput to increase the efficiency of 3&+ !bps at 4* 12z clock speed& V.Mallikarjun a (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIED COMPANY Branch!: "#$ra%a$ & Na'()r

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Page 1: A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

8/14/2019 A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

http://slidepdf.com/reader/full/a-fpga-design-of-aes-core-architecture-for-portable-hard-diskdoc 1/4

A FPGA Design of AES Core Architecture for

Portable Hard Disk

AIM:

The main aim of the project is to design and implement “A FPGA Design of

AES Core Architecture for Portable Hard Disk!

A"S#$AC#:

This paper describes a high effective AES core hardware architecture for

implementing it to encrypt/decrypt the data in portable hard disk drive system that

apply to effectively in the terms of speed, scale size and power consumption to

comply with minimum speed of !bps "#S$%&'(& )e proposed the *+ bits data

path of two different AES architectures design, $asic -terative AES, which reuses

the same hardware for all the ten iterations and , .ne Stage Sub ipelined AES,

with one stage of outer pipelining in the data blocks that both of them are purely

*+ bits data path architecture that different from the previous public paper& The

implementation result on the targeted 0!A, the basic iterative AES encryption

can offer the throughput of %& !bps at %'' 12z and one stage sub pipelined

AES can offer the throughput to increase the efficiency of 3&+ !bps at 4* 12z

clock speed&

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY Branch!: "#$ra%a$ &Na'()r

Page 2: A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

8/14/2019 A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

http://slidepdf.com/reader/full/a-fpga-design-of-aes-core-architecture-for-portable-hard-diskdoc 2/4

"%&C' DIAG$AM:

0ig5 A *+ bits data path of the basic iteration "6ata block 7l( and one stage sub pipelined AES

"6ata block 7* and 7+(

#&&%S:

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY Branch!: "#$ra%a$ &Na'()r

Page 3: A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

8/14/2019 A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

http://slidepdf.com/reader/full/a-fpga-design-of-aes-core-architecture-for-portable-hard-diskdoc 3/4

8ilin9 :&+-SE, 1odelsim 3&4c&

APP%ICA#I&( AD)A(#AGES:

A one stage pipelined with ;#T S<$o9 can give the throughput of more than

!bps as high but it consumed more resource than composite field S<$o9

about %'=&

-t should be more efficiency than previous paper in the operation speed "the

area wasn>t significant different( and throughput&

A synthesizable ?26; code is developed for the implementation of both

encryption and decryption process&

$EFE$E(CES:

• @& 6aemen and ?& ijmen, AES roposal5 ijndael "?ersion +(& B-ST AES

)ebsiteC http5//csrc&nist&gov/publications/ and

http5//csrc&nist&gov/DryptoToolkit/aes/rijndaellijndaelammended&pdf

• DAST, Advanced Encryption Standard Dore, available atC http5//www&cast<

inc&com/cores/aes/inde9&shtml

• - Dores, #ltra<Dompact, Advanced Encryption Standard Dore, available atC

http5//www&ipcores&com/AES*&pdf

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY Branch!: "#$ra%a$ &Na'()r

http://csrc.nist.gov/publications/

http://csrc.nist.gov/CryptoToolkit/aes/rijndaellRijndaelammended.pdf

http://www.cast-inc.com/cores/aes/index.shtml

http://www.ipcores.com/AES1.pdf

http://csrc.nist.gov/publications/

http://csrc.nist.gov/CryptoToolkit/aes/rijndaellRijndaelammended.pdf

http://www.cast-inc.com/cores/aes/index.shtml

http://www.ipcores.com/AES1.pdf

Page 4: A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

8/14/2019 A FPGA Design of AES Core Architecture for Portable Hard Disk.doc

http://slidepdf.com/reader/full/a-fpga-design-of-aes-core-architecture-for-portable-hard-diskdoc 4/4

• S& Dhantarawong, & Boo<intara, and S& Dhoomchuay, An Architecture for

S<$o9 Domputation in the AES, roc of -nformation and DomputerEngineering )orkshop& "-DE+''4(, pp&*F<*3+&

• Alireza 2odjat, and -ngrid ?erbauwhede, 1inimum area cost for a %' to F'

!bits/s AES processor, in roc& of the +''4 -EEE Domputer society Annual

Symposium on ?;S-, pp& %<&

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY Branch!: "#$ra%a$ &Na'()r

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