a floating point divider for complex numbers in the nios ii presented by john-marc desmarais...
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A Floating Point Divider for Complex Numbers in the NIOS II
Presented by John-Marc DesmaraisAuthors: Philipp Digeser, Marco Tubolino , Martin Klemm, Daniel Shapiro and Miodrag BolicEmail: {dshap092, mbolic}@site.uottawa.ca
Overview
Floating point division Instruction Set Extensions (ISE) NIOS II processor Instruction hardware Software interface Experiment Conclusion
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Floating Point Division
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Unlike real multiplication or real division, mathematicaloperations for complex numbers are usually provided by slowsoftware. Consider complex division:
Slow
Floating Point Division
• Fast complex dividers are necessary to drive an increasing number of applications such as signal processing systems for image and audio manipulation, GPS, and multi-antenna systems.
• Example: STSDAS offers math libraries for image analysis, including stsdas.analysis.fourier.carith, which is used to multiply or divide two complex images1.
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1http://stsdas.stsci.edu/cgibin/gethelp.cgi?carith.hlp
Instruction Set Extensions
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ISE(Instruction Set Extensions)
Instruction-Set Extensions, as the name implies, involves the addition of custom instructions to a processor’s instruction set.
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Many market processors allow for the addition of these internal custom instructions:1. Tensilica Xtensa (VLIW)2. Altera NIOS II3. Xilinx Microblaze4. MIPS CorExtend
In recent years there has been much research into the area of automatic identification of Instruction Set Extensions.
Instruction Set Extensions
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ISE(Instruction Set Extensions)
These automated efforts vary in their approach. Some look at the functional C level of the program where hotspot functions are identified. Others look lower at the basic construct of the program as data and control flow graphs.
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+
/ >>
x
yz
Modify ISAAdd
Custom Hardware
Modify Compiler, ASM & LD
Regenerate Custom Program
Instruction Set Extensions
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• An ISE candidate has limited IO access to the register file.
• The instruction width also poses an IO barrier.
Possible Remedies:1. Multiport Register File2. Register File Replication3. Shadow Registers4. Multicycle Reads (Altera’s NIOS II)5. Dedicated Data Links (Microblaze)
25 05610111516202131 26
opcode rs rt rd shamt funct
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Solution (Pozzi05):We use multicycle reads/writes from/to
the register bank in order to squeeze several operands into the two input-one-output register file.
NIOS II Processor
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Generic custom instruction datapath Our custom logic block
Instruction Hardware
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We can see in these figures that a sequence of three calls to the custom instruction results in a complex operation with four inputs and two outputs.
Cycl
es
Instruction Hardware
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Operation when n=0 above, n=1 at right.
Software Interface
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The designed hardware for complex division can be used easily in assembly (by inline) or C/C++ code as shown below:
Experiment
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We used a NIOS II processor and a PLL as the starting point for the design.
Experiment
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Conclusion
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• We designed a complex divider instruction set extension for the NIOS II
• This instruction was able to accelerate the execution of code that uses complex division
• In the future we would like to implement additional complex operations, and publish the core on OPENCORES.org
Applications can be accelerated with instruction set extensions, and complex division is one case where there is a tangible benefit.