IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-26, NO. 3, SEPTEMBER 1977

A Fault-Detection System for Digital Integrated CircuitsJUAN J. BARROETA, SALVADOR CAMPS, RICARDO E. SUAREZ, MEMBER, IEEE, MIGUEL A. CANAS,

MEMBER, IEEE, AND RUBEN A. AMAYA, STUDENT MEMBER, IEEE

Abstract-A system has been developed for the detection of mostcommonly occurring faults in digital IC's. Such faults consist ofeither permanent ("stuck-at") logic levels at input or output ter-minals, or short-circuits between adjacent terminals in a micro-circuit.

In the test system to be described both input and output terminalsare simultaneously analyzed under quasi-optimum test patterns.The input and output test patterns for each circuit of interest arestored in an average of 330 bits of READ-ONLY memory.The present system is capable of testing the logic operation of

CMOS and all families of TTL circuits.

I. INTRODUCTION

CURRENT WIDESPREAD use of digital inte-grated circuits (IC's) has made apparent the need for

a low-cost system for the detection of the most commonlyoccurring faults in logic microcircuits. Recently developedmethods for fault-detection in digital networks [1], [2] havebeen exploited in this work to generate quasi-optimum testpatterns for both combinational and sequential circuits.The test patterns are permanently stored in READ-ONLYmemories (ROM's). Simplicity of operation is thusachieved, since the user needs only address the memorylocation corresponding to the particular circuit under test.The results of the test are displayed in a GO/NO-GO fashion.The tester can be easily integrated into a computerized testsystem, since both the addressing signals and the testoutput signals are directly compatible with microprocessorsignal levels and speeds. The existing test patterns can bemodified through simple re-programming of the ROM's,without changing the structure of the system. Similarly,test patterns for new IC's can also be introduced withease.The IC tester to be described has been initially devel-

oped for fault-detection in CMOS and all TTL logic fam-ilies. The modular design used, however, permits testingof other logic circuits by appropriate changes in the in-terface circuitry to the test socket.

II. DESCRIPTION OF FAULTS

The types of faults of interest are illustrated on a TTLgate in Fig. 1. Fault I in this figure is an open-circuitedconnection to input terminal A. Under this condition theoutput of the gate is

Y|I = Xl - X21I = 1 iX2 = X2.X(1)

Manuscript received February 17, 1977.The authors are with the Center of Engineering and Computer Sci-

ences, Instituto Venezolano de Investigaciones Cientificas (I.V.I.C.),Caracas, Venezuela.

Xl- X yX2 x

FAULT m

GND

Fig. 1. Typical "stuck-at" faults in a TTL gate.

+ Vcc

Fig. 2. TTL gate "-ith short-circuited inputs.

Thus an open-circuited connection at A presents an ef-fective logic "1" level for variable X1 and, consequently,the output Y is independent of X1. In this case terminalA is said to be "stuck-at-i" (s-a-1). In Fig. 1, Fault II is anopen-circuit at the output terminal C of the gate. Now, theoutput terminal is s-a-1 and the output variable Y is nota function of the input variables,

YIII= * X2111 = 1. (2)Similarly, in the case of Fault III, a short-circuit is presentbetween the output terminal C and ground. Then, terminalC is "stuck-at-0" (s-a-0), and,

YIIII = Xl - X2 III = ° (3)

Another type of fault which is of interest is labelled FaultIV in Fig. 2. In this case a short-circuit is present betweenthe input terminals. Also shown in Fig. 2 are the driversused to introduce the input signals. It is observed that theshort-circuit creates an implicit AND function at the outputof the drivers,

Xi1IV= X211V = X1I X2.The gate acts now as a simple inverter with

(4)

Yliv = X1IV = X2I1V = X1 * X2. (5)

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BARROETA et al.: FAULT DETECTION SYSTEM

TABLE ITruth Tables for a NAND Gate Under Typical Fault Conditions

Test X1 X2 Y X1 x2 YII yKi

v Y11I

1 0 0 1 1 1 0 1

2 0 110 1 0 1

3 1 0 11 1 0 1

4 1 1 o 0 1 0 0

Hence, the logic function observed at the output terminalis still a NAND operation, despite the presence of Fault IV.Therefore, at the output of the gate it is not possible todetect the presence of this particular fault. This illustrationindicates that, n order to detect all possible logic faults ofthe types described, it is necessary to examine both inputand output terminals during the test.The class of faults discussed are assumed to be perma-

nent. It is possible, however, that the failure mechanismwhich gives rise to a particular fault may only be presentunder certain working conditions. Such intermittent faultsare difficult to detect and are not considered in thiswork.

TABLE IISummary of Faults Detected

by Each Test

Test Faults Detected

1 III

2 I, IIII I~~~~~~~~~~~~~~~~~

III

II

3

4

TABLE IIITruth Table for the Detection of Fault

IV Through an X-OR Gate

X 1 1x2 Z ZlIv

o 0 0 0

o 1 1 0

1 0 1 0

1 1 0 0

III. FAULT DETECTION

The subject of fault detection in digital systems has beentreated extensively in the literature [1], [2]. The conven-tional formalism employed in the discussion of the problemis summarized as follows. Considering a logic circuit withI inputs and m outputs, an input vector Xk and an outputvector Yk are defined as:

Xk = (Xkl, Xkl,x,l) (6)

and

Yk =(Yk1,*l , Ykm) (7)

where

Xkl and Ykj E (1, 0).A test Tk is defined as a pair:

Tk = (Xk, Yk). (8)

Now, if a single fault a occurs, such that the output vectorYk a $ Yk the test Tk is said to detect the presence of thefault.

In sequential circuits as a rule it is necessary to performseveral tests to detect all possible faults of interest. In thiscase the specific order of the tests is important, and the setof required tests is called a test sequence of length s:

Tks = (Xkl, Ykl;---; Xk5, Yks). (9)The test sequence Tks is said to detect the presence of afault if the sequence of output vectors is different at anypoint from the expected sequence Yk1, - - *, Yks

The process of fault detection is illustrated on the spe-cific faults discussed in the previous section. Table I liststhe truth tables resulting from the failure modes underconsideration. It is observed that test 1, consisting of inputvalues X1 = 0 and X2 = 0 is capable of detecting fault III,but cannot detect faults I, II, or IV. This is so because onlythe resulting output YI"' is different from the expectedoutput Y.A summary of the faults which a given test can detect

is given in Table II. The table indicates that a particularfault can be detected through several tests, and some testscan detect several faults. Thus, tests 2 and 4 are sufficientto detect faults L,1, and III. As noted in Section II, how-ever, it is not possible to detect fault IV with any test whichis restricted solely to an observation of the output termi-nals.

In order to detect fault IV it is necessary to analyze theinput terminals as well as the output terminal of the gate.Since a short-circuit forces the same logic level on the twoterminals involved, the prcess of fault detection is reducedin this case to a simple parity check. Thus the network fordetecting faults due to short-circuits between adjacentterminals can be implemented with a network of EX-CLUSIVE-OR (X-OR) gates. In the case of fault IV, asshown in Fig. 3, the output of an X-OR gate with the inputscorresponding to X1 and X2 detects the presence of theshort-circuit. Table III shows the output of the X-OR gateunder normal operation and in the presence of fault IV.

For an n-terminal integrated circuit package it is nec-essary to incorporate a total of n X-OR gates for the de-

247

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-26, NO. 3, SEPTEMBER 1977

XI* YX2 _%

Fig. 3. X-OR gate for the detection of short-circuits.

Vcc

©R

TABLE IVTest for the Detection of All Possible Faults in a NAND Gate

Test X X Y s-a-1 s-a-0 Shorts1 2

1l 0 0 1 A , B C B-C, C -D, E-A

2 0 1 1 A B, C A-B, C-D, E-A

3 1 0 1 B A , C A-B, B-C, C-D

4 1 1 0 C A, B B-C

Q

TABLE VFault-Detection Tests for an RS Flip-Flop

0

Fig. 4. RS bistable circuit.

tection of faults arising from short-circuits between adja-cent terminals. There are, therefore, n outputs from thisparity check network. It is important to note, however, thatsince some of the inputs to the X-OR gates are the outputsof the circuit under test, it suffices to monitor only the noutputs of the parity network to detect both short-cir-cuited connections and "stuck-at" faults.

IV. TEST PATTERN GENERATION

A. Combinational Circuits

Comparison of the truth tables for the normal and faultycircuits is a straightforward method of establishing therequired tests for the detection of each possible fault. Thismethod can be quite time consuming in the case of net-works with a large number of input terminals, since 21input vectors are derived for an 1-input circuit. Generationof all possible input combinations is not required, however,since some of the input vectors are redundant.Table IV lists all possible faults that can be present in

the case of the NAND gate of Fig. 1. For this illustrationterminals A and E are assumed to be adjacent. From thetable it is clear that tests 2, 3, and 4 are sufficient to detectall the faults of interest, and no additional information canbe derived from test 1.The process of deriving a test for a given fault consists

in determining an input combination which produces anincorrect output in the presence of the fault. The appro-priate input vectors can be established with well-knownmethods, such as: path sensitizing [3], Boolean differences[1], the D-algorithm [4], Poage's technique [5], orArmstrong's equivalent normal form [3]. The problem ofminimizing the complete set of required tests can be solvedsystematically since the Boolean expression resulting fromthe aforementioned generation methods can be minimized

with conventional techniques, such as the Quine-McCluskey method. The problem is further simplified inthe case of standard IC modules since the functions con-tained in such circuits are often sufficiently simple topermit near-optimum minimization of the test pattern byinspection.

B. Sequential Circuits

The task of generating test patterns in the case of se-quential networks is complicated by the fact that theoutputs at a given state time depend on both the inputsand the previous state of the circuit. Consequently, a testsequence, rather than a single input vector, is usually re-quired to detect a fault. As in the case of combinationalcircuits, a number of formal techniques have been pro-posed to solve the general problem [6], [7]. However, thecase of standard IC modules is considerably simpler thanthe general case for several reasons: In the first place, thesequential functions which are available are simple andwell-defined. Secondly, the circuits can be initialized in astraightforward manner, and the internal state is observ-able directly or indirectly at the circuit outputs. Finally,only faults ocurring at the circuit terminals are of inter-est.The problem then is sufficiently simple to permit the

generation of quasi-optimum test patterns in a heuristicmanner. The method is illustrated on an RS flip-flop asshown in Fig. 4. Table V lists three possible tests for thecircuit. At first sight test 3 appears to be redundant. Thetest is necessary, however, to remove the uncertainty of acoincidental initialization of the circuit to state I (Q = 1,Q = 0) in the presence of a fault. Thus, if terminal B in

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249BARROETA et al.: FAULT DETECTION SYSTEM

TABLE VITest Pattern for an SN7400N Quad NAND Gate

WORD ROM II ROM 12 ROM 01 ROM 02

b7_b6 b5__b4l_b3_b2_b_ bO_b7b6IbSlb4 blIb2Ibl I|bO b71b6!b51b4jb31b21bl |bO b7|b6|b5|b4|b3|b2|bl IbO

FLAG 0 0. 0 0 0 00 O0 01O O OO 00 0 0 010 0 0 0 000000 0 0

SUPPLY I 0 0 01 0 0011l 0 0 0, 0 0 001 01 IOIO 1 L ; O O I

[ TET1 | O O O O O O O O| ol| o Oo O1 i oo o1 1 lo1 o tol o oI- ~~~~~~~~~~ -I ~

TEST 2U0PL i Y0 0 1 0 000 0 1|01 00 1 0l 0 00 1 1 00 1 0 1 1 0 1 0 110

TEST 3 0 1 1Oi 1 0 O OO| O O 1 0 iO 1i ° | 1 1 ° 1 ° ° | ° ° 1 1 °

NEXT | O 0

FLAG ~00 0000 0011000 0000 ~ 1O'O~O~ o 0 0 oi 0 0 0 O~ 0 0 O~ 0 00II - l j

1 2 3 4 5 6

- 1 2 3 4 5

7 8

6 7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PINS - 1 2 3 4 5 6 7 - 8 9 10 11 12 13 14

9 10 11 12 13 14 15 16

- 8 9 10 11 12 13 14

"s-a-i" and the circuit happens to be set to state I whenVcc is turned on, test 3 will detect the presence of thefault.

V. SYSTEM DESCRIPTION

A block diagram of the test system1 is shown in Fig. 5.The input test vectors and the corresponding output vectorfor each IC are organized in 16-bit words and are stored inROM's I1, I2, and 01, 02, respectively. These memoriescontain all the information required for testing standard14 and 16 pin IC packages. The average number of bitsrequired for an IC is 330. The structure of a test patternfor an SN7400N quad NAND gate is shown in Table VI.The first word is a Flag Word which is used for purposesof identification. The next word in the pattern specifies thelocation of the power supply terminals to the circuit undertest. The following words represent the actual test words,which are presented to the circuit one at a time.

In a typical operation the ROM location for the partic-ular circuit under test is specified through the AddressSelector indicated in Fig. 5. The test operation is initiatedwith the Start signal. The contents of the ROM's arescanned by means of the Memory Address Counter, andthe occurrence of Flag Words is counted in the Flag WordCounter. Since the Flag Words consist of all 0's in theoutput test word, the Flag Detector is simply a 16-inputOR gate. Upon location of the appropriate Flag Word, thenext clock pulse loads the Power Supply Word on to theSupply Register and this information is kept there untilthe end of the test. The Supply Register drives a set of

1 An earlier version of this system has been reported in [8].

Fig. 5. Block diagram of fault detection system.

relays for the Vcc and ground connections to the circuitunder test.On the following clock pulse the first input test word is

read from Memories I1 and I2 and is applied to the circuitunder test through open collector TTL Drivers. The bitscorresponding to output terminals on the IC are 0's in theROM to cut-off the appropriate drivers. Simultaneouslywith the input test word, the output test word is read fromMemories 01 and 02. The output word obtained from thecircuit under test through the Parity Network is comparedwith the output test word in the Detection Network. Adifference between the two output words is interpreted asthe occurrence of a fault by the Output Circuit. Upon de-tection a fault the Output Circuit latches on and the"Faulty" display is activated. If no faults are encounteredthe condition is indicated through the "Good" display. Atthe end of the test, the detection of the next Flag Wordresets the system and cuts off the power supply connec-

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-26, NO. 3, SEPTEMBER 1977

tions to the circuit under test. The display circuits remainactive until a Reset signal is introduced.To enhance the reliability of the test system means of

self-checking have been incorporated to determine possibletester malfunctions. An incorrect test outcome may arisefrom one of the following situations:

1) selection of an incorrect test pattern due to a mal-function in the memory address circuitry;

2) incorrect power supply connection because of afailure in the Supply Register or the relays;

3) application of an incorrect input test level caused bya fault in:a) the input ROM's,b) the open-collector TTL drivers;

4) incorrect comparison between the output word fromthe circuit under test and the output test word,arising from a fault in:a) the output ROM's,b) the parity network,c) the detection network;

5) display of an incorrect result caused by a malfunctionin the output circuitry.

In cases 3a) and 4a) either a single bit, a word or a col-umn of the ROM's may defective. This problem may beconsidered equivalent to an error in programming and canbe detected by reading the memory contents and com-paring the results with the correct data. Although columnfailures can be detected with the subsequent tests to bedescribed, it is assumed that this type of malfunctions aredetectable in the process of initial Memory programmingand are not given further consideration. The remainingfailures are independent of the circuit under test and canbe detected by the use of appropriate test patterns. Thesystem test patterns are stored in the memories and thetest is performed without an IC in the test socket.

If a failure is present in the Memory Address Circuitry,as in case 1, a test pattern corresponding to a specific ICwill be presented at the test socket. Since the system testcondition requires that no IC be present at the test socket,an incorrect condition will be displayed.

Failures associated with the power supply connectionare of two types: First, a supply pin may effectively beopen-circuited because of a relay malfunction or thepresence of incorrect information in the Supply Register.The condition can be detected in the case of the groundterminals by means of the pull up resistor of the open-collector driver associated with the terminal, as shown inFig. 6(a). The Power Supply Word of the System TestPattern will normally activate the ground supply relays toconfirm the possibility of establishing the appropriatelevels at the ground pins. If an effective open-circuit con-dition exists the pull-up resistor will establish the oppositelevel at the faulty terminal, and the condition will be de-tected in the usual way.An open-circuited condition in the case of a VC pin

cannot be detected in the same way as with the groundterminals, since the pull-up resistor will tend to establisha Vcc level at the pin. One way to determine the presenceof the fault is to insert a small (-< 170-Q) resistor in series

GND PIN D I'll

{ 4 From Power Supply Register

_ + VccPULL-UP RESISTOR

TTL OPEN - COLLECTOR DRIVER

(a)

VCC PIN

i+ Vcc

TTL OPEN - COLLECTOR DRIVER

( b)

Fig. 6. Supply connections to the circuit under test. (a) Ground ter-minal. (b) Vcc terminal.

with the collector of the TTL driver, as shown in Fig. 6(b).Under normal conditions with the relay activated, the firstTest Word will turn on the drivers associated with the VccSupply pins. The 170-Q resistor will sustain a "1" levelwithin the maximum specified sink current for the TTLdriver (40 mA). However, if the supply pin is open-cir-cuited a voltage divider will be formed between the pull-upand 1704- resistors. The resulting voltage level at the de-fective Vcc pin will be below the TTL "0" threshold, andthe condition will be detected.A second type of failure associated with the supply pins

corresponds to the condition wherein a pin is stuck at itsnominal supply operating level. This situation will arisein the case of a shorted-out relay. This type of failures canbe detected through the introduction of a second SystemTest Pattern. In the new test pattern the Supply TestWord is such that all the relays remain inactive. During thefirst Test Word the drivers corresponding to the groundsup-ply terminals will be turned off, so that the pull up re-sistors will establish Vcc levels in the absence of the fault.Otherwise, a ground level will be improperly maintainedand the condition will be detected. For the Vcc pins thedrivers are turned on to pull-down the voltage to "0." If thefault is present a "1" will be maintained and the mal-function will be determined.

Cases 3b), 4b), and 4c) can be treated simultaneously asa single interconnected network, as indicated in Fig. 7. Therequired tests in this case are those which will detect"stuck-at" faults or short-circuits between adjacent ter-minals of the IC's which constitute the network. The testwords of the two System Test Patterns are used for thispurpose.The remaining case under consideration, case 5, has to

do with the possible failure modes which can cause thesystem display to be stuck at "Good" or "Faulty." If thedisplay is stuck at "Faulty" the condition will be detecteddirectly by the System Test Patterns. In order to detectwhether the display is stuck at "Good," it suffices to ad-dress the Test Pattern corresponding to a specific IC and

250

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. IM-26, NO. 3, SEPTEMBER 1977

FROM INPUT ROM

IKr

H0

HH"'U

>0z

FROM OUTPUT ROM

Fig. 7. Network consisting of the TTL drivers, parity and detectioncircuits.

perform the test with a blank test socket. If the displaycircuitry is operating properly a "Faulty" condition willbe displayed; if not, the presence of the malfunction willbe detected.

VI. CONCLUSIONS

The fault detection system described in this work iscapable of testing for the most commonly occurring

malfunctions in TTL and CMOS logic integrated circuits.Test patterns for the detection of both "stuck-at" andshort-circuited faults are stored in programmable READ-ONLY memories (PROM's). The resulting tester is com-pact, self-contained and flexible. System expansion as wellas modification of the existing test patterns can be ac-complished through simple re-programming of thePROM's. System reliability is assured through the incor-poration of appropriate test patterns for self-checking.

REFERENCES

[11 A. D. Friedman and P. R. Menon, Fault Detection in Digital Circuits.Englewood Cliffs, NJ: Prentice-Hall, 1971.

[21 H. Y. Chang, E. G. Manning, and G. Metze, Fault Diagnosis of DigitalSystems. New York: Wiley-Interscience, 1970.

[31 D. B. Armstrong, "On finding a nearly minimal set of fault detectiontests for combinational logic nets," IEEE Trans. Electron. Comput.,vol. EC-15, pp. 66-73, 1966.

[41 J. P. Roth, "Diagnosis of automata failures: A calculus and a method,"IBM J. Res. Dev., Vol. 10, pp. 278-291, 1966.

[5] J. F. Poage, "Derivation of optimum tests to detect fault in combi-national circuits," Mathematical Theory of Automata. Brooklyn,NY: Polytechnic Press, 1963, pp. 483-528.

[6] J. F. Poage and E. J. McCluskey, "Derivation of optimum test se-quences for sequential machines," in Proc. 5th Annu. Symp. onSwitching Theory and Logical Design, pp. 121 132, 1964.

[71 S. Seshu and D. N. Freeman, "The diagnosis of asynchronous se-quential switching systems," IRE Trans. Electron. Comput., vol.EC-11, pp. 459-465, 1962.

[81 J. Barroeta and S. Camps, "Probador de circuitos integrados digi-tales," Special Report for Engineer's degree, Universidad de Cara-bobo, Venezuela, 1976.

A Cycle-Slip Detector for Phase-Locked Demodulators

FLOYD M. GARDNER

Abstract-Thresholding in a phase-locked demodulator occursbecause of cycle slipping between the received signal and the VCOof the PLD. Measurement of rate of occurrence of slips should bean elegant and sensitive method of determining the threshold of aPLL. It is surely a much simpler procedure than attempting tomeasure output SNR, particularly if the modulation is anythingother than a simple sinewave. This paper describes the principlesof a slip detector that was built for laboratory measurements.

DETECTOR USAGEFIG. 1 shows the elements of a test setup that

would make use of a slip detector. A transmitting os-cillator is frequency-modulated with a suitable message,noise is added, and signal plus noise are bandlimited by a

Manuscript received July 12, 1976; revised April 21, 1977.The author is with the Gardner Research Company, 1755 University

Avenue, Palo Alto, CA 94301.

NOISE

SLIP PULES RECOVEREDTO COUNTER MODULATION

Fig. 1. Usage of slip detector.

band-pass filter (BPF). The filtered signal and noise areapplied to a PLL which extracts the modulation.A properly designed PLL reproduces a faithful replica

of the original modulation, provided the loop is capable of

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