a dynamically reconfigurable platform for channel coding in … · 2009-09-29 · 1 a dynamically...
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A A DynamicallyDynamically ReconfigurableReconfigurable PlatformPlatform forforChannelChannel CodingCoding in Wireless in Wireless CommunicationCommunication
Norbert Norbert WehnWehnTimo Vogt, Matthias AllesTimo Vogt, Matthias Alles
DFG SPP DFG SPP „„RekonfigurierbareRekonfigurierbare RechensystemeRechensysteme““September 2009, KarlsruheSeptember 2009, Karlsruhe
PALAMAWA
Wide Area networksMetropolitan Area networksLocal Area networksPersonal Area networks
any information, any where, any time, any one
GSM GPRS UMTS EGDE HSDPA 3GPP-LTE WLAN
WiMAX DVB DAB UWB
Consumer applicationTime-to-Market
NRE-costs Silicon-costsLow-Power
Communication Centric WorldCommunication Centric World
2
Mobile Phone TrendsMobile Phone Trends
1000100 10 1 0.1 Workload [GOPS] 54 3 2 1 Battery energy [Wh]
10010 1 0.1 0.01 Downlink bitrate [Mb/s]
LTELTE-A
HSPA LTE
HSPA GPRS UMTS
GSM Cellular standards 4Gpre-4G 3.5G 2.5-3G 2G Cellular generation
20152010 2005 2000 1995 Year
Computational complexityComputational complexity
Energy efficiencyEnergy efficiency
FlexibilityFlexibility
Continous demand for higher data rates and more servicesContinous demand for higher data rates and more services
Baseband Receiver Baseband Receiver StructureStructure
PARAMETER ESTIMATIONPARAMETER ESTIMATION
SIGNAL DETECTIONSIGNAL DETECTION
INNER RECEIVER
OUTER RECEIVER
CHANNEL
DECODER
CHANNEL
DECODERDe-Interleaver
De-Interleaver
RF&ADCRF&ADC
Forward Error Correction
3
Mobile Phone Trends Mobile Phone Trends –– Channel DecodingChannel Decoding
gprs
wcdmacdma2000
td-scdma
td-scdma
lteumts hsdpaumts
gsm
lte-a
dmb-t
dab dvb-t
dvb-sdvb-h dvb-c
uwb
802.16e
802.11b
802.11n
802.11a
bluetooth
dvd
blueray
wimax
1
10
100
1000
10000
0.01 0.1 1 10 100 1000
bit rate [Mbps]
oper
atio
ns/b
it 0.1 GOPS 10 GOPScellular decodersbroadcast decodersconnectivity decoders
100 x Mops/Mw
Source: Kees van Berkel, DATE2009
ChallengesChallenges
Up to 60 GOPS digital radio processing within a power budget Up to 60 GOPS digital radio processing within a power budget of about < 500 of about < 500 mWmWFlexibility: multiFlexibility: multi-- and evolving standardsand evolving standards
What is the right architectural approach ?What is the right architectural approach ?Cost of flexibilityCost of flexibility versus versus Value of flexibilityValue of flexibilityHeterogeneous or homogeneous architecturesHeterogeneous or homogeneous architectures
Large diversity in operations and data typesLarge diversity in operations and data types
Inner ReceiverInner ReceiverTechniquesTechniques in in standards arestandards are differentdifferentStandard signal processing but complex Standard signal processing but complex algorithms algorithms FFT, correlator, filter, matrix calculationFFT, correlator, filter, matrix calculation……..((channel estimation, channel estimation, equalizationequalization, demodulation, , demodulation, synchronization..)synchronization..)SoftwareSoftware flexibilityflexibility brings large benefitbrings large benefit
4
Architectural ApproachArchitectural Approach
Programmable (reconfigurable) SIMD/Vector EnginesProgrammable (reconfigurable) SIMD/Vector EnginesSANDBLASTERSANDBLASTER ((SandbridgeSandbridge), MUSIC (Infineon), EVP (NXP), SODA ), MUSIC (Infineon), EVP (NXP), SODA (Arm/(Arm/UnivUniv. Michigan), ADRES (IMEC), . Michigan), ADRES (IMEC), MONTIUMMONTIUM ((TwenteTwente))……..
Outer receiverOuter receiverFEC techniquesFEC techniques: : ConvolutionalConvolutional--, Turbo, Turbo--Codes, LDPCCodes, LDPC--CodesCodesComplex (iterative) decoding algorithmsComplex (iterative) decoding algorithms
NonNon--standard signal standard signal processing algorithmsprocessing algorithmsNonNon--standard arithmeticstandard arithmeticNonNon--standard standard wordword--widthwidth
Flexibility required Flexibility required but limited value of highbut limited value of high--level level softwaresoftwareSIMD/Vector engines of inner receiver not suitedSIMD/Vector engines of inner receiver not suited
3.5G Workload (100GOPS@1Watt)3.5G Workload (100GOPS@1Watt)
0%
20%
40%
60%
80%
100%
GOPS
baseband
media
graphics
GOPS
baseband
media
graphics
application
mW
outer receiver
inner receiver
frontend
Source: Kees van Berkel, DATE2009
5
Flexibility/Performance TradeFlexibility/Performance Trade--Off @ Outer Off @ Outer ReceiverReceiver
Weakly programmable decoding engine based on ASIPsWeakly programmable decoding engine based on ASIPs
DesignPipeline
Pipeline
AnalyzeAnalyze
FunctionalBlocks
FunctionalKernels
ASIP(WPIP)ASIP
Micro-ArchitectureAlgorithm A
Micro-ArchitectureAlgorithm A
Micro-ArchitectureAlgorithm B
Micro-ArchitectureAlgorithm B
Micro-ArchitectureAlgorithm C
Micro-ArchitectureAlgorithm C
FlexibilityRequirements
FlexibilityRequirements
GenericProcessorGeneric
ProcessorSoftware
AlgorithmSoftware
Algorithm
ProfilingProfiling
AdditionalInstructionsAdditionalInstructions
CombineCombine
ASIPASIP
Flexibility @ Outer ReceiverFlexibility @ Outer Receiver
XXMemoryXXAlgorithm (VA, MAP..)XCodestructure
XCodeclass (CC, TC..)Run-timeDesign-time
Exploit programmabilityExploit programmabilityInstruction level flexibilityInstruction level flexibilityDecoding algorithms e.g. LogDecoding algorithms e.g. Log--MAP, MAP, ViterbiViterbi
Exploit hardware Exploit hardware reconfigurability at runreconfigurability at run--timetimeEfficient data Efficient data management/shufflingmanagement/shufflingCode structureCode structureFast context switching and multi context Fast context switching and multi context instructionsinstructions
DesignDesign--time and runtime and run--time configurabilitytime configurability
6
Design Time Design Time ConfigurationConfiguration
74391
88966
106762
109320
Area[mm2]
SynthesisStandard cells
(65nm)
450
415
400
400
Frequency[MHz]
FPGA (Xilinx xc4vlx80-12)
1354207bTC
1175494bTC, dbTC (dbTC only 8 states)
1126683bTC, dbTC, CC (H VA)
1097012bTC, dbTC, CC (H/S VA)
Frequency[MHz]
SlicesFunctionality
VariousVarious ASIP ASIP instancesinstances withwith different different functionalityfunctionality withoutwithout memoriesmemories
ASIP ASIP configuredconfigured forfor Turbo Turbo DecodingDecoding
ChannelChannel codecode structurestructure specifiedspecified in DRCCCin DRCCCNSC/RSC, NSC/RSC, constraintconstraint lengthlength, BMU/Butterfly , BMU/Butterfly assignmentassignment……
7
ASIP ASIP configuredconfigured forfor ViterbiViterbi DecodingDecoding
Performance Performance ComparisonComparison
SizeFrequencyTechnology
53kGE400MHz65nmASIP (CC/TC)
97kGE335MHz90nmASIP (ENST)
~1000kGE400MHz180nmSODA (Inner+Outer)
34Mbps11.844Mbps17Mbps23.5ASIP (CC/TC)
8.6Mbps37.5---5Mbps65ASIP (ENST)
200
Cycles/bit@5iter
UMTS bTC
2Mbps
Throughput@5iter
24Mbps
Through-put
WLAN CC
??SODA(Inner+Outer)
Throughput@5iter
Cycles/bit@5iter
DVB-RCS dbTC
8
ASIP ASIP configuredconfigured forfor LDPC LDPC decodingdecoding
OnlyOnly reusereuse of of memoriesmemories and and pipelinepipeline stagesstagesAdditional Additional logiclogic necessarynecessaryTwoTwo reconfigurablereconfigurable barrelbarrel shiftersshifters
ASIP (CC/TC)ASIP (CC/TC) 0.11 mm0.11 mm²² logiclogic + + 0.31mm0.31mm²² memorymemory = 0.42mm= 0.42mm²²ASIP LDPCASIP LDPC 0.12 mm0.12 mm22 logiclogic + + 0.20mm0.20mm²² memorymemory = 0.32mm= 0.32mm²²ASIP (CC/TC/LDPC) ASIP (CC/TC/LDPC) 0.23 mm0.23 mm22 logiclogic + + 0.39mm0.39mm²² memorymemory = 0.62mm= 0.62mm²²
Synthesis Synthesis ResultsResults
1097012400109320ASIP (CC/TC)
10914495400232346ASIP CC/TC/LDPC
1328076425113099ASIP LDPC
Area[mm2]
Standard cells(65nm)
Frequency[MHz]
FPGA (Xilinx xc4vlx80-12)
Frequency[MHz]
SlicesFunctionality
LDPC IP LDPC IP CoreCore: : 0.10 mm0.10 mm22 logiclogic + + 0.20mm0.20mm²² memorymemory = 0.30mm= 0.30mm²²
LDPC LDPC ThroughputThroughput: : up to 257up to 257 Mbit/sMbit/s @ 400 MHz @10@ 400 MHz @10--20 20 iterationsiterations
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65nm low power technology
Die size \wo interface 0,69 mm2
385MHz
~100 mW
4* S
D m
em20
48 x
82
x SM
M12
8 x
96
2 * CV mem4096 x 12
IL m
em61
44 x
13
PRO
G m
em51
2 x
24
HD mem +LIFO
ASIP ASIP Layout (CC/TC)Layout (CC/TC)
DuoDuo--binary Turbobinary Turbo--Code Assembler ProgramCode Assembler Program
……setPCFsetPCF AP(1) SOM(1) INT(1) ESF(1) ; set control flagsAP(1) SOM(1) INT(1) ESF(1) ; set control flagsstst 3,CVA3,CVA ; ; \\ set memory addressset memory addressstst 0,RDA0,RDA ; / pointer; / pointerstst (SMMA=66),SMR(SMMA=66),SMR ; load PII state; load PII statestst SMR,(SMMA=0)SMR,(SMMA=0) ; copy it to state ; copy it to state metrmetr. . MemMem..RPT RPT --> R1> R1 ; single instr. loop:; single instr. loop:
fwdrecfwdrec (CVA)+=4 #CVs=1>>,(SMMA+=1)(CVA)+=4 #CVs=1>>,(SMMA+=1) ; forward recursion; forward recursionfwdrecfwdrec (CVA)+=4 #CVs=1>>,(SMMA+=3)(CVA)+=4 #CVs=1>>,(SMMA+=3) ; inherently store end state; inherently store end state
stst 0,WBA0,WBA ; ; \\ update memoryupdate memorystst WBA+63,WBAWBA+63,WBA ; / address pointers; / address pointersstst (SMMA=67),SMR(SMMA=67),SMR ; load PII_MAP2_BWD; load PII_MAP2_BWDRPT RPT --> R1> R1
bwdrecllrbwdrecllr (SMMA(SMMA--=1) =1) ; backward ; backward recursion & llrrecursion & llrstst SMR,(SMMA=67)SMR,(SMMA=67) ; update PII_MAP2_BWD; update PII_MAP2_BWDIDLEIDLE ; put ASIP into idle mode; put ASIP into idle mode
; (waiting for interrupt; (waiting for interruptnopnop
WiMAX/DVB-RCS duo-binary Turbo Code (Rate=1/2)
10
ViterbiViterbi Assembler ProgramAssembler Program
……; first, init Trellis; first, init Trellis
stst (SMMA=0),SMR(SMMA=0),SMR ;; load allload all--zerozero--statestateVA1 (CVA)+=2 #CVs=2,(VA1 (CVA)+=2 #CVs=2,(SMMA=2);SMMA=2); partial parallel recursion (I)partial parallel recursion (I)stst (SMMA=1),SMR(SMMA=1),SMR ;; load equalload equal--probprob. state. stateVA2 (SMMA=3)VA2 (SMMA=3) ;; partial parallel recursion (II)partial parallel recursion (II)…… ;; storestore partial path metricpartial path metricstst (SMMA=1),SMR(SMMA=1),SMRVA15 (SMMA=16)VA15 (SMMA=16)stst (SMMA=1),SMR(SMMA=1),SMRVA16 (SMMA=17)VA16 (SMMA=17) ;; last partial steplast partial step;}}};}}}
……; TRACEBACK for first Window; TRACEBACK for first Window
stst WBA,WBA_fwb_bufferWBA,WBA_fwb_buffer ;; Backup WBA after path metric calculation (WBA start)Backup WBA after path metric calculation (WBA start)
stst WSpACQm1,RDAWSpACQm1,RDA ; ; \\ update memory addressupdate memory addressstst 32768,WBA 32768,WBA ; > pointers and enable ; > pointers and enable HD_memHD_memstst WBA+WSpACQWBA+WSpACQ--1,WBA 1,WBA ;; / (MSB of WBA=1)/ (MSB of WBA=1)
stst 0,ISR0,ISR ;; initialize inverse shift register with zeroinitialize inverse shift register with zero
RPT RPT --> > WSpACQWSpACQ ; single instruction loop:; single instruction loop:VATBVATB ; ; oneone ViterbiViterbi tracebacktraceback stepstep
stst WBA,WBA_TB_end_bufferWBA,WBA_TB_end_buffer ; Backup WBA after ; Backup WBA after TracebackTraceback (WBA end)(WBA end)……
WCDMA Viterbi decoder (256 states, Rate=1/2)
LDPC Assembler ProgramLDPC Assembler Program
.text.textl.subml.subm 2424 ; ; reconfigurereconfigure networksnetworks and and
; ; setset submatrixsubmatrix sizesize to 24to 24l.diagl.diag 0, s=1, a=10, s=1, a=1 ; ; processprocess submatrixsubmatrixl.diagl.diag 0, s=6, a=20, s=6, a=2 ; s ; s determinesdetermines shiftshift offsetoffsetl.diagl.diag 0, s=11, a=80, s=11, a=8 ; a ; a determinesdetermines addressaddressl.diagl.diag 0, s=4, a=90, s=4, a=9l.diagl.diag 0, s=23, a=120, s=23, a=12l.diagl.diag 1, s=0, a=131, s=0, a=13 ; last ; last edgeedge of check of check nodenode
l.diagl.diag 0, s=18, a=10, s=18, a=1 ; ; newnew check check nodenode beginsbeginsl.diagl.diag 0, s=19, a=50, s=19, a=5l.diagl.diag 0, s=5, a=60, s=5, a=6l.diagl.diag 0, s=22, a=70, s=22, a=7l.diagl.diag 0, s=21, a=110, s=21, a=11l.diagl.diag 0, s=0, a=130, s=0, a=13l.diagl.diag 1, s=0, a=141, s=0, a=14 ; last ; last edgeedge of check of check nodenode......l.diagl.diag 0, s=23, a=120, s=23, a=12l.diagl.diag 1, s=0, a=231, s=0, a=23 ; last ; last edgeedge of check of check nodenode
l.pchkl.pchk it=10it=10 ; ; performperform parityparity checkchecknopnopPDPD ; power down; power down
WiMAX LDPC Code (576 bits, R=1/2)
11
ASIP flexibility increases the validation/verification complexitASIP flexibility increases the validation/verification complexityyFormal verificationFormal verification
Complex Complex decentralized memorydecentralized memory structure, outstructure, out--ofof--order register access, context order register access, context dependant instructionsdependant instructions……New methodology based on interval property New methodology based on interval property checking (W. Kunz)checking (W. Kunz)
Simulation necessarySimulation necessaryCommunications performance & Communications performance & programprogram developmentdevelopmentContext switches & Context switches & realreal time requirementstime requirements
ASIP C++ software ASIP C++ software simulation (LISATek@CoWare)simulation (LISATek@CoWare)TC PerformanceTC Performance: 75 bit decoding per second on standard PC: 75 bit decoding per second on standard PCUMTS TurboUMTS Turbo--decoding 6100 bit decoding 6100 bit blocklengthblocklength
100.00100.00 Monte Carlo simulation runs necessary / SNR pointMonte Carlo simulation runs necessary / SNR point~ 37 hours per SNR point on standard PC ~ 37 hours per SNR point on standard PC UMTS standard: 10 cases specified, per case 10 SNR points necessUMTS standard: 10 cases specified, per case 10 SNR points necessaryary
Validation/Simulation ProblemValidation/Simulation Problem
CompleteComplete FEC FEC communication chaincommunication chain on on XilinxXilinx ML507 ML507 platformplatform
Virtex5FPGA (XC5VFX70TVirtex5FPGA (XC5VFX70T--1) 1) withwith hardwiredhardwired PPC440, PPC440, manymany interfacesinterfaces
Rapid Rapid PrototypingPrototyping PlatformPlatform
DD
R2
Controller
150 MH
z
DD
R2
Controller
150 MH
z
SysAC
EC
ontrollerSysA
CE
Controller
DV
IC
ontroller75 M
Hz Pixel C
lk1024*768, 16 bits
DV
IC
ontroller75 M
Hz Pixel C
lk1024*768, 16 bits
PS/2C
ontroller75 M
Hz
PS/2C
ontroller75 M
Hz
UA
RT
115200 Baud
UA
RT
115200 Baud
IBM
PPC440
450 MH
z32+32K
B C
acheSuperscalar
IBM
PPC440
450 MH
z32+32K
B C
acheSuperscalar
FPU150 M
Hz
double precision
FPU150 M
Hz
double precision
TFT
RA
M(256 M
B)
Keyboard
Mouse
Com
pactFlash
(512 MB
)
RS
232
ASIP
75 MH
zA
SIP75 M
Hz
Noise
Generator
75 MH
z
Noise
Generator
75 MH
z
12
System chain
Decoding:FlexiTreP
ASIP
Encoding ModulationDatasource
AWGN Noise
De-modulation
BER/FERcalculation
GUI
CompactFlash
SelectProgram
LoadProgram
LoadConfiguration
SystemParameters
CommunicationsPerformance
Software (PPC)
Hardware
Software / Hardware Software / Hardware PartitioningPartitioning
PlatformPlatform
13
UMTS TurboUMTS Turbo--Code: 882 bits @ 5 iterations / kbpsCode: 882 bits @ 5 iterations / kbps
ResultsResults
507,2 – 578,2 97,7 – 363,30,459/109/10
364,7 – 415,071,6 – 363,30,452/32/3
272,5 – 309,853,7 – 195,30,451/21/2
217,3 – 252,037,0 – 151,20,451/31/3
FPGA FPGA withwithHard AWGNHard AWGN
FPGA FPGA withwithSoft AWGNSoft AWGN
C++C++Model Model
(ASIP (ASIP onlyonly))Code RateCode Rate
C++ ModelC++ Model : 1 Million frames ~ 22 days / SNR: 1 Million frames ~ 22 days / SNR
Soft AWGNSoft AWGN : 1: 1 MillionMillion framesframes ~~ 3 hours / 3 hours / SNRSNR
Hard AWGNHard AWGN : 1 Million frames ~ 30 minutes/SNR : 1 Million frames ~ 30 minutes/SNR
Code rate and modulation scheme impacts computational complexityCode rate and modulation scheme impacts computational complexity of AWGNof AWGN
MultiMulti--Processor Processor ArchitectureArchitecture 4 x ASIP4 x ASIP
ASIP ASIP ASIP ASIP
CVram#a
ILram
Pin
gPo
ng CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
CV:
115
2x12
SP
IL: 1
536x
13 S
PEX
: 102
4x8
SP
Fully
buf
fere
d X
BAR
4 D
eep
Fifo
at e
ach
Bran
ch (1
6 FI
FOs)
Dou
ble
Buf
fer C
TL
Con
figur
atio
n fo
r HS
DPA
ASIP ASIP ASIP ASIP
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
EXram
CV:
115
2x12
SP
IL: 1
536x
13 S
PEX
: 102
4x8
SP
Fully
buf
fere
d X
BAR
4 D
eep
Fifo
at e
ach
Bran
ch (1
6 FI
FOs)
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
CVram#a
ILram
CVram#b
ILGen
3GPP2
ILGen
3GPP2
ILGen
3GPP2
ILGen
3GPP2
Onl
y S
ingl
e B
uffe
red
IO fo
r DV
B-S
H
Con
figur
atio
n fo
r DV
B-S
H
Flexible interconnect network
Dynamic re-organization of memories for different services
14
Architecture SpaceArchitecture Space
DSP
#bits/cyle@8-state MAP0.1 41
Flexibility
Architectural Efficiency
8
Multi-ASIPSingleASIP
HardwiredIP Core
150 Mbit/s LTE Decoder- 65 nm technology- 300 MHz- 2.1 mm2 after P&R
PublicationsPublications
[1] M. Alles, T. [1] M. Alles, T. LehnigLehnig--EmdenEmden, C. Brehm, and N. , C. Brehm, and N. WehnWehn. A Rapid . A Rapid PrototypingPrototypingEnvironmentEnvironment forfor ASIP Validation in Wireless Systems. In ASIP Validation in Wireless Systems. In ProceedingsProceedings of of EDAEDAWorkshop 2009Workshop 2009, , pagespages 4343––48. Dresden, Germany, May 2009.48. Dresden, Germany, May 2009.
[2] T. Vogt and N. [2] T. Vogt and N. WehnWehn. A . A ReconfigurableReconfigurable ASIP ASIP forfor Convolutional and TurboConvolutional and TurboDecodingDecoding in a SDR in a SDR EnvironmentEnvironment. . IEEE IEEE TransactionsTransactions on on VeryVery Large Large ScaleScaleIntegration SystemsIntegration Systems, , pagespages 13091309––1320, 1320, OctoberOctober 2008.2008.
[3] M. Alles, T. Vogt, and N. [3] M. Alles, T. Vogt, and N. WehnWehn. . FlexiChaPFlexiChaP: A : A ReconfigurableReconfigurable ASIP ASIP forfor Convolutional,Convolutional,Turbo, and LDPC Code Turbo, and LDPC Code DecodingDecoding. In . In ProcProc. . 5th International Symposium5th International Symposiumon Turbo Codes and on Turbo Codes and RelatedRelated TopicsTopics, , pagespages 8484––89. Lausanne, 89. Lausanne, SwitzerlandSwitzerland,,September 2008.September 2008.
[4] T. Vogt and N. [4] T. Vogt and N. WehnWehn. A . A ReconfigurableReconfigurable ApplicationApplication SpecificSpecific InstructionInstruction SetSetProcessorProcessor forfor Convolutional and Turbo Convolutional and Turbo DecodingDecoding in a SDR in a SDR EnvironmentEnvironment. In. InProcProc. . Design, Automation and Test in Europe (DATE Design, Automation and Test in Europe (DATE ’’08), 08), pagespages 3838––43. Munich,43. Munich,Germany, Germany, MarchMarch 2008.2008.
[5] N. [5] N. WehnWehn. An . An OuterOuter Modem ASIP Modem ASIP forfor Software Software DefinedDefined Radio. In Radio. In 8th International 8th International Forum on Forum on EmbeddedEmbedded MPSoCMPSoC (MPSoC(MPSoC’’0808), Aachen, ), Aachen, JuneJune, 2008, 2008
15
PublicationsPublications
[6] N. [6] N. WehnWehn. . Flexibility/ReconfigurabiltyFlexibility/Reconfigurabilty TradeTrade--OffsOffs in SDR in SDR ArchitecturesArchitectures. In . In FridayFridayWorkshopnWorkshopn ReconfigurableReconfigurable ComputingComputing, , Design, Automation and Test in Europe Design, Automation and Test in Europe (DATE (DATE ’’08), 08), Munich, Germany, Munich, Germany, MarchMarch 2008.2008.
[7] T. Vogt and N. [7] T. Vogt and N. WehnWehn. A . A ReconfigurableReconfigurable ApplicationApplication SpecificSpecific InstructionInstruction SetSetProcessorProcessor forfor ViterbiViterbi and Logand Log--MAP MAP DecodingDecoding. In . In ProcProc. . IEEE Workshop onIEEE Workshop onSignal Signal ProcessingProcessing (SIPS(SIPS’’06),06), pagespages 142142––147. 147. BanffBanff, Canada, , Canada, OctoberOctober 2006.2006.
[8] T. Vogt, C. [8] T. Vogt, C. NeebNeeb, and N. , and N. WehnWehn. A . A ReconfigurableReconfigurable OuterOuter Modem Modem PlatformPlatform forforFuture Future CommunciationsCommunciations Systems. In Systems. In DagstuhlDagstuhl Seminar, Seminar, DynamicallyDynamically ReconfigurableReconfigurableArchitecturesArchitectures, , DagstuhlDagstuhl Seminar Seminar ProceedingsProceedings 0614106141. . DagstuhlDagstuhl, Germany,, Germany,April 2006.April 2006.
[9] T. Vogt, C. [9] T. Vogt, C. NeebNeeb, and N. , and N. WehnWehn. A . A ReconfigurableReconfigurable MultiMulti--ProcessorProcessor PlatformPlatform forforConvolutional and Turbo Convolutional and Turbo DecodingDecoding. In . In ReconfigurableReconfigurable CommunicationCommunication--centriccentricSoCsSoCs ((ReCoSoCReCoSoC).). Montpellier, France, 2006.Montpellier, France, 2006.
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