a ctivity ii: alice its r eadout e lectronics s erial l ink c haracterization hira ilyas madiha...
TRANSCRIPT
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ACTIVITY II: ALICE ITS READOUT ELECTRONICS
SERIAL LINK CHARACTERIZATION
Hira IlyasMadiha TajwarJibran AhmedRaise Ikram (carrier board)Dr. Attiq Ur Rehman
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TASKS
Firmware development for serial link characterization
GUIBETCrosstalk analysis Jitter analysis
Carrier board schematic and layout (possibly)
Hardware testing
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BERBER
100 MHZ
200 MHz
300 MHz
400MHz
Frequency
JITTER
CHIP SELECT
1 2 3
4 5 6
7 8 9
Phase
Fixed Random
Pattern
Periodic
Duty Cycle
100
200
300
450
5Cross Talk on channel 1 2 3 4 5 6 7 8 9
Channel Select 1 2 3 4 5 6 7 8 9
Cross talk Pattern Random Worst case
BER JITTER
GUI LAYOUT
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4
DESIGN OF A TEST SET-UP FOR THE CHARACTERIZATION OF HIGH SPEED ITS SERIAL DATA LINKSObjectives
Bit error rate evaluation at various data rates
Cross talk analysis between data links
Power analysis
Key Tasks Specification design of
the test plan (can be seen in GUI)
Schematic design of test board
Firmware development
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TEST SETUP
5
USB INTERFACE
Lab view / Python
Virtex 6 Board
USB interfac
e
RESULT UNIT
Logical and physical
characterization block
AddressCommand decoder
Clock Manage
r
Configuration block
LINKConfigurati
on
Hig
h s
pe
ed
CO
N
HS
co
nn
ec
tP
ow
er
Chip A
Chip B
Chip C
Chip X
Carrier card
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BIT ERROR RATE TESTING
Generating clocks with different phases and frequencies to characterize BER.
Using system clock as input, generating different shifts with as minimum resolution as possible.
Integrating shifted clocks to check BER
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Clocking Wizard(Phase shifted clocks, and reference clock)
Clocking Wizard( x2 , x4… frequency generator)
Counter Generator (Every time Push Button is pressed, phase is shifted, phase resolution is variant)
PB_x2PB_x4
rst
clk
Ref_clk
Clocking Wizard(Phase shifted clocks
Clocking Wizard(Phase shifted clocks
PB_shift
DATA FLOW DIAGRAM of Clock generation
IBERT Core
7
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• ref_clk is taken as input clk 50MHz upto 1GHz, rest are shifted clocks with different phase and frequency compared to ref_clk.
• shifted clocks with 50 MHz, have been generated. Each being shifted to 10O (simulation, 9O to 11Oactual) as compared to last shift.
• These clocks will now taken as input to check BER, at different phases and frequencies
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FUTURE WORK
Different data patterns are sent at different phases and frequencies.
Jitter Analysis to be done on different clocks.
To figure out at what phase and frequency, optimum results are achieved.
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IBERT The ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core
for Virtex-6 GTX transceivers is a customizable core that can be used to evaluate and monitor the health of Virtex-6 GTX Transceivers.
The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers.
Software Requirements
Core GeneratorChip-scope Pro Analyzer
Hardware RequirementsVirtex-6, ML605SMA Cables
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DESIGN OF BIT ERROR RATE TESTER
DataPattern
PISO
CDRSIPOCompar-ator
ResultMemory
TX
RX
USB interface
usingCore
Generator
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HARDWARE SETUP AND INITIAL SETTINGS & RESULTS
Hardware setup
IBERT Initial Settings
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Bathtub Curve to Calculate Bit Error Rate (SMA) Line rate: 2.5 Gbps. Frequency 200Mhz
Length 1foot Length 2feet
Line rate 1 Foot 2 Feet
2.5 Gbps 55.9% 52.8%
3.125 Gbps 44.5% 38.6%
5 Gbps 36.2.3% 32.3%
UI OF BATHTUB CURVE @ SYSTEM FREQ 200MHZ
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BOARD LEVEL COMPATIBILITY BETWEEN
MASTER CARD & CARRIER CARD
VERTEX 6
Control
HS_DATA
Clock
SP6_1
SP6_9
Control
HS_DATA
Clock
?
D_Storage
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CONTROL
Master Card Master Clock 40 MHz
Chip Select IC Controlling Carrier Card
JTAG Header External Programming
Carrier Card Chip Select IC
Enabling Spartan-6 on Carrier Card
JTAG Header Programming Through
Master Card
HIGH SPEED DATA
Connector Configuration Routing Technique
Differential Pair Length Tuning Signal Integrity Analysis
Connector Configuration Routing Technique
Differential Pair Length Tuning Signal Integrity Analysis
CARRIER BOARD SCHEMATIC AND LAYOUT
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PURPOSED DESIGN TO TEST SERIAL LINK CHRACTERIZATION
Hig
h s
pe
ed
C
ON
ITS_BUS
Carrier card
• Master Card Design under Validation.• Board Design Layout under Process.
Link to be Characterized
FPGAXilinx Board
Hig
h s
pe
ed
C
ON
Spartan 6 as test chip
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HARDWARE SETUP
Agilent Infiniium 9000 Series Oscilloscopes
Keysight 81150A Pulse Function Arbitrary Noise Generators
ML605-Vitex 6