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A CMOS Band-Pass Low Noise Amplifier

With Excellent Gain Flatness for mm-

Wave 5G communications

H. Choi, S. Choi, C. Kim

Chungnam National University

Daejeon, Republic of Korea

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Contents

I. Introduction

II. Ka-band CMOS Low Noise Amplifier- Gain Flatness

- Band-pass Filter (Maximally Flat Gain)

- Circuit Design

# Pole-Zero Tuning

# Electromagnetic Structure

# Layout

- Measurement Results

- Electrostatic Discharge Issue

III. Conclusion

IV. References

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I. Introduction

5G wireless communications issue

5G issue

- High data rate with low error rate

- High reliability

- Antenna arrays & Beamforming

https://medium.com/@timscottseo/what-is-5g-431d4033bb9d

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Chip issue

- Low power consumption

- Low manufacture cost

- Fully integrated circuit

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I. Introduction

Advantage of scaled CMOS Process (under 65nm)- Compact & Low cost

- Mechanically robust

- Good compatibility with the digital system

Disadvantage of CMOS Process- Substrate loss : loss due to eddy current, most serve in highly doped

P+ substrate (Q limit by eddy current loss)

Off-chip components Fully integrated circuits

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I. Introduction [Challenges]

LNA– Design issue

Noise

performance

Power

dissipation

Bandwidth &

Gain ripple

Gain &

LinearityChip size

NF < 2.5 dB

Frequency band

= 24-31 GHz

Low gain ripple

Gain > 18 dB

Dc-power < 10 mW

CompactnessIIP3 > -15 dBm

Trade Off

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II. Ka-band LNA design [Gain flatness]

If the gain of the LNA is not flat, the amplification of the input signal is

not constant, which results an rough baseband signal.

It is difficult to compensate an rough base band signal, which deteriorate

the communication performance.

Well-regulated signal of the LNA can be compensated easily at base band

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II. Ka-band LNA design [band-pass Filter]

Butterworth Filter & Schematic

n = 3, H(S) = 𝟏

(𝒔+𝟏)(𝒔𝟐+𝒔+𝟏)

𝑩𝒏 𝒔 =ෑ

𝒌=𝟏

𝒏𝟐

𝒔𝟐 − 𝟐𝒔 cos2𝑘 + 𝑛 − 1

2𝑛𝜋 + 𝟏 , 𝒏 = 𝒆𝒗𝒆𝒏

𝑩𝒏 𝒔 =ෑ

𝒌=𝟏

𝒏−𝟏𝟐

𝒔𝟐 − 𝟐𝒔 cos2𝑘 + 𝑛 − 1

2𝑛𝜋 + 𝟏 , 𝒏 = 𝒐𝒅𝒅

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II. Ka-band LNA design [Pole-Zero Tuning]

Small signal model & Pole-zero distribution

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II. Ka-band LNA design [EM structure]

𝑪𝟏

𝑪𝟐

𝑹𝒅𝒆−𝑸

𝑺𝒐𝒖𝒓𝒄𝒆

𝑫𝒓𝒂𝒊𝒏𝑮𝒂𝒕𝒆

𝑺𝒐𝒖𝒓𝒄𝒆

𝑫𝒓𝒂𝒊𝒏𝑮𝒂𝒕𝒆

𝑪𝟑

𝑽𝑫𝑫

𝑶𝒖𝒕𝒑𝒖𝒕𝑰𝒏𝒑𝒖𝒕

𝑽𝑫𝑫1-poly 9-metal 𝑻𝑺𝑴𝑪 𝟔𝟓𝒏𝒎 𝒑𝒓𝒐𝒄𝒆𝒔𝒔

17 um

2 um

33 um

Metal stack-up & EM structure

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II. Ka-band LNA design [Layout]

Simulated S11, S22, Sopt Layout

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II. Ka-band LNA design [Measurement Setup]

Measurement setup [On-wafer probing]- S-parameter : N5224A(Keysight), GSG probe (GGB)

- Noise Figure : GSG probe (GGB), EXA N9010 Signal Analyzer

(Keysight) Noise source 346CK40 (Keysight),

Pre-Amplifier U7227 (Keysight).

Chip microphotograph

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II. Ka-band LNA design [Measurement Results]

Good correspondance Excellent gain flatness

NFave = 2.27

Low noise figure

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II. Ka-band LNA design [Measurement Results]

100 MHz

800 MHz 2000 MHz

2-tone measurements

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II. Ka-band LNA design [Measurement Results]

This work [7] MWCL 2018 [8] TCAS-2 2018 [9] IMS 2018 [10] MWCL 2019

Technology 65-nm CMOS 40-nm CMOS 28-nm CMOS 45-nm CMOS SOI 0.1-μm GaN-Si

Topology 2-stage CS 3-stage CC 2-stage CC 1-stage CC 3-stage CS

Frequency [GHz] 22.9–32.9 27.8 33 28 22–30

Gain [dB] 18.26-18.64 27.1 18.6 12.8 19.5–22.5

3-dB bandwidth [GHz] 10 7.4 4.4 17 8

Gain variation [dB]± 0.19

(24–32 GHz)3 NR 1.2 NR

Noise figure [dB] 2.27 3.3-4.3 4.9 1.4 0.4-1.1

Power dissipation [mW] 10.0 31.4 9.7 15.0 210.0

𝐼𝐼𝑃3 [dBm] -10.4 -12.6 -15.5 5 15.8

Core area [mm²] 0.11 0.26 0.19 0.3 2.21

FOM1 968 409 83 189 16

FOM2 8009 639 54 33908 911

𝑭𝒐𝑴𝟏 =𝑮𝒂𝒊𝒏[𝒂𝒃𝒔.]×𝑩𝑾𝟑𝒅𝑩[𝑮𝑯𝒛]

𝑭−𝟏 𝒂𝒃𝒔. ×𝑷𝑫𝑪[𝒎𝑾]×𝑪𝒐𝒓𝒆 𝒔𝒊𝒛𝒆[𝒎𝒎𝟐]𝑭𝒐𝑴𝟐 =

𝑮𝒂𝒊𝒏[𝒂𝒃𝒔.]×𝑩𝑾𝟑𝒅𝑩[𝑮𝑯𝒛]×𝑰𝑰𝑷𝟑[𝒎𝑾]

𝑭−𝟏 𝒂𝒃𝒔. ×𝑷𝑫𝑪 𝒎𝑾 ×𝑪𝒐𝒓𝒆 𝒔𝒊𝒛𝒆[𝒎𝒎𝟐]

Comparison with a state of the arts

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II. Ka-band LNA design [ESD Protection issue]

Electrostatic discharge protection

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III. Conclusion

Noise

performance

Power

dissipation

Bandwidth &

Gain ripple

Gain &

LinearityChip size

Frequency band

= 22.9 – 32.9 GHz

Gain ripple =

± .0.19 dB

Gain : 18.6 dB

Dc-power : 10.0 mW

Compact = 0.11 𝒎𝒎𝟐IIP3 > -10.4 dBm

NF = 2.27 dB

Smallest size

Smallest NF in reported CMOS LNA

Well balanced

LNA

Excellent gain flatnessLow power consumption

High linearity

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REFERENCES

[1] S. Onoe, “Evolution of 5G mobile technology toward 2020 and beyond,” in IEEE Int. Solid-State Circuits Conf.

(ISSCC) Dig. Tech. Papers, Jan./Feb. 2016, pp. 23–28.

[2] H.-T. Kim et al., “A 28 GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular

system,” in Proc. IEEE RFIC, Honolulu, HI, USA, pp. 69–72, Jun. 2017.

[3] R. Garg and A. S. Natarajan, “A 28 GHz low-power phased-array receiver front-end with 360° RTPS phase shift

range,” IEEE Trans. Microw. Theory Tech., vol. 65, no. 11, pp. 4703–4714, Nov. 2017.

[4] Y. Park, C.-H. Lee, J. D. Cressler, and J. Laskar, “The analysis of UWB SiGe HBT LNA for its noise, linearity, and

minimum group delay variation,” IEEE Trans. Microw. Theory Tech., vol. 54, pp. 1687–1697, Apr. 2006.

[5] Mcwhorter, M.M, Pettit, J.M, “The Design of Staggered Tuned Double Tuned Amplifier for Arbitrarily Large

Bandwidth,” proceedings of the IRE volume 33, pp: 923-931, August 1955

[6] S. Shekhar, J. S. Walling, and D. J. Allstot, “Bandwidth extension techniques for CMOS amplifiers,” IEEE J. Solid-

State Circuits, vol. 41, no. 11, pp. 2424–2438, Nov. 2006.

[7] M. Elkholy, S. Shakib, J. Dunworth, V. Aparin, and K. Entesari, “A wideband variable gain LNA with high OIP3 for

5G using 40-nm bulk CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 28, no. 1, pp. 64–66, Jan. 2018.

[8] M. K. Hedayati, A. Abdipour, R. S. Shirazi, C. Cetintepe, and R. B. Staszewski, “A 33-GHz LNA for 5G wireless

systems in 28-nm bulk CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 10, pp. 1460–1464, Oct. 2018.

[9] C. Li, O. El-Aassar, A. Kumar, M. Boenke, and G. M. Rebeiz, “LNA design with CMOS SOI process-l.4 dB NF K/Ka

band LNA,” in IEEE MTT-S Int. Microw. Symp. Dig., Philadelphia, PA, USA, Jun. 2018, pp. 1484–1486.

[10] X. Tong, S. Zhang, P. Zheng, Y. Huang, J. Xu, X. Shi, and R. Wang, “A 22–30-GHz GaN low-noise amplifier with

0.4–1.1-dB noise figure,” IEEE Microw. Wireless Compon. Lett., vol. 29, no. 2, pp. 134–136, Jan. 2019.

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