a bist architecture for sigma delta adc testing based on embedded noeb self-test and cordic...
DESCRIPTION
A BIST Architecture for Sigma Delta ADC Testing Based on Embedded NOEB Self-Test and CORDIC AlgorithmTRANSCRIPT
11/16/16
Design & Technology of Integrated Systems in nanoscale era (DTIS’10)
A BIST Architecture for Sigma Delta ADC Testing Based on Embedded
NOEB Self-Test and CORDIC Algorithm
Nabil CHOUBALaroussi Bouzaida
STMicroelectronics Tunis, Tunisia
22/16/16
OVERVIEW
Audio 16-bit ADC architecture
Discussion : Advantages/Limitations8
SILICON VALIDATION Chip & Board7
Cordic based BIST architecture5
On-chip sine-wave fitting4
High-precision binary stimulus3
Conclusions
2
9
Matlab : Simulation results6
Introduction ADC Test 1
33/16/16
1. Introduction ADC Test
• Static test : Histogram test - offset
- gain
- Integral non linearity (INL)
- Differential non linearity (DNL)
ADC
Analog sine wave (or ramp) input test signal
in out
The number of occurrences (or hits) of each code is directly proportional to the width of the code.
44/16/16
1. Introduction
ADC Test
• Dynamic test : FFT test or sine wave fitting- Total Harmonic Distortion (THD)
- Signal-to-Noise Ratio and Distortion (SNRD)
or Number Of Effective Bits (NOEB)
- Spurious-Free Dynamic Range
Analog sine wave input test signal
Binary input test signal (code sine wave signal ) Or
M
nnn
noiserms yyM 1
, 2_1
2/1
Where:yn :is the test signal coming from ADC
y’n is the fitted reference signal
M is the number of used sampled valuesFrom rms_noise we can find SNRD & NOEB
IEEE Std 1241-2000
∆∑ ADC
55/16/16
2. AUDIO 16-bit SD ADC ARCHITECTURE
Test Vehicle :
SPECIFICATIONS:- SNDR: 96 dB (16 bits)- Signal bandwidth: 22.05 kHz - Clock frequency: 12.288 MHz- Output Rate: 48 kHz (OSR=256)- Input Full Range: 1.4VPP
2nd ORDER ANALOG MODULATOR
Wooley et al. (1991) 2zzSTF
Digital Decimation Filter
4 stages (IIR Design)
66/16/16
3. HIGH-PRECISION BINARY STIMULUS (1)
STIMULUS GENERATION
PERIODICAL REPETITION OF A BINARYSTREAM ENCODING A SINUSOIDAL SIGNAL
(Roberts et al. 1999)
Use a software 3rd order modulator
Optimise the input phase and the N-window selection.
store the optimised N-bitstimulus in the chip (ROM)
N-Window
N-bit
ROM2252 bits
77/16/16
3. HIGH-PRECISION BINARY STIMULUS (2)
f
For N=2252 and fSAMPLING= 12.28 MHz
@ 5 kHz 0.8Vpp STIMULUS
S/THDAUDIO
- fSTIMULUS= 5.46 kHz
- 3 harmonics in the audio band
- 16-bit precision
Attenuation to avoid the modulator saturation
(Cheng et al. 2002)
2rd order -coded stimulus
88/16/16
563-POINT REFERENCE SIGNAL
SNDR=113.89 dB
Special effort design in the decimation filter: 21-bit path 23-bit path
In general, a sine-wave fitting implementation needs: sines
Reuse Decimation Filterand Binary Stimulus
to generate
A Synchronised Reference Signal of 19-bit
The old approach will:
4. ON-CHIP SINE-WAVE FITTING (1)
99/16/16
4. ON-CHIP SINE-WAVE FITTING (2)
SINE-WAVE CURVE
FITTING ALGORITHM
Adapt Amplitude and DC value of reference signal to match output response
Calculate the amplitude by correlation
Adapt the reference signal to match the actual response
Calculate the DC valueby averaging
Calculate the error SNDR
We need 25-bit adders and multipliers
BIST Overhead ~40% of ADC~
1010/16/16
5. Reference signal in SINE-WAVE FITTING
2-ORDER ∆∑ MODULATOR
STAGESDECIMATION
FILTER
Reference Signal
Generated by CORDIC
16bits OUT
19bits
SINE-WAVE FITTING Algorithm
Need of 3 bits more precise Reference signal than the ADC output
Solution :
-Use CORDIC algorithm for sine generation (as reference)
calc
1111/16/16
Amplitude
α
Amplitude*sin(α)
Output signal :
The CORDIC is used to generate the reference sine signal
CORDIC internal structure
3 adder, 3 register, 2 barrel shifter, 3 mux, Atan logic
Input Angle : α
5. Reference signal in SINE-WAVE FITTING (Cordic ARCHITECTURE)
Overt sampling ratio (OSR=256)We use an iterative version for the CORDIC for less area overhead
1212/16/16
6. CORDIC BASED BIST ARCHITECTURE
2-ORDER ∆∑ MODULATOR
STAGESDECIMATION
FILTER
Angle generation
16bits
Signature :
Offset, Amplitude, SNDR / NOEB => Or Pass / Fail
Binary TEST signal INPUT
IN OUT
CORDIC
Stimulus generation
ctrl
calc
∆∑ BIST
∆∑ ADC
ADC output signal : Sine signal
Stimulus: generate the binary stimulusAngle : generate angle α for the Cordic : sin(α)Cordic : implement the sine function Calc : perform the sine wave fitting algorithmCtr : is the main controller (The Maestro)
1313/16/16
SINE-WAVE CURVE
FITTING ALGORITHM
Adapt Amplitude and DC value of the reference signal to match the output response
Adapt the reference signal amplitude to match the response one - adapt the signal by acting on the CORDIC initialization
Calculate rma (root-mean-absolute) - no need to make any multiplication !
Calculate the DC value by averaging : A division is necessary - use CORDIC native structures to make the division
Only 3 adders and 3 registers are needed
6. CORDIC BASED BIST ARCHITECTURE
(improvement ON-CHIP SINE-WAVE FITTING)
1414/16/16
Calculate the DC value by averaging
-1- result_reg is used as accumulator
-2- use CORDIC for multiplication by 1/563
-3- offset is stored on offset_reg registerlogic
CORDIC
yn
sin_adc_reg
offset_reg
init_x0_reg
op_type
diff_first
Sin_adc_offsetInput signal
Bist signature
x0
result_reg
6. CORDIC BASED BIST ARCHITECTURE
(Calculate the DC value by averaging )
1515/16/16
Adapt the reference signal amplitude - by adjusting init X0 CORDIC value - init X0 is stored on init_x0_reg
To minimize the hardware overhead && to be independent from the ADC output noise
use of neuronal learning methodologies : by using multi-step X0 adjusting
logic
CORDIC
yn
sin_adc_reg
offset_reg
init_x0_reg
op_type
diff_first
Sin_adc_offsetInput signal
Bist signature
x0
result_reg
6. CORDIC BASED BIST ARCHITECTURE
(Adapt the reference signal amplitude)
1616/16/16
Calculate rma (root-mean-absolute)
logic
CORDIC
yn
sin_adc_reg
offset_reg
init_x0_reg
op_type
diff_first
Sin_adc_offsetInput signal
Bist signature
x0
result_reg
nxxxxN ...)( 211
22
2
2
12 ...)( nxxxxN
Norm 1:
Norm 2:
-1- offset adjustment is done by : offset_reg-2- amplitude adjustment is done by: init_x0_reg-3- result_reg is used as accumulator
6. CORDIC BASED BIST ARCHITECTURE
(Calculate : root-mean-absolute)
1717/16/16
6. Matlab : SIMULATION RESULTS
Very good accuracy (error<1dB) for noise measurement
(dB)ΣΔ Modulator Non-Idealities
SINAD(FS)[A]
SINAD(-12dB FS)
[B]
SINADBIST[C]
BISTError
[C]-[A]
BISTError
[C]-[B]
Fault-Free Modulator 96.66 98.68 98.07 1.41 -0.61
KTC Noise (C=0.1pF) 90.44 90.62 90.67 0.23 0.05
KTC Noise (C=0.01pF) 81.12 81.19 81.30 0.18 0.11
Bandgap Noise (50µVrms) 94.43 95.23 95.02 0.59 -0.21
Opamp Noise (100µVrms) 80.40 80.39 80.49 0.09 0.10
Power Supply Noise (500µVrms) 77.36 77.32 77.39 0.03 0.07
Integrator Leakage (LLK=0.995) 96.19 98.34 96.53 0.34 -1.81
Integrator Leakage (LLK=0.98) 91.23 94.98 88.63 -2.60 -6.35
(β3,INTEGRATOR = -0.004%) 91.28 98.73 97.69 6.41 -1.04
Very good detection of integrator leakage degradation (LLK)
For defects which may introduce distortion the error is greater: - Stimulus is attenuated
- Our test signal is binaryLimitation on weak distortion detection
(not a limitation in AUDIO applications)
1818/16/16
7. SILICON VALIDATION: Chip & Board
HCMOS9 Prototype:- 3.3V analogue and mixed-signal already fabricated
Board Test:- Digital filter implemented in a FPGA
-experimental results Done
1919/16/16
BIST fault coverage (method: same ADC, parameters varying)
Defect label
SNRDIEEE
standard
SNRDVHDLBIST
[Difference] IEEE vs
VHDL BISTTest
Result
90 (fault Free) 84.646956 8.37E+01 0.9467960 Pass
94 78.882325 7.82E+01 0.7288150 Fail
82 80.530554 8.01E+01 0.3916340 Fail
9 76.25735 7.63E+01 0.0092600 Fail
6B 71.124027 7.24E+01 1.2652630 Fail
11B 64.260295 6.45E+01 0.2102750 Fail
34 59.598019 5.99E+01 0.3196710 Fail
50 0.024882 1.26E-01 0.1015335 Fail
13 52.912328 5.31E+01 0.1600920 Fail
35 49.740523 5.02E+01 0.4150670 Fail
51 0.047735 -4.76E-01 0.5239983 Fail
53 0.010704 -6.56E-01 0.6669335 Fail
16 30.685949 3.12E+01 0.4667410 Fail
37 27.10194 2.75E+01 0.3640400 Fail
42 29.432345 2.99E+01 0.4256950 Fail
38 16.076631 1.69E+01 0.8625690 Fail
19 12.663245 1.33E+01 0.6513350 Fail
7. SILICON VALIDATION: Result
2020/16/16
8. DISCUSSION: Advantages/Limitations
Advantages:
BIST is equivalent to analog -12dBFS sinusoidal test
- 1.5% Overhead area (stereo audio) Smaller in new technologies
- No need for high precision test instrumentation on ATE
- Test time = 30 ms (against ~60 ms~ in FFT test)~300 ms~ in Digital Filtering test)
>10 s in Histogram test)
Limitations:
- It is not a FS Test but should be enough in audio applications
- Parallel & Concurrent tests are easier
2121/16/16
9. CONCLUSIONS
Conclusions
BIST proposal for ADC SNDR test
Reduced test time (0.03 s)
Equivalent to an analog test at -12dBFS
Reduced BIST overhead digital: 1.5% (~10.000 µ, cmos65) Analog + digital: 6% BIST is completely separated from ADC !
Validated results in HCMOS9 silicon prototype
RTL BIST validated on FPGA