A 7 bit 3.52 GHz Current Steering DAC for WiGig
Applications
Thesis to obtain the Master of Science Degree in
Electrical and Computer Engineering
Eng. António Ilídio Rocha Leal
Examination Committee:
Supervisor: Prof. Jorge Manuel dos Santos Ribeiro Fernandes
Members of Committee: Prof. João Manuel Torres Caldinhas Simões Vaz
June 2016
i
Acknowledgements
Firstly, I would like to thank Synopsys for the opportunity to develop this thesis with their
collaboration and using their resources. In particular, I would like to thank Engineer António Leal
for all his guidance and help with practical knowledge which was essential to the project. I would
also like to thank all of the DACs team at Synopsys for their insightful tips throughout the
project.
I would also like to thank Professor Jorge Fernandes for giving me the opportunity to
develop this thesis and for all the guidance throughout the project.
My colleagues Marta Freire and João Ribeiro should be mentioned. I would like to thank
Marta for the friendship we developed during these 5 years at Técnico where we shared an
insane amount of hours working on projects and labs. I would also like to mention João who is
also developing a thesis at Synopsys and with whom I shared many concerns and questions
about the project during our lunch breaks.
My parents must also be mentioned for their support throughout my whole life, allowing
me to take my Master’s Degree and especially during the months I developed the thesis. Even
away they listened to my concerns and victories and encouraged me every step of the way.
My grandfather who during the development of this thesis I lost to the battle against
cancer but to whom I dedicate this thesis. The person who always valued my education and
always encouraged me to thrive for success. My grandmother who was always there for me, to
comfort me and support me.
I would also like to thank my brother for his insightful tips about life and about success
which make me always thrive for the best. I would also like to refer my aunt and uncle for their
encouragement and support.
Finally, I would like to thank my friends, especially my best friend Sara Ribeiro, who
although many times could not count with my presence during these months, was always there
for me with kind words of encouragement.
ii
Abstract
A Digital to Analog Converter (DAC) is a system that translates an input digital code into
a sum of electrical units that appear at the output as an analog electrical signal. In this thesis a
DAC to be used in the 60 GHz radio frequency (RF) band extended from the standard Wi-Fi is
developed. This converter developed in a 28 nm CMOS technology works with 7 bit resolution
input data at a sampling rate of 3.52 GHz.
The architecture used in this DAC is the Current Steering which consists of four main
blocks: Current Source, Driver Circuit, Biasing Circuit and Decoder. The Current Source
generates the current of a branch associated with a bit of the input code that will be switched
on/off to the output, being the output the sum of the currents of the branches that are active.
The Driver Circuit synchronizes and shapes the signals that control the switches in each current
source. The Biasing Circuit generates a stable voltage that bias the Current Source transistors.
The Decoder translates the input bits into thermometer bits.
In this project there is an initial study of the subject to understand the constraints of this
type of converter, a development of a mathematical model to initially predict the behavior of the
circuit, a dimensioning of the complete schematic circuit and finally the layout of the
dimensioned circuit. In each phase of the project the results will be further analyzed and the
decisions about the procedure followed will be further discussed.
Keywords: Digital to Analog Converter, Current Steering, WiGig, 28 nm, High Update Rate
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Resumo
Um Conversor Digital Analógico (DAC) é um sistema que traduz um código de entrada
digital numa soma de unidades eléctricas resultando à saída um sinal eléctrico analógico.
Nesta tese é desenvolvido um DAC para ser utilizado na banda de rádio frequência dos 60
GHz, extensão do standard Wi-Fi. Este conversor, desenvolvido numa tecnologia de 28 nm
CMOS, funciona para códigos de entrada de 7 bit a uma frequência de amostragem de 3.52
GHz.
A arquitectura utilizada é a “Current Steering” constituída por quatro blocos principais:
fonte de corrente,“Driver”, circuito de polarização e descodificador. A fonte de corrente gera a
corrente de cada ramo associado a um bit do código de entrada que será activado ou não para
a saída, resultando esta como a soma das contribuições dos ramos da fonte de corrente que
estão activos. O circuito de “Driver” sincroniza e molda as formas de onda que controlam os
interruptores em cada fonte de corrente. O circuito de polarização gera uma tensão estável que
polariza os transístores da fonte de corrente. O descodificador traduz os bits de entrada em bits
termómetro.
Neste projecto é feito um estudo do tema de forma a compreender as restrições deste
tipo de conversor, é elaborado um modelo matemático para prever o comportamento do
circuito, é feito o dimensionamento do esquemático do circuito e por fim é feito o layout do
circuito dimensionado. Em cada fase do projecto os resultados obtidos são analisados e as
decisões tomadas em relação ao procedimento seguido são discutidas.
Palavras-chave: Conversor Digital Analógico, “Current Steering”, WiGig, 28 nm, frequência de
amostragem elevada
2. Digital to Analog Converter: Definition and Characterization ................................................. 6
2.1 Performance Specifications ........................................................................................... 6
2.2 DAC Architectures ......................................................................................................... 8
3.2 Basic Blocks ................................................................................................................ 15
3.3 Static/Dynamic Analysis .............................................................................................. 20
3.3.1 Static Behavior .......................................................................................................... 20
3.3.2 Dynamic Behavior ................................................................................................... 23
4.1 Level of Segmentation ................................................................................................. 25
4.2 Current Source Design ................................................................................................ 27
4.3 Biasing Circuit Design ................................................................................................. 33
4.4 Latch and Driver Circuit Design ................................................................................... 37
4.5 Decoder Architecture ................................................................................................... 40
4.6 Clock Driver ................................................................................................................. 44
4.7 Design Constraints ...................................................................................................... 45
5. Layout ................................................................................................................................... 55
5.2 Results of the Layout Blocks ....................................................................................... 58
v
5.2.3 Current Source ........................................................................................................ 62
5.2.4 Biasing Circuit .......................................................................................................... 64
5.2.5 Clock Driver ............................................................................................................. 67
5.2.7 Complete DAC ......................................................................................................... 71
7. Future Work.......................................................................................................................... 77
List of Figures
Figure 1 – Example of the device scaling by . [19] ..................................................................... 4
Figure 2 – Example of some metrics of the DAC. ......................................................................... 7
Figure 3 – Output spectrum of the DAC with representation of the harmonics of the signal and
the SFDR. ...................................................................................................................................... 8
Figure 4 –Example of the resistor string DAC architecture. .......................................................... 9
Figure 5 – Example of the binary weighted resistor DAC architecture. ...................................... 10
Figure 6 – R-2R resistor ladder DAC architecture. ..................................................................... 10
Figure 7 – Example of the capacitor DAC architecture. .............................................................. 11
Figure 8 – Example of a Current Steering architecture with two types of implementation a) The
Binary Implementation and b) The Unary Implementation. ......................................................... 12
Figure 9 - Types of Output: a) Single-Ended Output and b) Differential Output. ........................ 13
Figure 10 – Current Steering Architecture with a segmented implementation. .......................... 15
Figure 11 – Basic Block Diagram for a Segmented Current Steering DAC. ............................... 16
Figure 12 – Example of the topology of a driver. ........................................................................ 17
Figure 13 – Example of the topology of a) level shifter and b) latch. .......................................... 17
Figure 14 – Example of the topology of a current cell a) single and b) cascode. ....................... 18
Figure 15 – Schematic of a basic current mirror. ........................................................................ 19
Figure 16 – Schematic of a cascode current mirror. ................................................................... 20
Figure 17 – Comparison between the INL_yield obtained by [17] through Monte Carlo
simulations and the INL_yield obtained through the High Level Model of the DAC developed in
this project. .................................................................................................................................. 26
Figure 18 – Topology of the basic current cell. ........................................................................... 28
Figure 19 – Topology of the current source cell with a cascode transistor. ................................ 29
Figure 20 – a) Schematic of the basic current cell, b) Output impedance seen from the drain of
the switch transistor over frequency. ........................................................................................... 30
Figure 21 – a) Schematic of the basic current cell with cascode topology, b) Output impedance
of the cell over frequency. ........................................................................................................... 31
Figure 22 – Example of the current mirror of the Biasing Circuit for the Current Source Array. . 33
Figure 23 – Example of the circuit for the Reference Current Generator. .................................. 34
Figure 24 – Circuit of the one stage OpAmp and the second stage which is the current
reference. .................................................................................................................................... 35
Figure 25 – Circuit of the Voltage Reference Generator. ............................................................ 36
Figure 26 – Schematic of the Current Reference of the OpAmp. ............................................... 37
Figure 27 – Example of a driver with crossing point due to rise and fall time. ............................ 38
Figure 28 – Flip Flop used in the Driver. ..................................................................................... 39
Figure 29 – Diagram of the behavior of the flip flop. ................................................................... 40
Figure 30 – Thermometer Row and Column Decoder Matrix Architecture. ................................ 41
Figure 31 – Local Decoder of the Thermometer Decoder Matrix. ............................................... 41
Figure 32 – Logic Circuits for each of the outputs of the Row and Column Decoder. ................ 42
Figure 33 – Scheme of the Decoding Block of the DAC. ............................................................ 43
Figure 34 – Schematic of the Register. ....................................................................................... 43
Figure 35 – Driver circuit using a cascade of inverters to drive a capacitive load. ..................... 44
Figure 36 – Spike in the common node due to switching errors. ................................................ 46
Figure 37 – Output signal influence on the common node of the Current Source. ..................... 48
Figure 38 – The ideal sampling moments (dashed line) and the actual sampling moments due to
jitter. ............................................................................................................................................. 49
Figure 39 - Waveforms of the Input Bits, the Clock and the Output Differential Signal for the
Complete Schematic Circuit. ....................................................................................................... 50
Figure 40 – Frequency Spectrum for the Differential Output of the DAC for the Complete
Schematic Circuit in typical corner. ............................................................................................. 51
Figure 41 – Variation in layer line with minimum width during fabrication. ................................. 56
Figure 42 – Example of layout using Common-centroid technique. ........................................... 57
Figure 43 – Example of layout using Cross-Coupling technique. ............................................... 57
Figure 44 – Layout Planning of the Circuit. ................................................................................. 58
Figure 45 - Layout of the Latch. .................................................................................................. 59
Figure 46 - Layout of the Bank of Latches. ................................................................................. 59
Figure 47 - Layout of the Switch and Cascode transistors of the LSB bit and a thermometer bit.
..................................................................................................................................................... 61
Figure 48 - Layout of the Latches, Switches and Cascode. ........................................................ 61
Figure 49 - Scheme of the Common Centroid used in the Matrix of the Current Source. .......... 62
Figure 50 - Layout of the Matrix of Current Source Transistors. ................................................. 62
Figure 51 – Layout of the Current Source, Cascode, Switches and Latches. ............................ 63
Figure 52 - Layout of the Voltage Reference Generator. ............................................................ 65
Figure 53 - Layout of the Current Reference Generator. ............................................................ 65
Figure 54 - Layout of the OpAmp. ............................................................................................... 65
Figure 55 – Layout of the Biasing Reference of the OpAmp. ..................................................... 66
Figure 56 - Layout of the Complete Biasing Circuit. .................................................................... 66
Figure 57 - Layout of the Clock Driver. ....................................................................................... 68
Figure 58 – Layout of the Latency Equalizer. .............................................................................. 70
Figure 59 – Layout of a Register. ................................................................................................ 70
Figure 60 – Layout of the Local Decoder of the Matrix Decoder. ............................................... 70
Figure 61 - Layout of the Decoder of the Thermometer Bits. ...................................................... 70
Figure 62 – Layout of the complete Registers and Decoder Block. ............................................ 71
Figure 63 – Layout of the Complete DAC. .................................................................................. 72
Figure 64 – INL_yield for segmentation 6MSB/1LSB for ()/() = 0.0424 for a differential
Figure 65 – DNL_yield for segmentation 6MSB/1LSB for ()/() = 0.0424 for a differential
output. .......................................................................................................................................... 81
Figure 66 – INL_yield for segmentation 7MSB/0LSB for ()/() = 0.05 for a differential output.
..................................................................................................................................................... 82
Figure 67 – DNL_yield for segmentation 7MSB/0LSB for ()/() = 0.05 for a differential
output. .......................................................................................................................................... 82
Figure 68 - Spectrum of output voltage of the DAC for the circuit with the layout blocks for the
typical corner. .............................................................................................................................. 90
Table 1 – Comparison of published arts with similar specifications. ............................................. 3
Table 2 – Dimension of the transistors in the Current Source. ................................................... 32
Table 3 - Output Current and Output Impedance of the Current Source after dimensioning. .... 32
Table 4 – Values of the current references , 1 and 2 after dimensioning of the
biasing circuit. .............................................................................................................................. 34
Table 5 – Specifications of the OpAmp obtained after dimensioning. ........................................ 35
Table 6 – Voltage Reference obtained after dimensioning of the Voltage Reference Generator.
..................................................................................................................................................... 36
Table 7 – Biasing Current for the OpAmp after dimensioning of the Current Reference Circuit of
the OpAmp. ................................................................................................................................. 37
Table 8 – Rise and Fall Times of the Driver Circuit..................................................................... 38
Table 9 – Value of the Crossing Point of the Control Signals of the Switches. .......................... 39
Table 10 – Truth Table for the Row and Column Decoders of the Thermometer Decoder. ....... 42
Table 11 – Decoding and Latency Time of the Thermometer Decoder and Latency Equalizer . 43
Table 12 – Dynamic Performance of the Complete Schematic Circuit. ...................................... 52
Table 13 – Dynamic Performance of the Schematic Circuit for a 1 resistance in the supply
voltage. ........................................................................................................................................ 53
Table 14 - Dynamic Performance of the Schematic Circuit for Monte Carlo simulations. .......... 54
Table 15 - Dynamic Performance of the DAC considering the circuit with the extracted Layout of
the Bank of Latches. .................................................................................................................... 59
Table 16 – Dynamic Performance Comparison between the Schematic circuit and the circuit
with the extracted Layout of the Bank of Latches ....................................................................... 60
Table 17 – Dynamic Performance Comparison between the circuit with the extracted Layout of
the Bank of Latches and the extracted Layout of the Current Source Block. ............................. 64
Table 18 – Dynamic Performance Comparison between the Layout of the Bank of Latches and
the Layout of the Current Source Block. ..................................................................................... 67
Table 19 – Dynamic Performance comparison between the circuit with the Layout of the Current
Source Block and Biasing Circuit and the circuit with the Layout of the Current Source Block,
Biasing Circuit and Clock Driver. ................................................................................................. 69
Table 20 – Dynamic Performance of the DAC considering the Layout of the Current Source
Block, the Biasing Circuit, the Clock Driver and the Decoder. .................................................... 74
Table 21 – Dynamic Performance of the DAC considering the Layout of the Current Source
Block, the Biasing Circuit, the Clock Driver and the Decoder with a resistance of 1 in the
supply voltage.............................................................................................................................. 75
Table 22 - Performance Comparison of Published arts with the work developed. ..................... 76
Table 23 – INL/DNL specification computed through the high level model of the DAC for a given
segmentation. .............................................................................................................................. 83
x
Table 24 – Dynamic specifications not considering jitter computed through the high level model
of the DAC. .................................................................................................................................. 83
Table 25 – Dynamic specifications considering jitter computed through the high level model of
the DAC. ...................................................................................................................................... 83
Table 26 – Dimensions of the transistor of the Current Reference Generator. .......................... 83
Table 27 – Dimensions of the transistors of the OpAmp. ........................................................... 84
Table 28 – Dimensions of the transistors of the Voltage Reference Generator. ........................ 84
Table 29 - Dimensions of the transistors and resistor of the Current Reference of the OpAmp. 84
Table 30 - Dimensions of the transistors of the Driver. ............................................................... 84
Table 31 - Dimensions of the transistors of the Flip Flop of the Driver. ...................................... 84
Table 32 - Dimensions of the transistors of the Local Decoder. ................................................. 85
Table 33 – Dimensions of the transistors of the Row and Column Decoders. ........................... 85
Table 34 - Dimensions of the transistors of the Latency Equalizer. ............................................ 85
Table 35 - Dimensions of the transistors of the Register. ........................................................... 86
Table 36 - Dimensions of the transistors of the Clock Driver. ..................................................... 86
Table 37 – Corners Description ................................................................................................... 87
Table 38 - Dynamic Performance of the DAC considering the Layout of Latches, Switches,
Cascode and Current Source transistors. ................................................................................... 88
Table 39 - Dynamic Performance of the DAC considering the Current Source Block and the
Biasing Circuit.............................................................................................................................. 88
Table 40 - Dynamic Performance of the DAC considering the Layout of the Current Source
Block, the Biasing Circuit and the Clock Driver. .......................................................................... 89
Table 41 – Differences in the Dynamic Performance between the layout and schematic. ......... 91
xi
SNDR – Signal to Noise plus Distortion Ratio
INL – Integral Non-Linearity Error
DNL – Differential Non-Linearity Error
LSB – Least Significant Bit
MSB – Most Significant Bit
THD – Total Harmonic Distortion
W – Width
L – Length
1. Introduction
The project described in this report consists on the development of a Digital to Analog
Converter (DAC) with 7 bit resolution and a sampling rate of 3.52 GHz to be used in
communication systems exploring the high frequency spectral band around 60 GHz. The
resulting DAC needs an SNDR (Signal to Noise plus Distortion Ratio) of about 35 dB and an
INL/DNL (Integral Non-Linearity Error / Differential Non-Linearity Error) of about 1 LSB. The
DAC is to be implemented in a 28 nm CMOS technology. This chapter presents the motivation
for developing this system, the work already done in this field and a brief analysis of the
technology in which the circuit is going to be implemented.
1.1 Motivation
Telecommunications systems nowadays require high performance and high speed
digital and analog systems integrated on one chip at the lowest possible cost. These new
telecommunication devices have evolved towards broadband systems with moderate signal-to-
noise ratios using data converters that according to [1] have to operate at ever increasing
sampling rates, but requiring less precision. An example of these new requirements is the use
of the 60 GHz radio frequency (RF) band extended from the standard Wi-Fi, also known as
WiGig (IEEE 802.11ad standard), with ultra-wide communication bandwidth. This allows the
equipment to achieve multi gigabit per second data rates in indoor wireless transmissions. In
this standard according to [2] and [3], it is possible to use two modulation schemes in
transmission: the single carrier (SC) with frequency sampling of 3.52 GHz and bandwidth of
1.76 GHz and the orthogonal frequency-division multiplexing (OFDM) with frequency sampling
of 2.64 GHz and a bandwidth of 2.16 GHz.
Since the information transmitted through wireless is digital data but the signals used in
the devices are analog signals, like current or voltage, it is essential to use data converters. In
most systems-on-chip, according to [4], these data converters often limit the performance of the
overall system, so it is essential they achieve the appropriate speed and resolution to enable
high data rates. In the case of ultra-wideband systems like WiGig the requirement nowadays is
for very high speed but low resolution data converters.
Today there is a growing need for energy efficient systems, especially in the
communications mass market. Reducing the power consumption of the devices and hence
having a more efficient system can be achieved by downscaling the technology. However the
scaling of the technology in DACs is very challenging because the reduction of the gate oxide
thickness imposes a limit to the maximum voltage that can be applied to the device, forcing in
many cases the circuits to be design with two supply voltages. Moreover, the threshold voltage
of the transistors cannot be scaled accordingly. So designing DACs becomes more challenging
because the freedom of voltage margins are much lower. These most advanced CMOS
technologies also feature reduced voltage gain of the transistors, increasing the distortion of the
2
DAC as stated in [5]. Another major challenge on DACs designed for communication
applications, according to [6], is that they require a large SFDR, which is not straightforward to
achieve at high signal frequencies.
This project will be a contribution to the development of DACs which combine a high
update rate and a low power supply. Since these two specifications combined in scaled
technologies like the 28 nm present a challenge to the designers, this project will be a step
forward in achieving the performance required while meeting these specifications. Through the
use of different approaches to the topologies of the different blocks of the DAC, the correct
operation of the circuit for low power supply will be assured. The correct dimensioning of the
circuit will guarantee the required specifications while a careful layout will assure the minimum
losses and enhance the maximum performance.
1.2 State of the Art
The first records of the use of a DAC are not in electronic form but rather in hydraulic
form by the use of a metering system, using water tanks, in the nineteenth century in the
Ottoman Empire. Throughout the years as the telecommunication systems evolved so have the
specifications for data converters. The need for systems with larger capacity and higher speed
resulted in the enhancement and proliferation of the electronic data converters.
Throughout the years there were many factors helping to spread these systems: not
only the proliferation of discrete transistor circuits during the sixties, but a number of integrated
circuit building blocks became available which led to size and power reductions in data
converters.
In more recent years there is the trend for power consumption reduction, and along with
it, of the supply voltages. The drop in supply voltages to 5 V, 3.3 V, 2.5 V, and 1.8 V have
followed as CMOS line spacing shrank to 0.6 µm, 0.35 µm, 0.25 µm, and 0.18 µm. The resulting
smaller surface mount and chip-scale packages, according to [7], results in a "smart
partitioning" that can offer a higher performance and more cost effective solution, much more
adaptable to different systems than the simple system on chip.
Nowadays depending on their purpose we can find DACs with an accuracy around two
dozens of bits or update rates of a few Gigasamples/s, not simultaneously since there is a
trade-off between resolution and update rate. An example of the high accuracy DACs is the 15
bit DAC presented in [8] and an example of the high update rate DACs is the 8GS/s 6 bit DAC
presented in [9].
Regarding the specifications of this project we can find some examples of papers that
have similar content. In recent publications like [10], a DAC intended for WiGig applications with
a sampling rate of 3.1 GS/s, 6 bit resolution, a SFDR ≥ 37.2 dB and a SNDR ≥ 29 dB over the
Nyquist input in a 90 nm technology is presented. The approach when designing this DAC, in
order to have a wide linear band, was to use a topology with SUC (Stacked Unit Cell). In order
to reduce the power consumption and the hardware overhead, a full binary topology was
3
implemented. Some other examples with similar specifications are presented in Table 1
regarding the contents in [11], [12] and [13].
In [11] a DAC with a 3.5 GS/s sampling rate, 6 bit resolution and a SFDR > 40 dB over
800 MHz was implemented in a 28 nm technology. In this design the use of a cascode topology
is avoided, so the voltage headroom for the current source transistor increases and a CML
(Current-Mode Logic) data switching scheme is used providing natural differential signaling for
the switches of the current source. In [12] is presented a DAC with a 3.3 GS/s sampling rate, 6
bit resolution and a SFDR of 36.4 dB at a Nyquist input signal, implemented in a 90 nm
technology. Similar to [10] this paper presents a SUC implementation in order to reduce the
parasitic capacitance in the current source by reducing the interconnection from the current
source to the current switch. Finally in [13] a DAC with 3 GS/s sampling rate, 6 bit resolution
and a SFDR > 36 dB over the Nyquist frequency at 3 GS/s is implemented in a 90 nm
technology. The main difference to the other publications is that it uses what they call a bipolar
topology for the current source with both NMOS and PMOS transistors which presents half of
the power consumption of an implementation with only either NMOS or PMOS transistors.
Table 1 – Comparison of published arts with similar specifications.
Reference [10] [11] [12] [13]
Sampling Rate (GS/s) 3.1 3.5 3.3 3
Resolution (bit) 6 6 6 6
Technology (nm) 90 28 90 90
SFDR @ /2 (dB) 37.2 30.6 36.4 36.0
SNDR @ /2 (dB) 29 n.a. n.a. n.a.
INL/DNL (LSB) 0.09/0.06 0.03/0.03 0.25/0.22 0.07/0.05
Power Consumption (mW) 17.7 53.0 47.0 8.3
Core Area (2) 0.038 0.035 0.055 0.045
1.3 Technology: 28 nm CMOS
The trend across the years on integrated circuits has been for lower cost, higher speed,
higher density and lower power consumption devices. According to [14] scaling the transistors
dimensions has been the key for today systems with higher performance, reduced cost and
reduced physical size. In this reduction the limits of the CMOS (Complementary Metal Oxide
Semiconductor) have been reached and surpassed while the basic design of the transistors has
been kept almost the same.
The downscale of the technology has set a lot of demands on the properties of the 2
gate oxide. Although it offers several advantages and its properties and processing techniques
have been analysed for decades, there is a limitation on the ability to further reduce the gate
oxide thickness without risking the breakdown of the device. Recently this reduction has been
4
slower, when compared with previous pace, because of issues like the process controllability,
high leakage current or reliability. A very small variation on the device thickness can result in
changes in the device operation condition which makes it very difficult to maintain device
tolerances. The exponential increase in the gate dielectric leakage current causes concerns
regarding the standby power dissipation, reliability and lifetime of the transistor.
The reduction of both voltage level and gate oxide thickness when scaling down the
dimensions of the MOSFET results in a higher source to drain leakage current. Since the
electron thermal voltage (/) is constant for room temperature, then the ration between the
operating voltage and the thermal voltage shrinks, so the thermal diffusion electrons lead to a
higher leakage current.
In general according to [15] the ideal scaling of the technology follows three essential
rules:
1. Reduce all the lateral and vertical dimensions by a constant ( < 1);
2. The threshold and supply voltages are reduced by ;
3. The doping levels of the devices are increased by .
The idea is to ensure that the electric fields in the transistor are kept constant since all
these parameters scale proportionally. One of the main impacts of the ideal scaling is the
reduction of the supply voltage but in reality the technology scaling has not followed the ideal
trend. The threshold voltage of MOS transistors has not scaled similarly to the device
dimensions since there are limitations regarding short-channel effects, which doesn’t allow to
obtain the benefits presented in the ideal scaling.
When having a constant scaling , like shown in Figure 1 the physical dimensions of the
device (gate length (L), gate width (W), oxide thickness () and junction depth ()) the supply
voltage () and the threshold voltage () are all reduced by a factor of . So, while the circuit
density increases by 2 the depletion width () decreases by the same factor which is possible
by increasing the substrate doping by . This results in a scaling down of the gate capacitance
( = /) and the drain saturation current () by . The intrinsic switching delay of
the transistor is reduced by since ~/ so the performance of the device increases.
At the same time the power dissipation ~ is reduced by 2 so the power density
remains the same (/()).
Figure 1 – Example of the device scaling by . [19]
5
The main concerns in scaling for 28 nm CMOS technology according to [16] are the
stress effects (induced by interface boundaries between materials with different dopant
densities) which can be mitigated by the use of dummies and equally spaced devices. These
stress effects can cause mobility variation, which influences the bandwidth, the current
mismatch and the gain of the device; diffusion proximity which results from the dopant atoms
scattered from adjacent photoresist that can cause a variation in Vt and the gate leakage which
is due to quantum tunneling effect that can cause noise, mismatch and it can be a low
frequency limiter.
In order to improve the performance of the MOSFET we can apply enhancing of the
carrier transport properties of silicon by strain-induced modification of the electronic band
structure or use high-k gate dielectric and metal gate electrodes which have higher .
Since there are limitations in both scaling by constant voltage which results in an
increase of the electric fields and scaling by constant electric field since the threshold voltage
scaling has not followed the trend, new innovative solutions for the scaling of the transistors
have been studied to ensure the reliability and performance of the devices.
6
and Characterization
The DAC is a system that reconstructs an analog waveform according to a digital word
input. It acts like a sample and hold circuit throughout the signal reconstruction. During each
clock cycle, the output, which is given according to the input word, is steady so the resulting
signal is a series of modulated rectangular pulses. In order to achieve the performance
specifications required in a DAC, there are a number of important parameters defined by [17]
that need to be measured. Depending on the intended use of the DAC some of these
parameters matter most for achieving the specifications. The difference to the ideal behavior is
characterized by a number of performance metrics that characterize the DAC static and
dynamic performance.
2.1 Performance Specifications
There are many different characterization parameters of the DAC, according to its use,
that are useful in comparing the different architectures possible to use. So it is important to
know the meaning of each one, so that we can analyze its performance according to the
intended purpose of the DAC.
Some of the more important parameters are:
Gain Error: The gain error is defined as the deviation of the slope of the transfer
function actually observed compared with the ideal transfer function (theoretically
specified).
Offset Error: The offset error is defined as the constant DC offset of the transfer function
of the DAC, with respect to the ideal transfer function.
Quantization Error: Analog signals represented with a finite number of bits will have an
error between the analog value and its digital representation. This error is the
quantization error and limits the maximum achievable dynamic range of the converter.
Monotonicity: A converter is monotonic if the output increases progressively when
applying a ramp at the converter input. Monotonicity is guaranteed if the deviation from
a best-fit straight line is less than half an LSB.
Differential Non-Linearity Error (DNL): The differential non-linearity error measures the
worst case of deviation between the actual and the ideal step size on two adjacent
codes. It is a measure of the degree to which the steps between the codes are uniform.
A good DNL implies good resolution and a good noise performance since all the steps
have almost the same size, as stated by [18].
Integral Non-Linearity Error (INL): The integral non-linearity error represents the
deviation of the DAC's transfer function from the ideal. It is a measure of the degree to
7
which the line deviates from the ideal straight line through all the states. A good INL
results in a good accuracy and low distortion of a digital waveform being converted.
Effective Number of Bits (ENOB): Defines the number of bits that an ideal converter
would have under the same conditions of the converter considered and is given by:
ENOB =
6.02 bit (1)
Resolution: The resolution of a DAC has been defined by [19] as “The number of bits
used to produce each analog output level. The higher is the number of bits, the smaller
is the analog (voltage or current) output step that could be output level generated. An N-
bit resolution implies producing 2N distinct analog levels”.
Settling Time: The settling time is defined as the time needed for the output to
experience a full scale transition and to settle within a specified error band around its
final value.
Slew Rate: The slew rate is the maximum rate at which the output of the DAC can
change with the changing input and it is given by:
SR =

(2)
Spurious Free Dynamic Range (SFDR): SFDR is defined as the usable dynamic range
of a DAC before spurious noise interferes and distorts the signal as represented in
Figure 3. It is the ratio between the power of the fundamental () and the power of the
largest spur () from DC to the full Nyquist bandwidth (/2):
SFDR = 10 log (
8
Signal to Noise Ratio (SNR): SNR is defined as the ratio of the power of the
fundamental signal to the integrated noise power. Where N the number of bits, the
theoretical SNR is given by:
SNR = 6.02 + 1.76 dB (4)
Signal to Noise-plus-Distortion Ratio (SNDR): The definition of SNDR given by [18] is
the ratio of the power of the fundamental signal () to the total noise () and harmonic
power at the output (), when the input is a sinusoid.
SNDR = 10 log (
) dB (5)
Total Harmonic Distortion (THD): The THD is defined as the ratio of the sum of the
power harmonic components () to the power of the fundamental signal ().
THD = 10 log (
∑ ∞ =2
2.2 DAC Architectures
The architecture used for a DAC depends on the performance parameters in which we
have interest. The output value of the DAC can be formed using voltage, current, charge or
time. Some DACs enable high resolution but require a large area while others may consume
more power but are faster. So there are three main classes of DACs based on the type of
output they provide: resistors (voltage), capacitors (charge) and current sources (current). Every
one of them generates a certain quantity at the output according to the digital input code.
Figure 3 – Output spectrum of the DAC with representation of the harmonics of the signal and the SFDR.
9
Resistor string DAC
In this architecture 2N resistors, where N is the number of bits of the input digital code,
are connected either between two reference voltages or one reference voltage and ground. The
reference voltage is divided in 2N parts, corresponding each node of the resistor string to a
portion. The input code controls the switches, passing the correct voltage to the output. In
Figure 4 it is shown an example of this architecture with a resistor string DAC. Although it is a
very simple architecture and guaranteed to be monotonic, according to [17], high resolution
DACs, higher than 8 bit, occupy a large area of silicon and the delay through the switching
network becomes a great limitation of the DAC speed of operation. Since the impedance of the
resistor string is dependent on the position in the ladder and the time constant formed by the
ladder impedance and the loading capacitor is dependent on the position and the signal value
this architecture will show distortion at high frequency signals, as stated in [20]. In order to
reduce this dependency, according to [21], the output impedance of the resistor string must be
sufficiently high compared to the total resistance of the string. This architecture requires an
amplifier/buffer as an output stage so it serves as a high impedance voltage amplifier/buffer.
Binary weighted resistor DAC
In the structure of this converter, as presented in [17], there are N binary weighted
resistors, where each resistor in the string has a value proportional to the weight of the bit it
represents. The output of this architecture is obtained from the sum of the different current
contributions of the bits that are active. The architecture described for the binary weighted
resistor has an example in Figure 5. The main advantage compared to the resistor string is that
each bit has only one resistor and one switch but the difference in value of the resistors is very
Figure 4 –Example of the resistor string DAC architecture.
10
wide for high resolution DACs. Not only there are large values for resistors but there is no
guaranteed monotonicity and the output may be susceptible to glitches. In this converter, the
output impedance must be very low, so the current distribution does not depend on the actual
setting of the switches. In the case of this architecture the need of an output amplifier/buffer is
related with the need of a low impedance current summing node for the current to voltage
conversion by using a resistive feedback architecture.
R-2R resistor ladder DAC
This topology makes use of switches associated to voltage sources or current sources,
as presented in Figure 6. It is similar to the binary weighted but the resistors only take two
values, either R or 2R. Although compared with the previous solutions we have twice the
number of resistors, this architecture can be implemented using only combinations of resistors
R. These differences result in a smaller area and higher accuracy with low power consumption.
The disadvantage of this topology is the fact that if the switch in the first vertical branch has 1%
larger resistance, the current will split in 0.495 and 0.505 portions limiting the achievable
resolution.
Figure 5 – Example of the binary weighted resistor DAC architecture.
11
Figure 7 – Example of the capacitor DAC architecture.
In general, according to [21], the bandwidth of the buffer is a limitation to the overall
bandwidth of the converter. Regarding the main applications, these types of converters are
used in limited low-resolution and low-cost applications like offset correction.
Capacitor DAC
In this architecture if all the capacitors have the same value, it needs a thermometer
decoded input, using a thermometer decoder explained in Section 3.2. For an architecture
similar to the resistor string DAC with a binary structure, it is possible an implementation with
capacitors with different values. If a bit is active, the capacitor associated with the bit switches
its charge from ground to the reference voltage, resulting the output voltage of the DAC as the
sum of all the charges of the capacitors which have active bits as an input [17]. A simple
example of this architecture is presented in Figure 7. The main limitation of this architecture is
the mismatch between the capacitors, which result in non-linearity errors. The main differences
of this architecture to the resistor scheme is that since there is no need for a constant current
flow it is possible to achieve a good power efficiency and the jitter has a difference influence on
the output. While for voltage and current domain the overall packet consists of the time period
multiplied by the current or voltage amplitude which changes the signal, for charge the total
magnitude of the packet remains the same even if the transfer charges has a little delay [20].
Examples of application of this architecture are DACs that are used in pipeline ADCs or SAR
ADCs.
Current Steering DAC
This architecture provides a current, through the combination of the values of different
current sources. This converter is built with active current sources in which the current cell can
12
Figure 8 – Example of a Current Steering architecture with two types of implementation a) The Binary Implementation and b) The Unary Implementation.
not be turned on or off, instead they have to be steered, to the appropriate summing node(s) so
the biasing required for these circuits is not disturbed. There are three possible implementations
of the coding of the bits that control the switches of the current sources: the binary
implementation, the unary implementation and the segmented implementation. The binary
implementation and the unary implementation of the Current Steering DAC are represented in
Figure 8 a) and Figure 8 b) respectively. The three implementations of the DAC will be further
discussed in Section 3.1.
The output of this architecture can be of two types: a single-ended output or a
differential output. While the first type is mostly used for low frequency instrumentation and
control applications, the differential output is nowadays the primary choice when the spectral
purity and signal quality regarding noise and distortion is the main concern.
When a switch is turned on it connects a fixed output impedance to the output node,
whereas when it turns off its impedance becomes very large. So, the total output impedance is
the combination of the parallel output impedances of the cells that are switched on.
Since in a differential output the output signal is the difference of two single ended
outputs with opposite polarity signals, the harmonic distortion due to even-order tends to be
suppressed and the signal tends to be somewhat immune to disturbance and noise on common
circuit nodes. The use of a differential output also allows the use of only a single ended output
by using just one of the output nodes.
13
In Figure 9 a) is represented the topology of a single ended output and in Figure 9 b) a
differential output. In general this architecture combines a small area with a high update rate.
Figure 9 - Types of Output: a) Single-Ended Output and b) Differential Output.
14
3. Current Steering Architecture
Through the analysis of the different architectures for implementing a DAC and taking
into account the specifications to be pursued in this project, the architecture that is most suitable
is the Current Steering. The resistor string architecture enables high resolution but at the cost of
a large area and it has a limitation on speed because of the large capacitance input in the
buffer. This buffer is a great inconvenient since it has a large power consumption and
introduces distortion to the circuit. The capacitor architecture has been shown not to be a
suitable solution for telecommunication systems, according to [17], because of its nonlinear
behavior, resulting from the driver needed for the capacitors that can have a nonlinear behavior.
Also as it happens for the resistor string, this circuit requires a buffer that has the same
inconveniences explained before. The Current Steering has an output in current form, it has a
lower cost in terms of area, is intrinsically faster and has a more linear behavior than the resistor
and capacitor based architectures, although in general it has a large power consumption, it has
proved to be the best solution for the wanted specifications.
3.1 Different Codification Schemes
There are three different types of codification schemes for the bits of the input code: the
binary implementation, the unary implementation and the segmented implementation. These
different implementations take advantage of different characteristics of the topology, since the
segmentation of a DAC is a crucial parameter because there is a trade-off between the linearity,
the area, the THD, the glitch energy and the segmentation level of the DAC.
The Binary Implementation
In this implementation the coding of the current sources is binary, every switch switches
to the output a current twice as large as the one of the less significant bit before. In this way the
input code can automatically control the switches with no need for additional decoding logic.
This kind of implementation doesn’t always show a monotonic behavior and suffers from a large
DNL and dynamic error. The current sources are all the same but are grouped and switched in
groups of 2i current sources, where i is the number corresponding to the bit weight.
The Unary Implementation
The current sources in this implementation are thermometer coded, having every
current source the same value. The input code is converted to a thermometer code which
controls the switches of each current source independently. This architecture has the advantage
of being monotonic because only one additional current source needs to be switched so that the
output has an extra LSB. When compared with the binary implementation, it has good DNL
error and small dynamic switching errors. Due to the coding and decoding needed it is a lot
more complex and increases significantly the area and power consumption.
15
The Segmented Implementation
Another approach to the current steering architecture is adapting both of the
implementations, the unary and the binary, and combine them to take advantage of the best
aspects of both. Usually the least significant bits are implemented using the binary architecture
and the most significant bits are implemented using the unary implementation. This results in
better compromise between the power, area, complexity of the circuit and the parameters of
analysis of the circuit.
Although INL is independent of the segmentation, the more binary bits used the higher
the DNL is, so in general we should use the maximum number of thermometer decoded bits.
The restriction in this analysis, as described in [22], is that the area of the circuit highly
increases with the number of bits used in thermometer code.
3.2 Basic Blocks
It is essential to understand the different basic blocks that constitute the DAC with
Current Steering architecture since each block has a specific function in the circuit and the
design of each component is essential to guarantee the overall performance. Since there are
three different types of codification schemes for the input bits that control the switches the basic
blocks will vary according to the implementation chosen. Examples of the blocks of a
segmented Current Steering DAC are represented in Figure 11.
For example, for the segmented implementation, which is a combination of the other
two implementations, the basic blocks of a Current Steering DAC are the Thermometer
Decoder, Latency Equalizer, Latch and Driver Circuit, Biasing Circuit, Cascode Current Source
and Current Source. This gives a general view of the basic blocks that may need to be
dimensioned when designing the circuit.
The basic principle of operation of the Segmented Current Steering is that the N input
bit code is split in NLSB least significant bits and NMSB (N = NLSB + NMSB) most significant bits.
The NMSB bits are thermometer decoded and while the decoding occurs the NLSB bits are
delayed in the Latency Equalizer. When the processing of all the bits is finished the current
sources are commuted according to the bits by complementary switches synchronized by
latches and drivers circuits.
16
Figure 11 – Basic Block Diagram for a Segmented Current Steering DAC.
Thermometer Decoder
According to the type of implementation of the Current Steering architecture it must be
needed the use of a thermometer decoder for the switching scheme. The thermometer decoder
receives the input bits of the DAC and translates the input code and the thermometer code at its
output. This component, as stated in [17], can be of three major types:
Row and column decoder: Combines the two types of decoder, the row decoder
and the column decoder, from the combination of both signals it determines if the switch
associated with the current source is active or not. This type of architecture is very simple to
implement but the switching scheme optimization is not very flexible.
VHDL decoder: This decoder allows any switching scheme because it
implements the row and column decoder in one single block in VHDL and the array for the
current sources and the array for the switches and the drivers are different. The major drawback
is that the update rate depends on the standard library cell available but it has a high level of
automation.
Custom made decoder: Using a custom made decoder allows the designer a
high speed DAC since it exploits the optimal solution for the implementation. Although it
requires a lot more effort in design, not only it results in high update rate but since the designer
can verify the timing constraints at every point of the circuit it may improve its dynamic behavior.
Latency Equalizer
In this implementation where the least significant bits of the input code are not
thermometer decoded and directly control the switches of the current sources there is the need
for a latency equalizer that guarantees the same overall delay on all the bits that go to the driver
and switches. Since going through the decoder adds a delay to the most significant bits we
have to guarantee that the current sources are active at the same time for all the bits, hence the
need for a latency equalizer for the least significant bits.
17
Figure 12 – Example of the topology of a driver.
Figure 13 – Example of the topology of a) level shifter and b) latch.
Latch and Driver
This block includes the drivers, the level shifters and latches. The driver provides the
signals that control the switches associated with each current cell. It guarantees that both switch
transistors of the current cell are never simultaneously off, preventing glitches at the output. The
idea is to generate complementary waveforms that assure that when a transistor is turned off
the other is turned on. Generating waveforms with non-symmetrical crossover assures this
behavior on the switch transistors. An example of a topology of a driver used in the circuit
presented in [21] is represented in Figure 12.
The level shifter has the function of converting the voltages of digital logic circuits,
where the input bits are processed in the DAC, to the voltages of the analog circuits. As an
example, the digital logic circuit can have a different supply voltage than the analog circuit, so
we have to convert the voltages from one part of the circuit to the other. Some examples of the
topology of the level shifter and of the latch associated with this level shifter are presented in
Figure 13 a) and Figure 13 b). The latches associated with the level shifter assure the
synchronization and shape of the signals to improve the dynamic performance of the circuit.
These latches are inserted between the level shifter and the driver, the first latch is active at
high level and captures the output of the level shifter when the clock signal is “high”, and the
other latch is active at low level and provides its output to the driver when the clock signal is
“low”. To ensure the correct operation at the moment of capture all outputs of the digital decoder
must be established.
18
Figure 14 – Example of the topology of a current cell a) single and b) cascode.
Current Source
The block of the Current Source Array includes all the current sources that are activated
by the driver and latch circuit according to the bits of the input code. The topology selected for
the configuration of each current cell has to take into account random errors that can be
minimized by the area of the transistor operating as current source and the effect of finite output
impedance that can be mitigated by recurring to the cascode configuration. The simplest
topology presented in Figure 14 a) consists of two MOS transistors (Msw) operating as switches
in saturation steering the current from one transistor to the other according to complementary
gate signals and a single MOS transistor (Mcs) operating in saturation with constant gate-source
voltage. To ensure higher output impedance we can use a cascode current cell, as used in
many literature examples like [22], which has a second MOS transistor (Mcas). This circuit,
presented in Figure 14 b), seen by Vout has the output resistance of a double cascode and it is
not such a limitation for the SFDR.
Biasing Circuit
The correct functioning of the Current Source Circuit is dependent on the Biasing Circuit
which defines the gate voltages for the cascode and current source transistors. The Biasing
Circuit usually consists on a set of current mirrors. The design of these current mirrors depends
on important aspects like the supply voltage, process and temperature, output resistance and
matching.
For the current mirror represented in Figure 15 the transistors have to operate in
saturation to guarantee as a stable current. The expression for the drain current for both
1 and 2 transistors in saturation, neglecting channel length modulation, is given by:
19
( − )2 (8)
Since these two identical transistors have equal , if they operate in saturation and
have (
)
1 = (

)
2 , they carry equal current since from (7) and (8) we can conclude that:
Iout = (
IREF (9)
So this circuit allows a precise copying of the reference current independently of the
process and temperature, since we can control the ratio between the current by adjusting the
ratio of their dimensions.
Usually in current mirrors the same length (L) is used in all transistors so the errors due
to side diffusion of the source and drain areas can be neglected. Also, as stated in [15], in short
channel devices the threshold voltage shows dependency on the channel length, so the ratio
between the currents is defined only by the width of the transistors.
This analysis was based on the fact that the channel length modulation () can be
neglected but in reality and especially for minimum length transistors, this effect has significant
impact on the currents copied. Considering this effect the previous relations for the current drain
of the transistors 1and 2 result:
I1 = 1
2 (
20
Although 1 = 1
= 2 due to the circuit associated at the drain node of
2, 2 may not be equal to 2
so the current relation is not only dependent on the ratio
between the dimensions of the transistors.
So, to minimize the effect of the channel length modulation a topology, as the one
represented in Figure 16, with a cascode transistor (3) in the current source may be used.
The transistor 3 allows the 2 transistor to be less sensitive due to the circuit that is
connected to the 3 drain.
To ensure that 1 ≈ 2
in order to have a good current mirroring and since
both sources are connected to ground, 1 ≈ 2
, we need to ensure that the gate voltage
of 3 is = 3 + 1
.
3.3 Static/Dynamic Analysis
The design of a Current Steering DAC for high resolution or high update rates like the
one presented in this project requires a thorough understanding of its static and dynamic
behavior. The performance of the DAC due to its static behavior is related with the matching of
the current source transistors. According to [5] there are two types of errors associated with this
matching, the random errors due to process variations but also the systematic error due to
various gradients. The dynamic behavior of the DAC has a main constraint due to the fact that
for high speed, the second and third harmonic distortion, in the frequency domain, are a
limitation for the spurious free output signal bandwidth. It is crucial to understand this
constraints and how to reduce their effect on the performance of the DAC so we can achieve
better results.
3.3.1 Static Behavior
The static performance of a DAC, as stated in [5] is intrinsically related with the
mismatch of the current source transistors in this architecture. The mismatch can be defined as
Figure 16 – Schematic of a cascode current mirror.
21
the variation in physical quantities of identically designed devices. The matching errors consist
of both random and systematic errors which have to be considered. The systematic mismatch
comes from for example gradients in process parameters, like oxide thickness, doping or
temperature. They can be overcome by using appropriate switching schemes, calibration or
randomization.
The random errors are due to random variations during the fabrication process of
different DACs, in the same process technology, resulting in a different INL performance.
Although the variation may be due to random errors it is essential to predict it within certain
boundaries. The static matching of the current sources sets a lower limit to the INL that is
possible to achieve and to the distortion performance of the DAC. According to [23] the current
mismatch has four major physical effects: edge effects, implantation and surface-state charges,
oxide effects and mobility effects.
The yield figure associated with the INL on DACs defines the percentage of functional
DACs that have a smaller performance than the specification of half an LSB. Taking into
account the research on [10] there are different approaches that can be used to calculate this
yield:
The Lakshmikumar Approach: It gives us a formula to estimate the yield that is
based on the assumption that there is no correlation between the outputs of the DAC, however
it has been considered too optimistic since it only takes into account two outputs and ignores
the rest.
The Monte Carlo Approach: It calculates the output current of the DAC for every
digital input code, taking into account that every current source has a random value derived
from a Gaussian distribution, and calculates the yield by the ratio of the number of functional
DACs and the total number of try-outs.
The New INL_Yield Formula: The idea is that if an INL error occurs when
passing through all the possible codes generated by the 2N-1 digital input words that there is a
50% chance that the error still exists for the code 2N. It doesn’t require the computation time of
the Monte Carlo approach since it is the application of a formula.
In general, although it requires more time of computation, the Monte Carlo approach is
more used when making an estimation of the yield since it provides more accurate results than
the formulas available.
For a MOS transistor in strong inversion the relative standard variation of the drain
current is given by:
. (


) 2
(13)
In the long-channel approximation and according to [5] by the Pelgrom Model presented
in [23] it is given by:
2 (


) =
2
+
22
where and are constant parameters dependent of the technology matching, WL is the
area of the matched transistors and ( − ) is the gate overdrive voltage. The mismatch of
the transistors can be predicted by this model according to [15] and by analysis of the
expression it is possible to conclude that the mismatch error is mainly influenced by the area of
the transistor (WL) and that we should have high gate-source overdrive voltage to minimize
threshold voltage mismatch. Since the area necessary for the current sources determines the
parasitic capacitances it will impact the dynamic performance of the DAC even when employing
cascode transistors. For smaller transistor dimensions in modern CMOS technologies,
according to [21], the matching behavior will be affected by other effects related with the
accuracy of the photolithographic process and influence of pocket implants.
Regarding the systematic errors the main contributors according to [17] are:
Transistor Mismatch Effect: Due to the fact that the mismatch behavior of a
transistor is dependent of its surroundings it can have a negative effect on the static
performance of the DAC. To overcome this effect it should be used dummy transistors around
the current sources to ensure identical surroundings.
Voltage Drop in the Ground Line: The fact that there is a voltage drop along the
ground line will result in non-linearity errors because it will change the output current of different
transistors on the same row. This effect on NMOS current sources can be minimized by either
using appropriate switching schemes or by using wide power supply lines.
Process and Temperature Gradients: Increasing one bit in the resolution of the
DAC can double the area occupied by the unity current source and doubles the number of
current sources in the current source array. So increasing four times the area of the current
source array for every extra bit results in an area so large that gradients have to be considered.
These temperature and process gradients cause non-linearity errors that by using special
switching schemes can be compensated.
When the random errors are the main contributor for the matching precision by
estimating the yield it is possible to understand the minimal requirement and through adjustment
of the active area keep the INL under one LSB. So, it is essential to compensate the systematic
errors in order to keep the random errors dominant, which can happen by using appropriated
switching schemes for the current sources. These switching schemes are layout techniques that
make the different interconnection between the decoder and the switches of the current sources
in order to have optimal process and temperature gradients for the arrays.
The use of DEM (Dynamic Element Matching) techniques increases the static linearity
beyond the limits imposed by random mismatch. According to [21] when using thermometer
decoded arrays the elements to use for a given input code are not unique. Since, in principle,
the members of the array are not distinguishable, an input code can be represented by different
combinations of these elements. It takes advantage of this redundancy of the code
representation to guarantee that errors from individual elements are averaged out over time.
This averaging perception results in an increase in the static accuracy of the DAC. Instead of
directly addressing the DAC elements, it shuffles the data vector and the elements chosen are
23
different according to this shuffling for each sampling interval. An example of these techniques
is the DWA (Data Weighted Averaging) which is a rotation algorithm that cycle through all the
elements at the maximum rate. The first element to be switched on in the current sampling
period is the first element to be switched off in the previous cycle.
Current Source calibration is another technique that tries to minimize the mismatch
before the elements are used. It can be done once after fabrication or continuously in the
background. All the elements are measured and their output is trimmed to the desired value.
Each of the current sources is compared with a constant reference and the difference between
the output current of the element and the reference current is minimized by changing the value
of the element.
All of these techniques have an advantage for systems where the accuracy of the DAC
is the main concern.
Since most applications, emphasizing the telecommunications applications, are mainly
in the frequency domain, both the dynamic and static performance are important because their
non-linearity errors reflect as noise and distortion in the frequency domain.
The major contributors for the dynamic performance of the DAC are according to [17]:
timing errors, capacitive feedthrough from the digital control signals to the output node, voltage
stability of the drain node of the current source transistors and dependency of the output
impedance.
Timing Errors: An example of the timing errors that can have an effect on the
performance is the synchronization of the control signals of the switches of the current sources.
If they are not exactly matched it may result in a glitch error in the output of the DAC. The
solution is to use synchronization blocks immediately before the input of the switch transistors,
so that any delay can be compensated.
Capacitive Feedthrough: The switch transistors of the current sources form a
feedthrough path, because of their gate-drain capacitance, between the digital control signals
and the output. Using a low voltage swing at the input of the switches or by cascoding the
switch transistors the glitch error originated can be minimized. The first solution is easier to
implement since it can use the synchronization circuit used for timing errors. On the other hand,
the cascode can increase the area and can result in distortion because it interferes with the
symmetrical operating principle of the current cell.
Voltage Swing: If there is a time interval where both switch transistors are
conducting it will result in a glitch at the output. So it is necessary to have a switch driver that
can assure a non-symmetrical crossover of the control signals at the input of the switch
transistors. This block can be associated with the synchronization circuit referred for timing
errors. However, for fast switching, the static current of the driver circuit can become quite large
and be susceptible to variations of the supply voltage and temperature.
24
Output Impedance: The output impedance becomes a major factor for the
dynamic performance when we are designing a high resolution DAC since we design the
current cells to have large output impedance so that the INL is very low. Although the cascode
of the current source transistors result in a good INL specification it is only true over a limited
frequency bandwidth, because it has a pole and a zero at finite frequencies. Changing the
location of this pole and zero is not trivial because they are dependent on the gate length L
which is dictated by matching considerations. A solution for this problem is changing the
frequency dependency of the output impedance by placing an extra cascode transistor on top of
either the switch transistors or the current sources transistors resulting in a different frequency
behavior and increasing the DC value.
25
4. Design Methodology of the DAC
In the previous chapters not only the essential parameters when designing a DAC were
defined, but also the different architectures and especially the Current Steering Architecture was
further analyzed. In this chapter we go step by step through the designing methodology of a
DAC with Current Steering Architecture applying the restrictions and specifications of the DAC
required in this project.
4.1 Level of Segmentation
The first issue to be addressed when designing the DAC is the level of segmentation.
According to the different segmentation schemes referred in Section 3.1 there are three
different types of codification: the unary, the binary and the segmented. To define the level of
segmentation, we can apply different approaches but for this specific project we used the Monte
Carlo Approach with simulations for different levels of segmentation and analysis of the results.
According to those conclusions the level of segmentation for this specific DAC is defined.
Using this approach each of the 2 − 1 current sources has a random value derived
from its Gaussian distribution with mean value I and standard deviation σ(I). For each digital
input code, the output current of the DAC is calculated and compared to its ideal value. If the
difference is larger than one LSB the DAC is considered not functional and is rejected. For each
value of σ(I) we repeat this procedure a great number of times (>10000 times) to obtain reliable
results. We can obtain the INL_yield dividing the number of functional DACs, which achieve a
difference lower than one LSB and the total number of tries.
In general, the resolution of the DAC is determined by the mismatch of the current
sources while the update rate is determined by the switch transistors. The dependency of the
DNL error is related with the segmentation level so that in the unary implementation each
transition has the same probability of determining the DNL error, while in the binary
implementation each transition has different probability that has to be simulated. So, the DNL
error strongly increases with the number of bits in binary implementation, compared with the
unary implementation. Even though the INL is independent of the number of LSB bits in binary
codification (NLSB), an increase of these bits results in an increase of the DNL, which as seen in
[22] results in an increase of THD and glitch energy.
The first step in determining the level of segmentation was to make a high level model
of the DAC. This model consisted in a program developed in Matlab that computes the INL/DNL
of the DAC for each input code having as input variables: the level of segmentation (NLSB -
number of bits in binary coding and NMSB – number of bits in thermometer coding), the standard
deviation of the LSB current source (σLSB(I)/I), the sampling frequency (Fs), the input frequency
(Fi) and the input signal.
To measure the INL/DNL the input signal is a ramp that starts in code 0 and ends in
code (2 − 1) where N is the total number of bits of the DAC. From this computation we could
26
either obtain the INL_yield/DNL_yield according to the input code for one given value of
σLSB(I)/I or the INL_yield/DNL_yield according to a given value of σLSB(I)/I for a range of
σLSB(I)/I values.
In order to guarantee that the INL/DNL model developed is according to the real circuit
the results obtained were compared with the results presented in Figure 4.1 in [17] for a DAC
with 10 bit resolution for a range of σLSB(I)/I from 0 to 0.4. For a segmentation of 3 bits in binary
codification and 7 bits in unary codification and for an output current not considering the output
impedance of the DAC the results obtained using this model in comparison with the ones
presented in [17] are represented in Figure 17. For considerations regarding the level of
segmentation of the DAC in this project the INL/DNL was computed using the output voltage
considering the output impedance of the DAC for more accurate results. This output voltage can
be computed considering either a single ended output or a differential output.
The dynamic performance of the DAC was also considered in the model through the
spectral analysis of the SFDR, SNDR, SNR, THD and ENOB. After computing the output
voltage of the DAC, the FFT (Fast Fourier Transform) of the signal was computed and plotted
considering only the Nyquist band (/2) and all the dynamic metrics referred were computed.
Finally, this model also considers one more parameter which is the effect of jitter in the
output signal of the DAC. For a given maximum value of jitter considered, the output signal of
the DAC is computed and the FFT of the signal is generated making the same type of analysis.
Since in this project we pretended to develop a DAC with sampling frequency of 3.52
GHz and a bandwidth of 1.76 GHz, an input signal with Fi = 1.76 GHz and a sampling frequency
of Fs = 3.52 GHz were considered in the analysis. To determine the level of segmentation of the
Figure 17 – Comparison between the INL_yield obtained by [17] through Monte Carlo simulations and the INL_yield obtained through the High Level Model of the DAC developed in this project.
27
DAC the INL/DNL was calculated for segmented implementation with 6 bits in unary
implementation and 1 bit in binary implementation and for a thermometer implementation with 7
bits in unary codification for either a single ended or a differential output. The results of these
simulations considering different σLSB(I)/I are presented in Figure 64, Figure 65, Figure 66 and
Figure 67 (see Attachments).
The values obtained in this analysis are represented in Table 23 (see Attachments) and
regarding the dynamic specifications of the DAC without considering jitter for a segmented
implementation with 6 bits in unary implementation and 1 bit in binary implementation and for a
codification with 7 bits thermometer decoded for a differential output the results are represented
in Table 24 (see Attachments). Regarding the dynamic specifications of the DAC considering
jitter the results are presented in Table 25 (see Attachments).
Since an extra bit in unary codification doubles the area occupied by the latches and
increases the complexity of the layout and since by comparison of the dynamic metrics and of
the INL/DNL the differences between the two segmentations are not relevant to consider the
use of 7 bits in unary implementation, a segmentation with 6 bits in unary codification and 1 bit
in binary codification was chosen for the DAC.
4.2 Current Source Design
The simplest design of the current cell is a single MOS transistor biased with constant
gate to source voltage that operates in saturation region. The switching consists in two MOS
transistors operating as switches with complementary gate signals. The design of this current
cell requires a minimum area for the transistor of the current source, so the random errors are
small and their impact on the relative standard deviation can be neglected. The area of the
transistor can be obtained taking into account the formula (13) obtained from the Pelgrom
Model. Defining the value required for the yield, we derive the precision for the current cell
(
() =
1
( − )2 (16)
From these expressions we conclude that the only degree of freedom is the gate
overdrive voltage given by:
= − (17)
Increasing the gate overdrive voltage results in a decreased of the minimum area
required. So in order to define this voltage we can choose it so that the current source
minimizes the systematic errors. For large values of area, the mismatch is mainly determined
by .
These systematic errors, stated in [17], are mainly caused by the layout and can be
optimized by the switching scheme and a careful layout generation but the finite output
28
Figure 18 – Topology of the basic current cell.
impedance is a major effect. To minimize this effect we can use a topology with cascode
configuration. The simple single current source topology with NMOS is presented in Figure 18
and based on that topology we can analyze the output impedance of the circuit.
The small signal output impedance for the current source and the switch is given by:
≈
(18)
where is the transconductance of the switch transistor, is the drain to source
resistance of the switch transistor ( ) and of the current source transistor (
) as
presented in [24].
In general the output impedance of one single transistor is not high enough to meet the
required static output impedance requirements and the large area defined by the matching
requirements results in a very large parasitic capacitance that deteriorates the high frequency
linearity. Using the cascode topology, presented in Figure 19, as stated in [5] increases the
output impedance in both DC and high frequencies.
For the cascode topology the output impedance is given by:
≈
where is the transconductance of the cascode transistor and
is the drain to source
resistance of the cascode transistor.
The transconductance and the drain to source resistance in general are given by:
= 2

(21)
where K is the number of LSB sources in parallel, is the drain current, is a constant of the
technology, is the drain to source saturation current, is the channel length modulation
parameter and ∅0 is also a technology constant, the built-in junction potential presented in [24].
Since the topology of the circuit is the same for all current sources only the sizes of their
29
Figure 19 – Topology of the current source cell with a cascode transistor.
transistors need to be scaled from the basic current cell, which usually is the LSB current
source, according to their weight. While the DAC static and dynamic performance is mainly
determined by the performance of the basic current source cell, the design of the other
components of the DAC is mainly determined by the speed requirements.
The output impedance of the DAC is a design constraint of the circuit because the finite
output impedance of the DAC is a cause for distortion. According to [