This work was supported by the National Natural Science Foundation of China (No.61076028), Doctoral Program of Higher Education of China (No.20100071120026)

A 3.4dB NF k-band LNA in 65nm CMOS Technology

Jianfei Xu, Na Yan, Qiang Chen, Jianjun Gao1, Xiaoyang Zeng ASIC & System State Key Laboratory, Fudan University Shanghai, China

1School of Information Science and Technology, East China Normal University, Shanghai, China

Abstract— This paper presents a k-band (18-26.5 GHz) high gain low noise amplifier (LNA) in 65-nm CMOS mixed signal process. The LNA has a peak gain of 20.46 dB at 22.45 GHz and a -3 dB bandwidth of 3.8 GHz. S11 of the chip is better than -11 dB and S22 better than -15 dB across the band. The measured smallest noise figure (NF) is 3.4 dB. The whole chip consumes 11mA current under 1.1V supply voltage and occupies an area of 710 μm × 540 μm.

I. INTRODUCTION K-band has been widely used for satellite communication

and radar for a long time. Recently, as the development of LTE, UWB, WIFI, Zigbee and other communication standards, the spectrum below 10 GHz is becoming extremely crowded. More attentions are paid to higher frequency such as 24 GHz (24.0-24.2 GHz ISM band) and 60 GHz (57-64GHz for WLAN or Wireless-HD) for high speed communication [1], [2]. The low cost, high integration level characteristics of CMOS process make it attractive for fabricating RF circuits. As the dimension decrease of CMOS transistors, the performance of CMOS process becomes sufficient for design voluminous RF and mm-wave circuits [3], [4].

This paper describes a k-band LNA fabricated in 65nm CMOS process. In section II, the considerations for design LNA in k-band are illustrated. Then a LNA is designed in section III. Section IV describes the measurement results of the LNA.

II. DESIGN CONSIDERATIONS

A. Optimzation of Transistors RF performance of transistor is interrelated to its geometric

size, such as gate length (L) and unit gate finger width (Wf). As they have great influence on Rg (gate resistance), Rs (source resistance) and Cgb (gate–bulk capacitance). These parameters largely affect fT, fMAX, and NFmin of the transistor. The RF performance influences of L and Wf are investigated in [5], [6]. According to their research, the optimized L is 60nm, and Wf is 1-2μm for 65nm CMOS process.

RB

CB

CS

CD

CG

RgG

S

D

B

Rs

Rd

Cgs

Cgd

Csb

Cdb

Fig. 1 Transistor model with parasitic parameters

To improve simulation accuracy, parasitic parameters are included in the transistor model. The new model is shown in Fig. 1. The parasitic parameters are acquired by EM simulation tool such as HFSS or Momentum. B. Inductor

The inductor performance and model accurateness are crucial to NF, center frequency and impedance matching for LNA design. Both transmission line and spiral inductor can be used for k-band circuit design, but the area of transmission line is much bigger than spiral inductor at k-band for wave length is still longer than 1 cm. Inductor made by top thick metal is a good choice. For parasitic capacitor between inductor metal and substrate are smaller than other metals, and is the parasitic resistor. Consequently, the inductor have better quality factor Q. A 2.5 turn inductor with radio of 15 μm made of top thick metal is simulated by HFSS in Fig. 2 (a) and the simulated performance is shown in Fig. 2 (b). Q of the inductor is higher than 20 at k-band.

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(a)

(b)

Fig. 2 Inductor for k-band: (a) Layout of spiral inductor (b) Simulation reasults of the inductor

C. LNA Topology At frequency well below fT of transistors, the cascode

topology LNA in Fig. 3 provides low noise figure, good input matching and high reverse isolation [4].

Fig. 3 Cascode LNA topology

After the derivations in [7], at deep submicron process the noise parameters and input impedance of the circuit in Fig. 3 are as follows:

2

22 2

(1 ) (1 )5 5

(1 ) (1 )5 5

opt s

gs

c j cZ sL

C c c

δ δα αγ γ

α δ δω αγ γ

− + += −

⎡ ⎤− + +⎢ ⎥

⎣ ⎦

≈1Re[ ]opt s

gs

Z sLsC

− − (1)

1in s T s

gs

Z sL LsC

ω= + + (2)

Compared equation (1) and (2), we can see the fact that the imaginary parts of *

inZ and Zopt are equaled. So if

T sLω = Re[ ]optZ was achieved, *inZ and Zopt are equaled

consequently. As a result, to realize noise match and power match simultaneously, the value of Ls is:

2

22 2

(1 )Re[ ] 5

(1 ) (1 )5 5

opts

Tgs

cZ

LC c c

δαγ

ω α δ δω αγ γ

−= =

⎡ ⎤− + +⎢ ⎥

⎣ ⎦

(3)

III. LNA DESIGN The LNA’s topology is shown in Fig. 4 . To achieve high

voltage gain, two stage cascade topology is used in the LNA. The chip is implemented in TSMC 65nm CMOS process.

Fig. 4 circuit of the k-band LNA

Fig. 5(a) shows the effect of Ls intuitively on Smith Chart. A matching network includes parasitic capacitor of input pad is inserted between input port and gate of M1. It can be viewed as a tapped capacitor network combined with a tapped inductor network. The small signal equivalent circuit of the network is depicted in Fig. 6. Inductor LB in the bias branch is sliced into two inductors: LB1 and LB2. C2 of the tapped inductor matching network is not a real capacitor; it’s the effect of the imaginary part of *

optZ . Assuming *optZ =Ropt -

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jXopt, then C2=1/(ω0Xopt). Ropt is transferred to RI through the tapped inductor matching network, and RI is transferred to ZS through the tapped capacitor network. The relationship between RS, RI and Ropt are:

2

1

1

S

I pad

R CR C C

⎛ ⎞= ⎜ ⎟⎜ ⎟+⎝ ⎠

(4)

2

2

2

I B

opt B G

R LR L L

⎛ ⎞= ⎜ ⎟+⎝ ⎠

(5)

The quality factors of the two matching network are: 0 1

1B

I

LQ

Rω

= (6)

2 0 2optQ R Cω= (7)

From the equations, we can see that Q1 can be defined arbitrarily. Consequently bandwidth of the LNA can be designed within a large range. Intuitionistic view of the effect of the matching network is shown in Fig. 5 (b).

*optZ

0inZ

*optZ

Fig. 5 Impedance transform on Smith Chart: (a) effect of source degenated inductor Ls. (b) effect of the matching network

*optZ

Fig. 6 small signal equivalent circuit of the matching network

Fig. 7 is the post simulation matching results after the whole chip is completed. Gmin is optimum noise reflection coefficient, it’s defined as:

minS opt

S opt

Y YG

Y Y−

=+

(8)

So the closer the curve of Gmin to the origin, the better Zs and Zopt matched. The simulation results show that the impedance and noise match are well achieved.

Fig. 7 Post simulated noise and impedance matching results

Then a resonance network is designed as the load of the first stage. A second stage is added to achieve high gain and better isolation from output to input. An output matching network includes output pad capacitor is added to transfer the output impedance to load impedance (usually 50Ω).

For k-band circuit design, parasitic parameters of strings have a great influence on the performance of the circuit. So the layout of the circuit is carefully optimized. Transistors are located in deep n-well to insulate noise coupling through substrate. Strings between different units are designed as short as possible. For long strings, the parasitic parameters are distilled by EM simulation tool. Inductors are placed apart from each other and dummy are added around the inductors to insulate the inductors’ magnetic induction.The most important of all, resistance of the ground plane is optimized very small and on chip decoupling capacitors of relatively large value are added between power supply and ground.

IV. MEASUREMENT REASULTS The chip is fabricated in TSMC 65nm CMOS MIXED

SIGNAL RF 1P9M process with two top thick metals. The chip is probed using SUMMIT 12000 and the S parameters are measured by network analyzer (Agilent E8363C). The noise finger is measured by noise analyzer (Agilent N8975A).

Fig. 8 Chip micrograph of the LNA

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The measured results are shown in Fig. 9. The measured peak S21 is 20.46 dB at 22.45 GHz. The -3 dB bandwidth of the measured is 3.8 GHz. The measured S11 is better than -11 dB and S22 is better than -15 dB across the band. The measured NF is shown in Fig. 10.The lowest NF is 3.4 dB at 23.5 GHz.

Fig. 9 Measured Results

Fig. 10 Measured noise finger Table I provides a comparison of this work with other k-

band LNAs fabricated in CMOS process. It shows that the LNA of this work has a relatively high gain and low noise under low power consuming.

Table I PERFORMANCE COMPARISON OF THE PROPOSED K-BAND LNAS WITH THIS WORK

Process Peak Gain Frequency

(GHz)

Gain (dB)

NF (dB) PDC (mW) Reference

40nm CMOS 24 13 3.2 4.1 ICICDT2011[8]

90nm CMOS 24 7.5 3.2 10.6 ESSCIRC2005[9]

130nm CMOS 24 14.0 5.0 18 COMCAS08[10]

130nm CMOS 18 22.4 4.1 36 ISSCC08[1]

65nm CMOS 22.45 20.46 3.4 12 This Work

V. CONCLUSION This paper illustrates the design considerations for LNA

working at k-band, and then describes the design of a k-band LNA in 65nm CMOS process. The LNA has low NF, high gain and relatively wide bandwidth. It can be used for k-band satellite receiver, radar or wireless communication at 24 GHz ISM band.

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