a 2.8 mw sub 2 db noise figure inductorless

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1

A 2.8-mW Sub-2-dB Noise-Figure InductorlessWideband CMOS LNA Employing

Multiple FeedbackEhab Ahmed Sobhy, Student Member, IEEE, Ahmed A. Helmy, Student Member, IEEE,

Sebastian Hoyos, Member, IEEE, Kamran Entesari, Member, IEEE, and Edgar Sánchez-Sinencio, Life Fellow, IEEE

Abstract—A wideband low-noise amplifier (LNA), which is a keyblock in the design of broadband receivers for multiband wirelesscommunication standards, is presented in this paper. The LNA isa fully differential common-gate structure. It uses multiple feed-back paths, which add degrees of freedom in the choice of the LNAtransconductance to reduce the noise figure (NF) and increase theamplification. The proposed LNA avoids the use of bulky induc-tors that leads to area and cost saving. A prototype is implementedin IBM 90-nm CMOS technology. It covers the frequency rangeof 100 MHz to 1.77 GHz. The core consumes 2.8 mW from a 2-Vsupply occupying an area of 0.03 mm�. Measurements show a gainof 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is1.85 dB, while the average NF is 2 dB across the whole band. TheLNA achieves a return loss greater than 10 dB across the entireband and a third-order input intercept point �� of 2.85 dBmat the maximum gain frequency.

Index Terms—Common gate (CG), feedback, inductorless,low-noise amplifier (LNA), low power, noise figure (NF), widebandLNA.

I. INTRODUCTION

M ULTIBAND multistandard concepts have gained con-siderable interest in modern wireless communications

systems [1]–[4]. To support a wide set of communication stan-dards and to accommodate different applications in a singledevice, broadband transceivers are essential and inevitably indemand. A wideband RF receiver front-end architecture con-structed by one single path [5] provides lower cost, area, andpower consumption compared to the parallel-path architectures[6], [7]. The single-path wideband concept can also accommo-date emerging standards for cognitive radio applications, re-sulting in efficiency improvement in utilizing scarce spectrumresources.

One of the major challenges in wideband receivers is the de-sign of a wideband low-noise amplifier (LNA) that is sharedamong different standards. As the first block in the receiver

Manuscript received May 17, 2011; revised August 07, 2011; accepted Au-gust 17, 2011.

The authors are with the Department of Electrical and Computer Engi-neering, Texas A&M University, College Station, TX, 77843 USA (e-mail:[email protected]; [email protected]; [email protected]; [email protected]; [email protected].).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TMTT.2011.2169081

chain, such an LNA should achieve good impedance matching,high and flat gain, and low noise figure (NF) across a widefrequency band. In addition, good linearity and low area andpower consumption LNAs are required for high-performanceand low-cost radios.

Recently, many wideband LNAs in CMOS technology havebeen reported, including distributed amplifiers [8] and resis-tive shunt feedback amplifiers [9], [10]. The former offers su-perior bandwidth in terms of high power consumption, largearea, and deterioration of noise performance, which limits itswidespread applications. The latter provides good broadbandmatching, noise, and gain, but it is hampered by greater powerconsumption, which makes them unattractive for low-power ap-plications. Other implementations are inductor-based, such asL-degenerated broadband LNAs [11]. They have good perfor-mance in terms of NF and power consumption. However, theuse of area consuming on-chip bulky inductors makes themunattractive for use in upcoming wireless low-cost transceivers.

One of the wideband LNA topologies that has been widelyinvestigated is the common-gate low-noise amplifier (CGLNA).The CGLNA is attractive compared to other topologies as it fea-tures wideband input impedance matching. Also, it offers goodlinearity, stability, and low power consumption. However, itsmain drawback is the relatively high NF [12]. This is due tothe input matching condition, which restricts a certain value oftransconductance to be used that leads to low gain, and hence,high NF. Noise-reduction techniques are used to overcome thedisadvantage of the CGLNA configuration [12]–[17]. The gainboosting scheme using negative feedback employing capacitivecross-coupling [12], [13], dual negative feedback [16], and pos-itive-negative feedback [17] are applied to break the tradeoff be-tween the input matching condition and the NF, which lead to si-multaneous reduction in noise and power dissipation. However,reducing the NF below 2 dB is still challenging in CGLNAs.

In this paper, a wideband differential CGLNA employingmultiple feedback is proposed. It uses three feedbacks toadd more flexibility in determining the of the impedancematching device. This breaks the lower bound of the noiseperformance and leads to reduction in the NF and increase inthe gain. To the best of the authors’ knowledge, the proposedLNA achieves the lowest NF and highest gain among CGLNAsreported in the literature while consuming low power. It alsoavoids the use of bulky inductors resulting in considerable areaand cost savings. The presented LNA covers frequency bandsfor digital video broadcasting (DVB) at 450–850 MHz, global

0018-9480/$26.00 © 2011 IEEE


2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 1. Conventional differential CGLNA and low-noise feedback techniques.

system for mobile communications (GSM) at 900 MHz, andglobal positioning system (GPS) at 1.2 and 1.5 GHz, providinga practical solution for multistandard applications. This paperis organized as follows. In Section II, existing noise-reductiontechniques for the CGLNA using negative and positive feed-backs are discussed. Section III covers the proposed CGLNA,showing detailed analysis for the major LNA parameters. InSection IV, circuit implementation is presented along with sim-ulation results and measurements. Finally, Section V concludesthis paper.

II. BACKGROUND

Fig. 1(a) shows the differential configuration of the conven-tional CGLNA. In this circuit, the differential voltage gain

and the differential input impedanceare given by

(1)

(2)

where is the transconductance of transistor . Assumingperfect matching condition , the noisefactor is given by

(3)

where is the excess channel thermal noise coefficient, andis the ratio between and the zero-bias drain conduc-

tance, . The last term in (3) represents the noise contribu-tion due to the load, . Due to the power matching constraint,the CGLNA suffers a relatively high NF. Noise-reduction tech-niques are used to improve the NF of the CGLNA. In the Sec-tions II-A and II-B, these techniques are briefly presented.

A. Negative Feedback CGLNA Employing CapacitiveCross-Coupling

The idea to improve the noise performance of the CGLNAis based on introducing a decoupling mechanism between theinput power matching condition and the NF. This is achievedby improving the effective transconductance and enhancing the

gain. The single-ended model of the transconductance boostingstructure is shown in Fig. 1(b). The structure uses an invertinggain that is inserted in the feedback between the gateand source terminals of . The effective is boosted to

with input impedance matching of. This means smaller bias current, less

channel noise from , and consequently smaller noise contri-bution and power consumption. The noise factor is then givenby

(4)

One possible way to implement the inverting gain isto use cross-coupling capacitors , as shown in the differen-tial CGLNA topology in Fig. 1(c) [12]. is approximatelygiven by the capacitors ratio , where

is the gate–source capacitance of . For ,is almost unity, which reduces , , and to the fol-

lowing:

(5)

(6)

(7)

Comparing to the conventional CGLNA, is reduced and theeffective transconductance is increased with reduction in powerconsumption.

B. Positive–Negative Feedback CGLNA

The negative feedback CGLNA reduces the NF by the useof capacitive divider. Meanwhile, its transconductance isrestricted to 10 mS to satisfy the input power matching condi-tion. Thus, this solution suffers from low gain. To alleviate therestriction of low , a positive feedback along with the neg-ative feedback is used in [17]. To increase the gain, the ideais to create a positive current feedback path through , asshown in the single-ended model in Fig. 1(d). This feedbackpath increases the input impedance of the LNA to be equal to

, where is the


SOBHY et al.: 2.8-mW Sub-2-dB NF INDUCTORLESS WIDEBAND CMOS LNA 3

Fig. 2. Schematic of the proposed CGLNA (biasing circuit not shown).

positive feedback gain, which varies from 0 to 1 for stability.In this way, can be chosen arbitrarily to values higher than10 mS without restricting the input matching condition. For ex-ample, if is designed to be 0.5 and , then

mS for the 50- input matching to be satisfied. Thus,the gain increases.

The fully differential positive-negative CGLNA in [17] isshown in Fig. 1(e). Since the positive feedback loop provides adegree of freedom in a way that the impedance matching doesnot fix the bias current, the current will be a design variableto improve the noise performance. Considering the thermalchannel noise, under input matching condition, the noise factoris given by

(8)

For and , , , and are reducedto the following:

(9)

(10)

(11)

The third term in (11) represents the noise due to . The valueof is chosen to be small, which translates to small noise con-tribution. Therefore, the positive–negative feedback CGLNAcan achieve a lower NF than the negative feedback and conven-tional CGLNAs with higher gain. However, power consumptionincreases compared to negative feedback CGLNA.

III. PROPOSED CGLNA

The idea of the proposed CGLNA is based on adding an ad-ditional degree of freedom on the impedance-matching con-dition of the positive–negative feedback CGLNA in Fig. 1(e).

Fig. 3. Simplified single-ended CGLNA model.

Fig. 4. Schematic of the proposed CGLNA showing noise sources.

Fig. 5. Calculated NF versus the optimization parameter � for the proposedCGLNA at � � ��, � � �� , � � ��, and � � ��.

In this way, there will be more flexibility in choosing the op-timum value of the LNA transconductance that achieves min-imum NF. Fig. 2 shows the proposed CGLNA. The biasing in-ductors are replaced by current sources that are capac-itively cross-coupled using [13]. As shown



TABLE ICOMPARISON BETWEEN DIFFERENT CGLNA CONFIGURATIONS TOGETHER WITH THE PROPOSED ONE

in the single-ended model in Fig. 3, the capacitively coupledtransistor creates another positive current feedback path be-side the one created by . Therefore, the output current ofthe LNA becomes the sum of the current provided by the sourceand those injected through and , making the current gainlarger than unity.

A. Input Impedance

The two current (shunt) positive feedback paths have the ef-fect of increasing the CGLNA input impedance. Referring toFig. 2, the input impedance is given by

(12)

where , , and .Thus, the input matching condition is given by

(13)

From (13), two degrees of freedom, and , existthat allow arbitrary choice of achieving high gain and op-timum minimum NF, as will be seen in the noise analysis.

B. Stability

The condition of stability is based on the approach of the re-turn ratio (RR) [15]. This approach is used to study the amplifierstability in the presence of multiple feedback loops and to modelbidirectional paths between input and output. For the proposedCGLNA, the RR has the following expression:

(14)

The proposed CGLNA is stable if and this can beguaranteed by setting with a safe marginto take into account any process variation.

C. Noise Analysis

Fig. 4 shows a simplified model for the noise sources ofthe proposed CGLNA. The circuit noise performance is an-alyzed and its NF is computed assuming that the dominantnoise sources are due to the thermal noise of the transistors

Fig. 6. Schematic of the entire LNA with the output buffer.

TABLE IITRANSISTOR ASPECT RATIOS FOR THE LNA AND BUFFER

Fig. 7. Die photograph of the proposed LNA.

and the load. The coupling capacitors, and , in Fig. 2are replaced with short circuits since they are much largerthan the gate capacitance of the input transistors and ,respectively. In this case, the noise due to the source resistance



Fig. 8. Measured and simulated input matching versus RF input signal fre-quency.

Fig. 9. Measured and simulated voltage gain versus RF input signal frequency.

, the thermal noise due to , , and that due to ,, as shown in Fig. 2, create two equal and opposite noise

currents in the output branches with magnitudes of ,, and , respectively, while the

thermal noise due to , creates two unequal output noisecurrents with differential value of . Theoutput differential current due to each noise source is given by

(15)

Assuming , the noise factor is given by

(16)

Note that the last term accounts for the noise contribution dueto the load . Increasing the value of relative to reducesthe load noise contribution to the overall NF. Under the input

Fig. 10. Measured and simulated NF versus RF input signal frequency.

Fig. 11. Measured �� for the proposed CGLNA.

Fig. 12. Stability factor for the proposed CGLNA.

power matching condition,reduces to

(17)

where and are the optimization parametersused to determine the minimum noise factor for the proposedCGLNA. To find the optimum value of , . As aresult, for large ,

(18)



TABLE IIIPERFORMANCE SUMMARY OF THE PROPOSED BROADBAND LNA AND COMPARISON WITH THE EXISTING WORK

Estimated from data provided in the corresponding papers.Power gain.Active area size.

For small values of , (18) becomes

(19)

Accordingly, the minimum noise factor, , is given by

(20)

The negative sign for the third term in (17) plays an importantrole in reducing the proposed CGLNA noise factor. We can saythat the combination of multiple feedbacks contributes to noisecancellation. As an example, for to ensure sta-bility, is given by

(21)

Graphically, Fig. 5 shows the NF versus sweep of the opti-mization parameter . As depicted, there is an optimum value

to minimize the NF, which is confirmed by the above anal-ysis. In this design example, a minimum NF, , of 1.4dB can be achieved for typical values of short-channel devices.Compared to the conventional CGLNA and other reported feed-back-based CGLNA topologies, the proposed CGLNA achievesthe lowest NF with advantages of removing the bulky induc-tors and arbitrary choice of without restricting the inputmatching condition. Table I summarizes the main properties ofthe different CGLNA configurations together with the proposedone. The last line is showing the percentage of reduction in NFfor each feedback method relative to the conventional CGLNAat , , and . It can be shown thatthe proposed CGLNA can achieve the highest reduction amongother topologies.

IV. CIRCUIT DESIGN AND MEASUREMENT RESULTS

The proposed LNA with a voltage gain of 23 dB, 3-dB band-width of 1.76 GHz, and a minimum NF of 1.85 dB over the bandis implemented. A highly linear voltage buffer is used at theLNA output to drive the 50- load of the measuring equipment.Coupling capacitors are used between the LNA and the buffer

to provide the buffer with separate dc bias. The gain and NF ofthe buffer are predetermined to de-embed their effect from theoverall response to get the LNA response. The total schematicof the LNA with the buffer is shown in Fig. 6. Table II showsthe transistor aspect ratios for the proposed LNA and buffer.In the layout implementation, the transistors are laid out withmaximum number of fingers and close to minimum width perfinger to minimize the effective series gate resistance to reducethe signal loss and improve the NF specially for the input tran-sistor . To reduce the effect of the flicker noise, the lengthsof the transistors are increased. The coupling capacitors, em-ployed in the design, are implemented using a MIMCAP de-vice supported by the IBM 90-nm CMOS process, which has adensity of 5.8 fF m . The biasing resistors are implementedusing poly resistors. Fig. 7 shows a micrograph of the fabricatedCGLNA/buffer with a chip size of 1 mm 1 mm (including thepads). The core LNA area is 0.03 mm

The core LNA consumes 1.4 mA from a 2-V supply whilethe buffer consumes 10 mA. The LNA is encapsulated in amicro leadframe (QFN) open package, where the dc biasesand input RF signal are applied/monitored using an FR-4printed circuit board (PCB). The output signal is monitoredusing a ground–signal–ground–signal–ground (G–S–G–S–G)differential probe. This measurement setup is used to evaluatethe performance of the LNA including the PCB traces andpackaging effect. Baluns are used at the input and output forsingle-ended to differential signal conversion. Figs. 8–10 showthe post layout simulated and the measured input reflectioncoefficient , voltage gain, and NF, respectively. They areplotted versus RF input frequency up to 2 GHz after de-em-bedding the effect of the output buffer. The measured islower than 10 dB from 100 MHz up to 1.8 GHz (Fig. 8).The voltage gain is measured to be 23 dB in the passband withan upper 3-dB frequency of 1.77 GHz (Fig. 9). The measuredminimum NF is 1.85 dB at 0.7 GHz with degraded performanceat the lower and higher frequencies because of the flicker noiseand LNA bandwidth limitation, respectively. Across the entire3-dB bandwidth, the average measured NF is 2 dB. Thesemeasurements show that the proposed LNA achieves an almostconstant NF from 100 MHz up to its upper cutoff frequency.This property does not exist in many reported broadband LNAs,



which achieve a minimum NF at a specific frequency and havea much higher NF across the entire frequency range. Theinput-referred intercept point, , for the proposed widebandCGLNA is measured using a two-tone test for a 300-MHzoperating frequency. The two tones are applied with the sameamplitude and a frequency offset of 10 MHz. An value of

2.85 dBm is obtained, as shown in Fig. 11. As a measure ofthe stability of the proposed CGLNA, Fig. 12 shows a plot forthe stability factor that is calculated based on the -parame-ters LNA buffer through the following expression:

(22)

Table III compares the performance of the proposed CGLNAwith that of the state-of-the-art wideband LNAs around thesame frequency range. The power consumption reported is ofthe core LNA only. As shown in this table, the proposed broad-band LNA with multiple feedback provides the minimum NFamong common-gate (CG) topologies. It also has low powerconsumption and high gain when compared to previouslyreported wideband LNAs.

V. CONCLUSION

An inductorless broadband CGLNA employing noise re-duction has been proposed in this paper. The LNA relies onmultiple feedbacks to fully decouple the tradeoff between noiseand input power matching. The theory shows that the proposedapproach reduces the lower limit of the noise performance ofthe previously reported CGLNAs, allowing for an NF around1.4 dB. Measurements of a fabricated prototype in 90-nmCMOS technology show a voltage gain of 23 dB with a 3-dBbandwidth of 1.77 GHz. A minimum NF of 1.85 dB and anof 2.85 dBm are also measured. The measured NF is lowerthan the best reported NF of CGLNAs. The LNA consumes2.8 mW from a 2-V supply.

REFERENCES

[1] H. Darabi, P. Chang, H. Jensen, A. Zolfaghari, P. Lettieri, J. C. Leete,B. Mohammadi, J. Chiu, Q. Li, S.-L. Chen, Z. Zhou, M. Vadipour, C.Chen, Y. Chang, A. Mirzaei, A. Yazdi, M. Nariman, A. Hadji-Abdol-hamid, E. Chang, B. Zhao, K. Juan, P. Suri, C. Guan, L. Serrano, J.Leung, J. Shin, J. Kim, H. Tran, P. Kilcoyne, H. Vinh, E. Raith, M.Koscal, A. Hukkoo, C. Hayek, V. Rakhshani, C. Wilcoxson, M. Ro-fougaran, and A. Rofougaran, “A quad-band GSM/GPRS/EDGE SoCin 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp.870–882, Apr. 2011.

[2] J.-H. Chang, H. Kim, J.-H. Choi, H. Chung, J. Heo, S. Kang, J.-D.Bae, H. Oh, Y. Kim, T.-W. Kwon, R. Kim, W. Choo, D. Rhee, andB.-H. Park, “A multistandard multiband mobile TV RF SoC in 65 nmCMOS,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2010,pp. 262–263.

[3] Y. Le Guillou, O. Gaborieau, P. Gamand, M. Isberg, P. Jakobsson,L. Jonsson, D. Le Deaut, H. Marie, S. Mattisson, L. Monge, T.Olsson, S. Prouet, and T. Tired, “Highly integrated direct conversionreceiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic rangecontinuous-time �� ADC,” IEEE J. Solid-State Circuits, vol. 40, no.2, pp. 403–411, Feb. 2005.

[4] R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M.Mikhemar, W. Tang, and A. A. Abidi, “An 800-MHz–6 GHz soft-ware-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-StateCircuits, vol. 41, no. 12, pp. 2860–2876, Dec. 2006.

[5] P. Mak and R. Martins, “‘A 0.46 mm 4 dB-NF unified receiverfront-end for fullband mobile TV in 65 nm CMOS,” in IEEE Int.Solid-State Circuits Conf. Tech. Dig., Feb. 2011, pp. 172–174.

[6] H. Kim, S. Kang, J.-H. Chang, J.-H. Choi, H. Chung, J. Heo, J.-D.Bae, W. Choo, and B.-H. Park, “A multi-standard multi-band tuner formobile TV SoC with GSM interoperability,” in IEEE Int. Solid-StateCircuits Conf. Tech. Dig., Feb. 2010, pp. 189–192.

[7] H. Moon, J. Han, S.-I. Choi, D. Keum, and B.-H. Park, “An area-ef-ficient 0.13-�m CMOS multiband WCDMA/HSDPA receiver,” IEEETrans. Microw. Theory Tech., vol. 58, no. 5, pp. 1447–1455, May 2010.

[8] K. Entesari, A. R. Tavakoli, and A. Helmy, “CMOS distributed ampli-fiers with extended flat bandwidth and improved input matching usinggate line with coupled inductors,” IEEE Trans. Microw. Theory Tech.,vol. 57, no. 12, pp. 2862–2871, Dec. 2009.

[9] T. Chang, J. Chen, L. A. Rigge, and J. Lin, “ESD-protected wide-band CMOS LNAs using modified resistive feedback techniques withchip-on-board packaging,” IEEE Trans. Microw. Theory Tech., vol. 56,no. 8, pp. 1817–1826, Aug. 2008.

[10] J.-H. C. Zhan and S. S. Taylor, “A 5 GHz resistive feedback CMOSLNA for low-cost multi-standard applications,” in IEEE Int. Solid-StateCircuits Conf. Tech. Dig., Feb. 2006, pp. 721–730.

[11] H. J. Lee, D. S. Ha, and S. S. Choi, “A 3 to 5 GHz CMOS UWB LNAwith input matching using miller effect,” IEEE J. Solid-State Circuits,vol. 41, no. 2, pp. 731–740, Feb. 2006.

[12] W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. P. de Gyvez, D. J. All-stot, and E. Sanchez-Sinencio, “A capacitor cross-coupled common-gate low-noise amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs,vol. 52, no. 12, pp. 875–879, Dec. 2005.

[13] A. Amer, E. Hegazi, and H. Ragai, “A low-power wideband CMOSLNA for WiMAX,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54,no. 1, pp. 4–8, Jan. 2007.

[14] A. Linscidini, M. Brandolini, and D. Sanzogni, “A 0.13 �m CMOSfront-end for DCS1800/UMTS/802.11b-g with multiband positivefeedback low-noise amplifier,” IEEE J. Solid-State Circuits, vol. 41,no. 4, pp. 981–988, Apr. 2006.

[15] A. Liscidini, G. Martini, D. Mastantuono, and R. Castello, “Analysisand design of configurable LNAs in feedback common-gate topolo-gies,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 8, pp.733–737, Aug. 2008.

[16] K. Jusung, S. Hoyos, and J. Silva-Martinez, “Wideband common-gateCMOS LNA employing dual negative feedback with simultaneousnoise, gain, and bandwidth optimization,” IEEE Trans. Microw.Theory Tech., vol. 58, no. 9, pp. 2340–2351, Sep. 2010.

[17] S. Woo, W. Kim, C. Lee, K. Lim, and J. Laskar, “A 3.6 mW differentialcommon-gate CMOS LNA with positive-negative feedback,” in IEEEInt. Solid-State Circuits Conf. Tech. Dig., Feb. 2009, pp. 218–219.

[18] S. Seong-Sik, I. Dong-Gu, K. Hong-Teuk, and L. Kwyro, “A highlylinear wideband CMOS low-noise amplifier based on current ampli-fication for digital TV tuner applications,” IEEE Microw. WirelessCompon. Lett., vol. 18, no. 2, pp. 118–120, Feb. 2008.

[19] F. Bruccoleri, E. Klumperink, and B. Nauta, “Wide-band CMOSlow noise amplifier exploiting thermal-noise canceling,” IEEE J.Solid-State Circuits, vol. 39, no. 2, pp. 275–282, Feb. 2004.

[20] M. Vidojkovic, M. Sanduleanu, J. van der Tang, P. Baltus, and A. vanRoermund, “A 1.2 V, inductorless, broadband LNA in 90 nm CMOSLP,” in IEEE RFIC Symp. Dig., 2007, pp. 53–56.

[21] M. El-Nozahi, A. A. Helmy, E. Sanchez-Sinencio, and K. Entesari,“An inductor-less noise-cancelling broadband low noise amplifier withcomposite transistor pair in 90 nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1111–1122, May 2011.

[22] W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linearbroadband CMOS LNA employing noise and distortion cancellation,”in Proc. IEEE RF Conf. Dig., 2007, pp. 61–64.

[23] D. Im, I. Nam, J.-Y. Choi, B.-K. Kim, and K. Lee, “A CMOS activefeedback wideband single-to-differential LNA using inductive shunt-peaking for SAW-less SDR receivers,” in IEEE A-SSCC Tech. Dig.,Nov. 2010, pp. 1–4.

[24] H. Wang, L. Zhang, and Z. Yu, “A wideband inductorless LNA withlocal feedback and noise cancelling for low-power low-voltage appli-cations,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp.1993–2005, Aug. 2010.



Ehab Ahmed Sobhy (S’05) received the B.Sc. andM.Sc. degrees in electronics and communicationsengineering from Cairo University, Giza, Egypt,in 2004 and 2007, respectively, and is currentlyworking toward the Ph.D. degree at Texas A&MUniversity, College Station.

In Summer 2003, he was an Intern with theMicrosystems Components and Packaging De-partment, IMEC, Leuven, Belgium, where he wasinvolved with MESFETS. From 2004 to 2007, hewas a Teaching and Research Assistant with the

Electronics and Communications Engineering Department, Cairo University.In 2011, he was with Qualcomm Inc., San Diego, CA, as an RF Design Intern,where he designed wideband LNAs. He is currently with the Analog andMixed-Signal Center (AMSC), Texas A&M University. His research interestsinclude RF and analog circuits.

Ahmed A. Helmy (S’09) was born in Cairo, Egypt,in 1983. He received the B.Sc. degree (with honors)and M.Sc. degree in electronics engineering fromCairo University, Giza, Egypt, in 2005 and 2008,respectively, and is currently working toward thePh.D. degree in electrical and computer engineeringat Texas A&M University, College Station.

From 2005 to 2008, he was a Research Assistantwith the Yousef Jameel Science and TechnologyResearch Center, The American University, Cairo,Egypt. From 2005 to 2008, he was a Teaching

Assistant with the Electronics and Communications Engineering Department,Cairo University. In Summer 2011, he was an RF Design Intern with SamsungTelecommunications America, Dallas, TX, where he was involved with mil-limeter-wave wireless transceivers. His research interests include RF integratedcircuit (RFIC) design, CMOS sensors, and microelectromechanical systems(MEMS).

Sebastian Hoyos (S’01–M’04) received the B.S.degree in electrical engineering from the PontificiaUniversidad Javeriana (PUJ), Bogota, Colombia,in 2000, and the M.S. and Ph.D. degrees in elec-trical engineering from the University of Delaware,Newark DE, in 2002 and 2004, respectively.

From 1999 to 2000, he was with Lucent Tech-nologies Inc., during which time he worked for theAndean Region in South America. Simultaneously,he was a Lecturer with PUJ University, where helectured on microelectronics and control theory.

During his masters and doctoral studies, he worked under PMC-Sierra Inc., theDelaware Research Partnership Program, and the Army Research Laboratory(ARL) Collaborative Technology Alliance (CTA) in communications andnetworks. In Fall 2004, he joined the Department of Electrical Engineeringand Computer Sciences, University of California at Berkeley, where he wasa Postdoctoral Researcher with the Berkeley Wireless Research Center. Heis currently an Assistant Professor with the Department of Electrical andComputer Engineering, Texas A&M University, College Station. His researchinterests include communication systems, wireless communications, robustsignal processing, and mixed-signal high-performance and low-power systemsand circuit design.

Kamran Entesari (S’03–M’05) received the B.S.degree in electrical engineering from Sharif Uni-versity of Technology, Tehran, Iran, in 1995, theM.S. degree in electrical engineering from TehranPolytechnic University, Tehran, Iran, in 1999, andthe Ph.D. degree from The University of Michiganat Ann Arbor, in 2005.

In 2006, he joined the Department of Electricaland Computer Engineering, Texas A&M University,College Station, where he is currently an AssistantProfessor. His research interests include design of

RF/microwave/millimeter-wave integrated circuits and systems, RF MEMS,related front-end analog electronic circuits, chemical/biochemical sensors, andmedical electronics.

Dr. Entesari was the corecipient of the 2009 Semiconductor Research Corpo-ration (SRC) Design Contest Second Project Award for his work on dual-bandmillimeter-wave receivers on silicon and the 2011 Faculty Early Career De-velopment (CAREER) Award sponsored by the National Science Foundation(NSF).

Edgar Sánchez-Sinencio (F’92–LF’09) was bornin Mexico City, Mexico. He received the degreein communications and electronic engineering(Professional degree) from the National PolytechnicInstitute of Mexico, Mexico City, in 1966, theM.S.E.E. degree from Stanford University, Stanford,CA, in 1970, and the Ph.D. degree from the Univer-sity of Illinois at Champaign-Urbana, in 1973.

He is currently the TI J. Kilby Chair Professorand Director of the Analog and Mixed-SignalCenter, Texas A&M University, College Station.

His research has more than 3000 citations according to the Thomson ReutersScientific Citation Index. He has graduated 46 M.Sc. and 38 Ph.D. students. Hehas coauthored six books on different topics, such as RF circuits, low-voltagelow-power analog circuits, and neural networks. His current interests are inthe area of power management, ultra-low power analog circuits, and medicalelectronics circuit design.

Dr. Sánchez-Sinencio was the editor-in-chief of the IEEE TRANSACTIONS

ON CIRCUITS AND SYSTEMS II—PART II: ANALOG AND DIGITAL SIGNAL

PROFESSING and a former IEEE Circuits and Systems (CAS) vice presi-dent-publications. In November 1995, he was awarded a Honoris CausaDoctorate by the National Institute for Astrophysics, Optics and Electronics,Puebla, Mexico. This degree was the first honorary degree awarded formicroelectronic circuit-design contributions. From 2000 to 2002, he was theIEEE Circuits and Systems Society’s representative to the IEEE Solid-StateCircuits Society. He was a member of the IEEE Solid-State Circuits SocietyFellow Award Committee from 2002 to 2004. He was a corecipient of the1995 Guillemin–Cauer Award for his work on cellular networks and the 1997Darlington Award for his work on high-frequency filters. He was the recipientof the 1999 IEEE Circuits and Systems Society Golden Jubilee Medal and theIEEE Circuits and Systems Society 2008 Technical Achievement Award. Hehas received Texas Senate Proclamation #373 for Outstanding Accomplish-ments in 1996.

a 2.8 mw sub 2 db noise figure inductorless

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