a 176-stacked 512gb 3b/cell 3d nand flash with 10.8gb/mm
TRANSCRIPT
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 1 of 26
A 176-Stacked 512Gb 3b/Cell 3D NAND Flash with 10.8Gb/mm2 Density Using
Peripheral Circuit under Cell ArrayJae-Woo Park, Doogon Kim, Sunghwa Ok, Jaebeom Park, Taeheui Kwon, Hyunsoo Lee,
Sungmook Lim, Sun-Young Jung, Hyeongjin Choi, Taikyu Kang, Gwan Park, Chul-Woo Yang, Jeong-Gil Choi, Gwihan Ko, Jaehyeon Shin, Ingon Yang, Junghoon Nam, Hyeokchan Sohn,
Seok-In Hong, Yohan Jeong, Sung-Wook Choi, Changwoon Choi, Hyun-Soo Shin, JunYoun Lim, Dongkyu Youn, Sanghyuk Nam, Juyeab Lee, Myungkyu Ahn, Hoseok Lee, Seungpil Lee, Jongmin Park, Kichang Gwon, Woopyo Jeong, Jungdal Choi, Jinkook Kim, Kyo-Won Jin
SK Hynix, Icheon, Korea
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 2 of 26
Self IntroductionI received the B.S degree in electronic engineering from Korea University, Seoul, Korea, in 2000, and the M.S degree in electrical engineering from Seoul National University, Seoul, Korea, in 2002.
Since 2014, I have been involved in the development of NAND flash memory in the Flash Design Team, SK-Hynix semiconductor where I worked on circuit and logic designing of NAND flash memories.
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 3 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive WL Overdrive(OVD) Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 4 of 26
Peripheral circuit Under Cell Array Area
Reduced PUC area due to an increase of WL StacksReduced page buffer area and enhanced pump drivability & efficiency w/o
increasing pump size
Cel
l Are
a [a
.u.]
96 stack
54% reduced
176 stack
Cell Array
Cell Array
Cell Array
XDEC
PAD/IO
XDEC
XDEC
XDEC
Peripheral Circuit
Peripheral CircuitPeri. Circuit outside of Cell Array
Cell Array
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 5 of 26
Word-Line RC
Increased load due to a higher number of WL stacks High WL-Channel capacitance due to an increase number of strings Variation in RC delay between WLs due to a non-uniformity in plug
critical dimensionOvercame these issues by using Center XDEC, Unselected string boosting,
and Adaptive WL Overdrive scheme
96-stack 176-stack 4-string 8-string
x2x1.84
Previous work This work
x3.7RC
RC
RC
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 6 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive WL Overdrive(OVD) Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 7 of 26
CacheCache
12-Stage Page Buffer
96-stacked WLs
BL c
onne
ctor
Page buffer array
Cache array
PBPB
BL con.
PBPB
BL con.
PBPB
BL con.
PBPB
BL con.
PBPB
BL con.
PBPB
BL con.
PBPB
BL con.
PBPB
BL con.
176-stacked WLsPage buffer array
PBPB
BL con.
PBPB
BL con.
Cache
PBPB
BL con.
PBPB
BL con.
Cache
PBPB
BL con.
PBPB
BL con.
Cache
PBUS
PB stages are reduced from 16 to 12, BL connectors for the connection between BL and page buffer are changed from 8 to 4
16 stages& 8 BL connecters
12 stages&4 BL connectors
56% reduced
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 8 of 26
12-Stage Page Buffer
25% area reduction by changing PB stages from 16 to 12 20% area reduction by changing BL connectors from 8 to 4 The overall reduction of the PB height, 56%, could be achieved
by reducing PB unit size
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 9 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive WL Overdrive(OVD) Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 10 of 26
Variable Stage and Frequency-Controlled Charge Pump with a Boosted Local Pump
Unit Pump
Unit Pump
VDD
Unit Pump
CKSTGN
CKSTGN-1
CKSTGK
RX
R1
STGN_LP STGN-1_LP
CBYPASS
VREF
L/S L/S
VDD
Local Pump
VDD
STGK_LP L/S
VDD
VPUMP
Pump Reg.
PUMP StageSTAGE
CONTROL CIRCUIT
STGN
PUMP_EN
STAGE_DN
STAGE_UP STGN-1
STGK
STGN_LP
STGN-1_LP
STGK_LP
STAGE_CON. LOGIC
VARIABLE FREQ. OSC.
Local pump boosting charge pumpVRE
VrefT
FLIP FLOP CKSTGN
STGN-1
STGK
Osc. EN
Osc. EN
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 11 of 26
Local Pump Boosting Charge Pump
Unit Pump
Unit Pump
VDD
Unit Pump
STGN_LP STGN-1_LPL/S L/S
VDD
Local Pump
VDD
STGK_LP L/S
VDD
VPUMP
IPUMP
CKSTGN
CKSTGN-1
CKSTGKCOMP
Conv. variable stage charge pump
Diode connected NMOS limits the first voltage(VS) of Pump core
Local pump boosting charge pump
VGS=VDD-VS
VS,K
Low VGS High Rdson
VS,N-1VS,N VS,KVS,N-1VS,N
VPP
VGS=VPP-VSVS ≈ VDD
Local pump made higher voltage(VPP) than VDD
High VGS Low Rdson
VS ≈ VDD-Vth
STGN
STGN-1
STGK
VDDVS=VDD-VTH-Rdson*IPUMP
VS=2VDD-VTH-Rdson*IPUMP
VS,K
VS,N-1
VS,N
STGN
STGN-1
STGK
VDDVS=VDD-Rdson*IPUMP
VS=2VDD-Rdson*IPUMPVS,K
VS,N-1
VS,N
Unit Pump
Unit Pump
VDD
Unit Pump
STGN
VDD VDD
STGN-1 STGK
VPUMP
IPUMP
CKSTGN
CKSTGN-1
CKSTGKCOMP
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 12 of 26
Variable Stage and Freq. Charge PumpConventional scheme- Variable stage & fixed frequency
This work- Variable stage & variable frequency
Driva
bili
ty(m
A)
VPUMP(V)
K stage
N-1 stage
N stage
Effici
ency
(%)
VPUMP(V)
N stage
N-1 stage
K stage
Pump stage & frequency are selected based on the pump level by considering pump drivability and efficiency
STGK < STGN-1 < STGNfCKK > fCKN-1 > fCKN
STGN
STGN-1
STGK
CK
CKK CKN-1 CKN
Freq.
Drivability(mA)
Efficiency(%)
fCKN fCKkfCKN-1
Effici
ency
(%)
VPUMP(V)
N stage
N-1 stage
K stage
Driva
bili
ty(m
A)
VPUMP(V)
K stage
N-1 stage
N stageLow stage& High Freq.
High stage& Low Freq.
Drivability ↑Efficiency ↑
Pump stage ↑, Frequency ↑ Drivability ↑, Efficiency ↓
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 13 of 26
Comparison to PUMP Performance
ICCPump Drivability @ equal loading
Proposed PumpConventional Pump
Normalized Time* S. K. Won et al., ASSCC, Apr. 2011, pp. 169-172
Normalized Time
Nor
mal
ized
Vol
tage
Nor
mal
ized
Cur
rent
WL RISING TIMEAverage ICC
RISING Time Reduction
improved current driving
Normalized Factor – Reference conventional pump(100%)
Pump speed has improved about 46% without additional power
0.0%
20.0%
40.0%
60.0%
80.0%
100.0%
120.0%
Conv. Local pump Local pump +Var. CLK
13% Faster
33% Faster
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 14 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive WL Overdrive(OVD) Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 15 of 26
Center X-Decoder
LWL (8 kB)LWL (8 kB)
BLKWL_L BLKWL_R
GWLCenter X-Decoder
LWL loading (16 kB)
BLKWL
GWL
Edge X-Decoder
Plane0
Plane1
Plane2
Plane3
Plane0
Plane1
Plane2
Plane3
WL RC could be reduced to ¼ by using the center X decoder scheme
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 16 of 26
Half-Plane Activation
LWL (8 kB)LWL (8 kB)
BLKWL_L BLKWL_R
GWL
1st 4kB 2nd 4kB 3rd 4kB 4th 4kB
LWL (8 kB)LWL (8 kB)
BLKWL_L BLKWL_RGWL
*Page size 16kByte
OFF ON
Select BLKWL_L Select BLKWL_R
OFFON
BLKWL_L/R are selectively enabled according to the selected 4kB range By applying Center XDEC and Half plane activation to 4kB Read, random
read performance is improved by 15% compared to edge XDEC
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 17 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive WL Overdrive(OVD) Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 18 of 26
Unselected String Boosting Scheme
The number of string increased WL capacitance ↑
− Ipump ↑ , ICC ↑ Number of read operation
− Read disturb ↑
Unselected string boosting scheme was used to reduce ICC and read disturb
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 19 of 26
Unselected String Boosting Scheme
WLs
Volta
ge
time
Channel potentialVo
ltage
time
WLs
Volta
ge
time
Channel potentialVolta
ge
time
DSL
SSL
Sel.WL
BL
SL Cha
nnel
pot
entia
l gro
und
or b
oost
ed le
vel
Unsel. WL(~6V)
Unsel. WL(~6V)
Sel.String
Unsel.String
W/O Channel Boosting W/ Channel Boosting
Reduced the WL Cap. and the potential difference between WL-CH by unsel. string channel boosting Reduced the charge needed to be filled Improved read disturb by reducing vertical e-field
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 20 of 26
Unselected String Boosting SchemeConventional scheme This work
Unselected string boosting scheme is performed to improve ICC by 7% and read disturb by 15%
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 21 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive WL Overdrive(OVD) Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 22 of 26
Adaptive WL Overdrive
Conventional Scheme
In the conventional scheme, finding optimized WL overdrive level and time is impossible
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 23 of 26
Adaptive WL Overdrive
WL RC
WL
Stac
k
ΔV1
t1
Volta
ge
Time
ΔV4t4
Volta
ge
Timetarget
Tset w/o OVD
Tset w/o OVD
This work
Minimized the difference of the settling time for each group by optimizing overdrive level and time considering WL RC variation
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 24 of 26
Outline Introduction PUC Area Reduction Techniques 12-Stage Page Buffer Variable Stage and Frequency-Controlled Charge Pump with a Boosted
Local Pump
Big and Variable Word-Line RC Overcome Techniques Center X-DEC and Half-Plane Activation Unselected String Boosting Scheme Adaptive OVD Scheme
Conclusion
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 25 of 26
Chip Architecture
Row
Dec
oder
Peripheral Circuits & PADsCell Array
(128Gb/Plane)WL Direction
BL Direction
Cell Array(128Gb/Plane)
Cell Array
Cell Array
30.1 A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture© 2021 IEEE International Solid-State Circuits Conference 26 of 26
Key Parameters
ISSCC2019 This WorkTechnology 128-WL 176-WL
Capacity (Gb) 512 512# bit/cell 3 3
# of planes 4 4Program Throughput (MB/s) 132 168
tR (µs) 56 50I/O interface (Gb/s) 1.066 1.6
Bit density (Gb/mm2) 7.8 10.8