A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz

Using Constant-Activity Element Switching Chengyu Huang, Yushen Fu, Zekun Yang, Yang Liu, Nan Sun, Xueqing Li, and Huazhong Yang

BNRist/ICFC, Electronic Engineering Department, Tsinghua University, Beijing, China Contact Email: xueqingli@tsinghua.edu.cn, yanghz@tsinghua.edu.cn

Abstract—This paper reports the first silicon-verified current-steering DAC using enhanced constant-switching-activity data-weighted-averaging (CSA-DWA). It achieves data-independent constant switching activities for all the input codes by exploiting redundant switching elements. In addition, a power supply network optimization is presented to meet the increased timing-match requirement due to the adopted extra switching elements. Without calibration, the fabricated 16-bit 4GS/s DAC in 65nm CMOS achieves >70dBc spurious-free dynamic range (SFDR) and <-80dBc third-order intermodulation distortion (IM3) up to 1GHz, showing 4-15dB SFDR and 5-14dB IM3 improvement across the Nyquist band.

Index Terms—digital-to-analog converter (DAC), data-weighted-averaging (DWA), IR-drop, switching distortion.

I. INTRODUCTION High linearity Nyquist DAC has been a critical component

in the wideband transmitter, as a DAC with higher SFDR and IM3 supports more channels and more complex modulation schemes, reducing the complexity for the overall system [12]. At low frequencies, the static mismatch is the bottleneck of DAC linearity; at high frequencies, the dynamic mismatch, including timing error and inter-symbol interference (ISI), dominates the overall performance [1].

Previous works have proposed post-fab calibration, post-layout sequence adjustment, digital pre-distortion (DPD), dynamic element matching (DEM), etc., to mitigate static mismatch [2-5,15]. Among these techniques, DEM adopts random element selection, and can turn the mismatch into noise. However, in conventional DEM, the element transition rate is signal-dependent, which causes signal-dependent ISI error and linearity degradation at high frequencies [8,14].

To mitigate the ISI induced distortion, one common technique is using return-to-zero (RZ) architecture [6]. By adopting RZ, the elements have uniform transition behavior for different switching operations. Thus, the element transition is independent of the input signal even though the element transition rate is dependent on the input signal. Other techniques such as differential-quad switching (DQS) [9] and switching-glitch compensation (SGC) [10] can also achieve uniform transition behavior. But these techniques are not able to handle the nonlinearity due to static mismatches.

In recent years, Σ-Δ modulation has been applied to keep a constant average transition rate, which is also capable of mitigating the ISI induced distortion [11]. The Σ-Δ modulator can also shape the static mismatch, suppressing the static mismatch induced nonlinearity. But the Σ-Δ based decoder is challenging to implement at a high sampling rate for wideband applications. Reference [13] proposed a constant-switching-activity data-weighted-averaging (CSA-DWA) decoder,

which achieve effective ISI error suppression and static mismatch shaping together in a high sampling rate.

This paper reports a 16-bit 4GS/s current-steering DAC in 65nm CMOS, which achieves >70dBc SFDR up to 1GHz. The technical contributions include:

1) The first CSA-DWA silicon implementation with enhanced suppression of the nonlinear distortions, showing 4-15dB SFDR improvement across the Nyquist band.

2) A proposed power supply network for the latch array that achieves reduced IR-drop mismatch, which mitigates the timing errors caused by the extra current source branches in the CSA-DWA DAC.

This paper is organized as follows: Section II introduces CSA-DWA with proposed enhancement. Section III presents the proposed power supply network. Section IV shows the chip measurement results. Section V concludes this paper.

II. ENHANCED CSA-DWA DECODER This section first provides a brief overview of the initial

CSA-DWA concept in [13], which eliminates the signal-dependent transition rate while shaping the static mismatch. Then we analyze the truncation distortion in general CSA-DWA and propose an enhanced design to solve the problem.

A. General CSA-DWA Decoder The CSA-DWA outperforms the conventional data-

weighted-averaging (DWA) in the capability of enabling constant switching activities. It is achieved by shifting the head index of the selected segment in a conventional DWA scheme, as illustrated in Fig. 1. This is explained below.

In a conventional DWA DAC without redundant elements, the quantity of selected elements in ith cycle, Ni, is equal to the input digital code Di. Therefore, from (i-1)th to ith cycle, the total number of transition Ci is:

𝐶! = 𝐷!"# +𝐷! (1) It could be observed that Ci only depends on the input

codes, and causes a signal-dependent transition rate. With redundant elements added, to achieve the same differential output, Ni is equal to Di + R / 2, in which R represents the total number of redundant elements. After shifting the head index, the total number of transition Ci could be rewritten as:

𝐶! =𝐷!"# +𝐷! + 𝑅 −2𝑂𝑣𝑒𝑟𝑙𝑎𝑝!"#→! (2)

where Overlapi-1 → i represents the overlapped elements between two adjacent cycles, as illustrated in Fig. 1.

From (2), if Overlapi-1→i is dynamically adjusted to be Di + Di-1, the total number of transition Ci becomes constant and equal to R. This is true only for 0 ≤ Overlapi-1→i ≤ min(Di-1 +

R / 2, Di + R / 2). If R ≥ M, in which M is the total number of designed levels, this condition can always be satisfied, as illustrated in Fig. 2.

B. Enhancement on Truncation Induced Distortion It could be derived from (2) that the shift amount in ith

period Si is equal to (Di-1 −Di + 2C) 2⁄ , in which C is the constant transition rate we set. The divide-by-two operation will generate truncation error for odd number, causing a harmonic in the spectrum of switching times, which induces signal-dependent switching activities. This effect is significant especially for a small MSB segment, as shown in Fig. 3(a).

To eliminate the truncation induced distortion, we replace C with CSI in (1) by adding one random bit to C for shift amount calculation. As Fig. 3(a) illustrate, after randomizing, the spectrum of switching times becomes tone-free, making it independent from the input signal. This randomization also has a suppression on element static mismatch, which further improves the overall dynamic range. Fig. 3(b) shows the CSA-DWA decoder block diagram after this enhancement.

III. LOW TIMING ERROR LATCH ARRAY Due to extra switching elements to synchronize in CSA-

DWA, the timing mismatch control of the driver latches becomes more challenging. For latch timing synchronization, this section presents the proposed power-supply network technique in detail.

Both random and gradient mismatches impact the timing error. For the gradient error, it is dominated by IR-drop on the supply route. The IR-drop in a 1-D latch array can be modeled as a resistor network shown in Fig 4. Generally, to reduce the IR-drop induced timing error, it is an effective strategy that designing RMETAL and RVIA as small as possible. However, it requires large area for power supply route. This problem

Fig. 1 Decoding strategy comparison between (a) Conventional DWA and (b) CSA-DWA.

Fig. 2 Overlapi-1→i and its upbound with R = C = M.

(i-1)th Cycle

ith Cycle

(i+1)th Cycle

Ni-1 + Ni times switching

Ni + Ni+1 times switching

Ni-1 + Ni – 2 * Overlapi-1->itimes switching

Ni+1 selected

Ni-1 – Overlapi-1->ielements become

unselected Ni – Overlapi-1->ielements become

selected

M-2 M-1 0 1

Element Index Increase

Ni-1 selected

Ni selected

Ni – Overlapi->i+1elements become

unselected

Ni+1 – Overlapi->i+1elements become

selected

Overlapi-1->ielements keep

selected

Overlapi->i+1elements keep

selected

Ni + Ni+1 – 2 * Overlapi->i+1times switching

Ni+1 selected

Ni-1 elements become unselected

Ni elements become selected

Ni elements become unselected

Ni+1 elements become selected

M-2 M-1 0 1

Element Index Increase

Ni-1 selected

Ni selected

(a) (b)

M-1

0M-1

0

Fig. 3 Truncation error and enhancement on it: (a) Power density spectrum of switching times with different truncation strategies (b) Enhanced CSA-DWA decoder block diagram.

Fig. 4 Modeled power supply network for IR-drop analysis.

Fig. 5 Proposed power supply network and simulation: (a) Proposed low gradient error power network (b) Simulation result comparison before and after optimization (c) Size optimization between random deviation and IR-drop-caused skew.

6dBc

Random overlapi->i+1truncation

Normalized Frequency (f/fs)

Non-random

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ty s

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hing

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5-bit ThermalDecoder

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Latches

{0, Di} <4:0>

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Di-1

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+

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÷2

CSI

……To pad

To latch KTo latch 1To latch 0

RMETAL RMETAL RMETAL RMETAL RMETAL

RVIA,1RVIA,0 RVIA,K

……

Latch Size

Timing skew (fs) (random&gradient)

SFDR (dBc)@ 3GS/s, 317MHz

x1

375

78.1

x2

183

83.2

x4

195

81.9

x8

358

67.5

0 20 40 60 80 1000

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Latch index

Before OptimizationAfter Optimization

Simulation Results

(a) (b)

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1

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2 3 50 51 52 99 100 101

GND

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GND

VDD

GND

VDD

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Random Deviation

Latch Size / Unit Latch Cell

Reduced IR-drop induced skew

Reduced Total Skew

Tim

ing

Skew

x1 x2 x4

becomes challenging in wideband DAC which is timing-mismatch sensitive. Here we adopt another design strategy to further reduce the IR-drop-mismatch induced timing errors. By making the via parasitic resistor RVIA,i vary from the index, we can achieve well matched supply resistance for each latch.

Fig. 5(a) depicts our proposed power supply network. It applies different quantity of vias to tune the RVIA,i mentioned above. After this optimization, though the absolute supply resistance goes up, the effective resistance exhibiting over 5.3x mismatch reduction, as shown in Fig 5(b).

To further reduce timing mismatch, we adopt a size optimization between random and gradient mismatches by evaluating the total timing skew in different latch scales. As illustrated in Fig. 5(c), the post-layout timing skew Monto Carlo simulation results exhibit a 192fs average timing skew reduction.

IV. MEASUREMENT RESULT To verify the proposed CSA-DWA decoder with enhanced

truncation distortion suppression and the proposed power-supply layout optimization, an experimental 16bit 4.0-GS/s current-steering Nyquist DAC was implemented and fabricated in a 65nm 1.0V/2.5V dual-supply CMOS technology, as shown in Fig. 6. The current source array is segmented as 5MSB + 4ULSB + 7LSB. The MSB and ULSB segments are unary, while LSB segment utilizes binary weights. Both MSB and ULSB segments adopt a CSA-DWA decoder to ensure full input-signal independency in the switching activities. Therefore, a total of 48 (=32+16) extra current sources were used for MSB and ULSB. In the decoder, the thermometer mode and Rotation-Based DEM mode [15] are alternative for testing. The LSB segment adopts a delay equalizer for data synchronizing between segments, and is not implemented with CSA-DWA.

Fig. 7 shows the chip micrograph and the layout floorplan. The total active area is 0.85mm2 including the retiming latches and clock distribution. An on-chip high-speed cache is built to provide 16-bit input digital data stream to the DAC core. At a 4GS/s sample rate, the DAC consumes 849mW power excluding the on-chip cache. The DAC delivers 16mA full-scale output current to an external 50Ω differential resistor. An external balun is used to couple the DAC output to a spectrum analyzer.

Fig. 8(a) shows the two-tone test spectra. The IM3 is measured to be 75dBc at 1.7GHz with CSA-DWA, bringing 5.7dB improved over a conventional DEM . A 5-14dB IM3 improvement is achieved, as shown from the measurement result summary in Fig. 8(b). Furthermore, thanks to lower randomization, the NSD shows 3-6dB reduction compared with conventional DEM.

Fig. 9(a) shows the SFDR measurement snapshots at 1.71GHz under different modes. At this frequency, the performance is severely limited by the dynamic distortion during the signal-dependent transition. In the DEM mode, the 3rd harmonic caused by the signal dependency transition dominates the performance. After turning on CSA-DWA, the 3rd harmonic is suppressed, the SFDR is improved to 70.8dB with 11.4dB improvement over the conventional DEM. For different input frequencies, the SFDR improvement ranges between ~4dB to ~15dB. Fig. 9(b) summarizes the SFDR performance compared with the state-of-the-art in high-speed

Fig. 6 Proposed DAC architecture.

Fig. 7 Prototype chip micrograph.

Delay Equalizer

CSA-DWA Decoder(Optional

Therm./Dem)

TestSignalCache 4ULSB

5MSB

7LSB

Ret

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ches

31

63

7

101

101

CLK Gen. SPI Power SupplyNetwork

Digital ControlClock DAC OUT

2.9m

m

Technology 65nm CMOS

Resolution 16 bits

Sample Rate 4 GS/s

Supply 1.0V&2.5V

Full Scale 16 mA

Active Area 0.85 mm2

Total Area 4.9 mm2

Power 849 mW

SFDR@1.7GHz 70.8dB

BW@SFDR>70dB 1.1GHz

1.7mm

Current SourcesLatches

CSA-DWADecoder

On-ChipCache

Clk

-Gen

Fig. 8 Two-tone test results: (a) IM3 and NSD measurement snapshot in different mode (b) Summary of IM3 and NSD performance.

Fig. 9 Single tone test results: (a) SFDR measurement snapshot in different modes (b) SFDR summary and comparison with state-of-the-art.

Improve5.7dB

Fs = 4GHzFsig = 1708MHzWith DEM

Fs = 4GHzFsig = 1708MHzWith CSA-DWA

(a)

(b)

-95-90-85-80-75-70-65-55

-132-135-138-141-144-147-150-152

0 200 400 600 800 1000 1200 1400 1600 1800 2000Frequency (MHz)

IM3

(dB

c)

NSD

(dB

m/H

z)

IM3 CSA-DWAIM3 DEM

NSD CSA-DWANSD DEM

Fs = 4GHzFsig = 1708MHzWith DEM

Fs = 4GHzFsig = 1708MHzWith CSA-DWA

Improve11.4dB

(a)

(b)

10095908580757065

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Frequency (MHz)

SFD

R (d

Bc)

605550

Huang, VLSI 2020, 28nmLin, ISSCC 2018, 16nmSu, ISSCC 2018, 65nm, single-rateErdman, ISSCC 2017, 16nmRavinuthula, VLSI 2016, 40nm

This work, CSA-DWA, 65nmThis work, DEM, 65nm

Solid: w/o calibrationDashed: with calibration

DACs. The measured SFDR vs the input signal frequency at 4GS/s shows >70dB up to 1066MHz and >65dB across the whole Nyquist band.

V. CONCLUSION In this paper, a 16-bit 4GS/s current-steering CMOS DAC

has been presented achieving >70dBc SFDR and <-80dBc IM3 up to 1GHz. An enhanced constant-switching-activity digital-weight-average (CSA-DWA) decoder and low IR-drop mismatch power supply network are discussed and verified. By adopting the decoder, the measurement result shows a 3-6dB NSD and 5-14dB IM3 improvement across the whole Nyquist band. The measured ~4dB to ~15dB SFDR improvement verifies the effectiveness of CSA-DWA decoder in suppressing signal-dependent transition.

ACKNOWLEDGMENT This work is supported in part by NSFC under grant

61934009.

REFERENCES [1] S. M. McDonnell et al “Compensation and Calibration Techniques for

Current-Steering DACs,” IEEE Circuits and Systems Magazine, vol. 17, no. 2, pp. 4–26, 2017.

[2] C. Lin et al., “A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS,” in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 360–362.

[3] S. Su and M. S. Chen, “A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands,” in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 362–364.

[4] C. Erdmann et al., “16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz,” in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 280–281.

[5] G. A. M. Van Der Plas et al “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1708–1718, 1999.

[6] W. Lin, H. Huang, and T. Kuo, “A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique,” IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 708–717, Mar. 2014.

[7] V. Ravinuthula et al., “A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz,” in 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, pp. 1–2.

[8] L. Lai, X. Li, Y. Fu, Y. Liu, and H. Yang, “Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 68–81, Jan. 2019.

[9] S. Park, G. Kim, S.-C. Park, and W. Kim, “A digital-to-analog converter based on differential-quad switching,” IEEE Journal of Solid-State Circuits, vol. 37, no. 10, pp. 1335–1338, Oct. 2002.

[10] H.-Y. Huang et al , “A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < −77dBc IM3,” in 2020 IEEE Symposium on VLSI Circuits, 2020, pp. 1–2.

[11] K. L. Chan, J. Zhu, and I. Galton, “Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2067–2078, Sep. 2008.

[12] G. Engel, D. E. Fague, and A. Toledano, “RF digital-to-analog converters enable direct synthesis of communications signals,” IEEE Communications Magazine, vol. 50, no. 10, pp. 108–116, Oct. 2012.

[13] L. Lai, X. Li, and H. Yang, “Redundancy-bandwidth scalable techniques for signal-independent element transition rates in high-speed current-steering DACs,” International Journal of Circuit Theory and Applications, vol. 46, no. 5, pp. 1006–1027, 2018.

[14] L. Risbo et al, “Digital approaches to ISI-mitigation in high-resolution oversampled multi-level D/A converters,” IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2892–2903, 2011.

[15] W.-T. Lin and T.-H. Kuo, “A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection,” IEEE Journal of Solid-State Circuits, vol. 47, no. 2, pp. 444–453, 2012.

TABLE I. Comparison with published high-speed DACs

This work ISSCC 2018 VLSI 2016 VLSI 2020 ISSCC 2018 ISSCC 2017

[3] [7] [10] [2] [4]

Technology (nm) 65 65 40 28 16 16

Resolution (bit) 16 16 14 14 16 14

Sample Rate (GS/s) 4 12/9 8.9 10 6 6.8

Supply (V) 1.0&2.5 1.0&2.5 1.0&3.6 1.1 1.0&3.0 -

Full Scale(mA) 16 16 40 16 40 20

Active Area (mm2) 0.85 1.17 - 0.1 0.52 0.86

Power (mW) 849 1760/1200 1200 177 350 330

Calibration No Yes No No Yes No

Calibration-Free SFDR@1GHz(dBc) 71 55(1)/57(1) 59 72 67(2) 74

Calibration-Free BW@SFDR>70dBc (GHz) 1.1 -(1) - 2.5 0.7(2) 0.5

SFDR@1GHz (dBc) 71 68/71 59 72 79 74

BW@SFDR>70dBc (GHz) 1.1 0.6/1.2 - 2.5 2.2 0.5

IM3@1GHz(dBc) -80 -72/-77 -76 -82 -92 -84

BW@IM3<-75dBc (GHz) 1.7 0.3/1.2 1.1 4.8 4.4 2.6

(1) Data available only with both DPD and DWA disabled.

(2) Data available only with both calibration and DEM disabled.