a 14-b 100-ms/s pipelined adc with a merged sha and first mdac byung-geun lee, member, ieee,...

A 14-b 100-MS/s Pipelined ADC With aMerged SHA and First MDAC

Byung-Geun Lee, Member, IEEE, Byung-Moo Min, Senior Member, IEEE,

Gabriele Manganaro, Senior Member, IEEE, and Jonathan W. Valvano, Member, IEEE

Adviser : Hwi-Ming Wang Student : Wei-Guo Zhang

Date : 2009/10/28

Outline

Abstract Introduction Low-Power Techniques In Pipeline ADC Proposed Opamp And Capacitor Sharing Technique Circuit Implementation Measurement Results Conclusion References

EE,STUT2Wei-guo zhang 2009/10/28

Abstract

This paper presents low-power 14-bit 100-MS/s ADC Further reduction of power and area is achieved by completel

y merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique

The ADC, implemented in a 0.18-um dual-gate-oxide(DGO)

CMOS technology 72.4-dB SNDR, 88.5-dB SFDR 11.7 effective number of bits at full sampling rate46-MHz input While consuming 230-mW from a 3-V supply


Introduction

Mobile wireless communication systems are major applications of recent analog-to-digital converters (ADCs). In these applications, the specifications of the ADC vary significantly across different receiver architectures

IF-sampling superheterodyne receivers require high-speed high-resolution ADCs, because intermediate frequency (IF) signals are directly converted to digital codes.

Regardless of the receiver architectures, low-power consumption, and small die area are key specifications


Introduction


Among various ADC architectures, a pipelined ADC is suitabl

e for high-speed, high-resolution, and low-power operation. In low or medium speed and resolution pipelined ADCs,opam

p-sharing and switched-opamp techniques are widely used to reduce power consumption.

However, these techniques are rarely used for high-speed high-resolution ADCs because of some drawbacks, such as memory effects and limited sampling-rate .

Further power and area savings can be achieved by removing the front-end SHA .However, maximum input and sampling frequencies of the ADC without a SHA can be limited due to aperture error between different input sampling networks

Introduction

In this paper, the opamp-sharing technique is chosen for low-power and small area. A discharge phase is added to suppress memory effects. In addition, instead of removing the SHA, it is merged with the first MDAC. Thus, the ADC achieves low-power operation without compromising speed or accuracy


Low-Power Techniques In Pipeline ADC

A. Opamp-Sharing Technique(A conventional pipeline stage operates with a two-phase nonoverlapping clock)



Thus, significant power and area can be saved by reducing the number of opamps.

It also has two drawbackssince the opamp is always active, there is no time to reset

the opamp and the previous sample stored on the opamp input capacitance affects the current output

• This can be relaxed by using a feedback signal polarity inverting (FSPI) technique

Is that it requires additional switches at the opamp input node to disconnect the opamp when it is not needed.

• These switches introduce series resistance and degrade the settling behavior



B. Switched-Opamp Technique Switched-opamp was first invented for low-supply operation Since the opamp does not need to be active during the sampl

ing phase, it can be turned off. However, this requires the opamp to be turned on and off at each clock which limits the operating speed

Recently, a partially switched-opamp technique was proposed to improve the settling behavior at the cost of power consumption.

Unlike a conventional switched-opamp technique, the second stage of the two-stage opamp is turned off during the sampling phase(when the opamp is not needed).



C. Removing Front-End SHA In a typical pipelined ADC with opamp-sharing, the front-end

SHA consumes about 20% to 30% of the total ADC power and often limits the linearity and dynamic range of the ADC.

The concept of completely removing the SHA was first published for low-power operation in

It has two drawbacks it requires a short comparison phase between the samplin

g and amplification phases of the first stage and an additional feedback capacitor decreases the feedback factor.

Is an aperture error caused by resistance–capacitance (RC) delay mismatch between the input networks for the first multiplying digital to analog converter (MDAC) and the flash ADC


Proposed Opamp And Capacitor Sharing Technique

Further power and area savings can be achieved by sharing both the opamp and the capacitors

The idea behind the opamp and capacitor-sharing technique is that after the current stage generates the output, the charge on the feedback capacitor is reused for the following stage instead of being thrown away



Opamp and capacitor-sharing technique.



Two important facts need to be noted on this technique. First, the amplification phase is about 20% to 30% shorter than that of a conventional due to the addition of the discharge phase

Using this technique, the total opamp load in amplification phase is reduced by about 40% to 60% depending on the architecture of the stage compared to that of a conventional one. The reduced output load allows the opamp output to settle faster to the required accuracy without increasing power.

The second important fact relates to the memory effect However, since there is no reset phase between 1 and 2 , th

e stage i+1 has the memory effect. Thus,it is important to keep the error voltage caused by the memory effect small such that it does not affect the output of the stage i+1


Circuit Implementation In this prototype design, the SHA is completely merged with

the first MDAC (SMDAC)


Circuit Implementation

SMDAC works with three clock phases: sample/amplification (S/A), discharge and hold phases




1 11 1

1

( ( )) ( ( ))' [ ( ) ] (3 ) [0 ]

1( ) [1 (4 )] (2)

res restota F res F P

o o

PF res

o F

V N V NQ C V N C C

A A

CC V N

A C

1

( ( )) ( ( ))4 [ ( ) ] [0 ]

4 ( ) (1 ) (1)

in intota F in P

o o

F in

V N V NQ C V N C

A A

C V N

1

14 ( ) (1 ) ( ) [1 (4 )] (3)P

F in F reso F

CC V N C V N

A C

Since the total charge should be conserved on both phases

The error is even 25% smaller than that of a conventional SC amplifier.

1

4 ( ) (1 )( ) 4 ( ) (1 3 ) (4)

1 4in

res in

V NV N V N

3 (1/ )(3 / 4)(4 ( / ))o P FA C C

1/ (1/ ) (4 ( / )) / 4o o P F F F PA A C C C C C



The telescopic amplifier with gain boosting is chosen for high DC gain and power efficiency. The opamp achieves more than 90-dB gain in all corner simulations. The SMDAC opamp consumes about 32 mA, the second stage opamp consumes about 10 mA, and the opamps in the rest of the pipeline stages consume about 8 mA.

Measurement Results The prototype ADC is implemented in 0.18- m DGO CMOS te

chnology and occupies a die area of 7.28 (2.8*2.6 ). This includes the ADC core and the peripheral circuits such a

s bandgap, reference buffers,clock,SMDAC,digital error correction,5 opamp sharing stage&fadc.


2mm 2mm

Measurement Results The measured differential nonlinearity (DNL) and integral

nonlinearity (INL) are less than 0.8 and 2.1 LSB, respectively


Measurement Results


Typical measured FFT plots for the inputs frequencies 46 and 135 MHz

ENOB=SNDR-1.762/6.02 ENOB=11.4dB

Measurement Results Measured dynamic performance versus input and sampling

frequency


Measurement Results The comparison of figure of merit (FOM).

The ADC performance is summarized in Table I.


2ENOB

PowerFOM

Fs

Conclusion A 14-b 100-MS/s ADC with low power consumption and small

die area has been described In addition to sharing an opamp between two successive pipe

line stages, the front-end SHA are completely merged into the first MDAC by using the proposed opamp and capacitor sharing technique

The ADC achieves low power consumption and small die area while maintaining high-speed high-resolution operation


References

[1] P. C. Yu and H.-S. Lee, “A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp 1854–1861Dec. 1996.

[2] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger,“A 250-mW, 8-b, 52 Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,” IEEE J. Solid-State Circuits,vol. 32, no. 3, pp. 312–320, Mar. 1997.

[3] B.-M.Min, P. Kim, F. W. Bowman, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2031–2039, Dec. 2003.

[4] J. Arias, V. Boccuzzi, L. Quintanilla, L. Enriquez, D. Bisbal, M. Banu,and J. Barbolla, “Low-power pipeline ADC for wireless LANs,” IEEEJ. Solid-State Circuits, vol. 39, no. 8, pp. 1338–1340, Aug. 2004.

[5] J. Crols and M. Steyaert, “Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power supply voltages,”IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936–942, Aug. 1994.

[6] M.Waltari and K. A. I. Halonen, “1-V 9-Bit pipelined switched-opamp ADC,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 129–134, Jan.2001.

[7] D.-Y. Chang and U.-K. Moon, “A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique,” IEEE J. Solid-State Circuits,vol. 38, no. 8, pp. 1401–1404, Aug. 2003.

[8] H. C. Kim and D. K. J. Kim, “A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 795–801, Apr.2006.


a 14-b 100-ms/s pipelined adc with a merged sha and first mdac byung-geun lee, member, ieee,...

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