a 12-bit self-calibrating sar adc achieving a nyquist 90.4-db sfdr

A 12-bit self-calibrating SAR ADC achieving a Nyquist 90.4-dBSFDR

Hua Fan • Xue Han • Qi Wei • Huazhong Yang

Received: 10 March 2012 / Revised: 24 June 2012 / Accepted: 3 October 2012 / Published online: 25 October 2012

� Springer Science+Business Media New York 2012

Abstract This paper describes a 10 or 12 bit program-

mable successive approximation register ADC for bridge

stress monitoring systems requiring high-resolution, high

linearity, low power and small size. Its sampling rate is

scalable, from 0 to 200 kS/s. The proposed ADC employs a

novel time-domain comparator with offset cancellation.

Prototyped in a 0.18-lm, 6MIP CMOS process, the ADC,

at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 68.74 dB

(11.13), an SFDR of 90.36 dB, while dissipating 579.6 lW

from a 1.8-V supply. The on-chip calibration improves the

DNL from ?0.2/-0.74 LSB to ?0.23/-0.25 LSB and INL

from ?1.27/-0.97 LSB to ?0.41/-0.4 LSB.

Keywords Analog-to-digital converter (ADC) �Self-calibrating � Successive approximation register (SAR)

1 Introduction

With the advance of ubiquitous sensor networks focusing

on the technologies for bridge stress monitoring, industrial

monitoring, environmental control and prevention of

disasters or accidents, on-chip analog-to-digital converters

(ADCs) have been becoming essential for the development

of highly sensitive, stable, and robust sensor interfaces.

Successive approximation register (SAR) ADC is known

for its prominent energy efficiency these years [7–9, 20, 31,

27]; simple and OPAMP-less architecture also render it

more amenable to sensor network applications than other

Nyquist ADC architectures such as pipeline.

This work is aimed for general wireless sensor network

applications, in particular for bridge stress monitoring

systems. In these systems, high linearity, low power, and

low cost ADCs have been essential for the development of

highly sensitive, stable, and robust sensor networks. The

performance of the ADC, in terms of the required resolu-

tion and linearity, is important because the detectable sig-

nal amplitude is very small, and the ADC will introduce the

quantization noise and distortion to the signal, the resolu-

tion should be chosen high enough to provide the adequate

signal-to-noise-plus-distortion ratio (SNDR) and spurious

free dynamic range (SFDR). As a result, resolution and

linearity are paramount design objectives. Moreover, re-

configurability in sample rate and resolution is desirable to

allow for flexibility in the detectable signal amplitude

range. However, the linearity of SAR ADCs is usually

limited to around 10 bits due to process limitation [22]. The

main factors limiting the accuracy and linearity of the SAR

ADC are: comparator offset and capacitor mismatch (*10

bit in 0.18 lm).

In [30] at first, comparator offset is cancelled by using

all of the following three techniques: (1) two preamp stages

which achieve an overall gain of about 30 dB; (2) input

offset cancellation with auxiliary calibration capacitive

digital-to-analog converter (DAC); and (3) chopping to

remove comparator offset and reduce the 1/f noise [29].

Then, capacitor mismatch is cancelled by using another

auxiliary calibration capacitive DAC which injects a cor-

recting charge into the charge balance node for each bit

decision. The capacitor mismatch calibration makes pos-

sible the implementation of SAR ADCs with resolution

beyond the matching limit.

H. Fan (&) � X. Han � Q. Wei � H. Yang

Department of Electronic Engineering, TNList, Tsinghua

University, Haidian, China

e-mail: [email protected]

H. Yang

e-mail: [email protected]

123

Analog Integr Circ Sig Process (2013) 74:239–254

DOI 10.1007/s10470-012-9977-6

Another similar self-calibrating SAR ADC was reported

in [15]. In [15], the comparator offset is cancelled by using:

(1) preamp; (2) input offset cancellation with auxiliary cal-

ibration capacitive DAC; and (3) output offset cancellation.

It must be noted that, different from [30], where two cali-

bration DACs are introduced into the system for comparator

offset cancellation and capacitor mismatch calibration,

respectively, here, the capacitor mismatch calibration and

the comparator offset calibration make use of the same

auxiliary calibration capacitive DAC, this greatly decreases

the die area and complexity of layout. Smaller area in turn

contributes to smaller power consumption, since the smaller

parasitic capacitance reduces the required drive power.

However, the actual calibration was done via off-chip FPGA.

This paper presents a 10 or 12 bit programmable SAR

ADC that utilizes an improved capacitor–resistor network

with on-chip digital calibration technique to correct com-

parator offset and capacitor mismatch based on [30] and

[15]. There are three major differences between the

improved capacitor–resistor network and that in [30]: (1) In

[30] capacitive DAC in capacitor–resistor network is based

on two’s complement architecture. The total capacitance of

the DAC in two’s complement architecture is 2N 9 Cu,

here, N is the resolution of main DAC, Cu is the unit

capacitor in DAC. In this work, the tri-level based capaci-

tive DAC proposed in [5] is used to take the place of con-

ventional capacitive DAC in capacitor–resistor network.

This improves conventional capacitor–resistor network in

the following two aspects: first, the total capacitance of the

main DAC is 2N-1 9 Cu, only half of the conventional

capacitive DAC, so the area reduction of main DAC is

about twice. Secondly, simulation results show that the total

power consumption of 10 bit tri-level based SAR ADC is

44.8 % of the conventional SAR ADC; (2) Bottom-plates of

capacitors are used to sample the input rather than top-

plates, so there is no signal-dependent charge injection; and

(3) Tri-level based capacitor mismatch calibration method

is proposed. In Sect. 3.2, we will discuss the tri-level based

capacitor mismatch calibration in detail. In addition, a novel

digital differential time-domain comparator based on [2]

with improved offset is proposed, which, instead of oper-

ating in the voltage domain, transforms the differential

inputs into pulses and compares their arrival times. The

time-domain comparator only dissipates dynamic power by

eliminating the preamplifier in conventional voltage com-

parator. Note that the proposed time-domain comparator

can be applied to both single-ended and differential SAR

ADCs, whereas the time-domain comparator in [2] can only

be applied to single-ended SAR ADC. Furthermore, the

digital time-domain comparator has eliminated the only

analog part of SAR ADC, meaning that entire SAR opera-

tion is moved to digital-domain, which enables the SAR

ADC more amenable to technology scaling than other

Nyquist ADC architectures. This paper is organized as

follows: Section 2 describes the design and architecture of

the proposed SAR ADC. Section 3 presents the error cor-

rection and calibration process using the correction capac-

itive DAC. Section 4 shows the experimental results.

Finally, Sect. 5 provides a short conclusion.

2 Circuit design

2.1 ADC architecture

Figure 1 shows the block diagram of the 10 or 12 bit pro-

grammable differential SAR ADC. It comprises combined

capacitor–resistor network, a calibration DAC, a novel

digital time-domain comparator, and the control logic. The

combined capacitor–resistor network is composed by 10-bit

capacitive main DAC and 2-bit resistor-string sub DAC

without digital decoding [11], which provides the ADC the

flexibility to switch between 10- and 12-bit resolution if

necessary. The 10 bit main DAC is based on tri-level charge

redistribution architecture to improve the switching energy

efficiency and simplify the SAR control logic circuits.

Furthermore, the tri-level based DAC has intrinsically one

more bit resolution than the conventional DAC [5], so the

total capacitors to realize a 10-bit DAC using this approach

are halved compared with the conventional one using ‘‘trial-

and-error’’ switching procedure. The metal-insulator-metal

(MIM) capacitors in the 0.18 lm CMOS process only

match to about 10 bits; in order to achieve the desired 12-bit

resolution, a 10-bit capacitive DAC is introduced into the

system to correct the mismatches of the upper 8 bits. The

conversion plans for the 10-bit and 12-bit modes of this

ADC are shown in Fig. 2. In 10-bit 100 kS/s mode, the

main clock frequency fclk is 1.1 MHz, the conversion

requires 11 clock periods of the main clock: the first one for

the input sampling, ten periods for the bit cycles. In 10-bit

200 kS/s mode, fclk is 2.2 MHz. No calibration for com-

parator offset or capacitor mismatch calibration is imple-

mented in 10-bit mode. In 12-bit mode, the accuracy of the

SAR ADC and capacitor mismatch measurement both

heavily rely on the accuracy of the comparator, so the

comparator offset cancellation is implemented prior to the

main DAC linearity calibration; otherwise, it will result in a

linearity error. In 12-bit 100 kS/s mode, fclk is 1.3 MHz.

First, 11 clock periods are used for the comparator offset

cancellation through 10-bit calibration DAC. Then, the

capactior mismatch calibration begins by measuring the

nonlinearity due to the MSB capacitor. 13 clock periods are

required to store the digital representation of the mismatch

of the MSB capacitor. The 8 MSB capacitors are calibrated.

Thus, 104 clock periods are needed for the capacitor mis-

match calibration. In 12-bit 200 kS/s mode, fclk is 2.6 MHz.

240 Analog Integr Circ Sig Process (2013) 74:239–254

123

It is worth noting that the ADC is allowed to re-run cali-

bration any time in order to capture the temperature

dependent change in both offset and mismatch. Once the

interrupt signal for recalibration is enabled, the normal

conversion of the ADC is interrupted and calibration is

performed again.

2.2 Tri-level based capacitor–resistor network DAC

The DAC capacitor array is the basic structure of the SAR

ADC and it serves both to sample the analog input voltage

and as a DAC for generating an error voltage between the

input and the current digital representation of the analog

input value via a binary search algorithm. The DAC choice

is combined capacitor–resistor network [30]. The alterna-

tive split DAC or C-2C ladder structures are not of interest

here owing to floating nodes which strongly influence the

accuracy and linearity [32]. This capacitor array in com-

bined capacitor–resistor network, however, uses charge

inefficiently during a conversion, so the tri-level based

DAC can take place of the conventional capacitive DAC in

capacitor–resistor network.

Figures 3 and 4 detail the differences between the con-

ventional and the tri-level based switching scheme using a

3-bit SAR ADC [5]. Since the ADC is fully differential, the

operation of the positive and negative sides is complemen-

tary. For simplicity, only the positive side of the ADC

operation is described below. During sampling, shown in

Fig. 3, the top-plates of the differential capacitor arrays are

shorted to common-mode voltage VCM, and the entire

capacitor array stores the voltage VCM–VIN. Note that

VCM does not need to be exactly at the center of the full

reference range in a fully differential circuit, because it is a

common level and will be cancelled out. During the MSB

decision phase, since the MSB notifies whether the input is

larger or smaller than 0, the MSB can be determined directly

by placing the sampled differential inputs at the comparator;

in the meantime, all the capacitors’ bottom plates are

switching to the common-mode voltage VCM, resulting in

the equivalent output voltage -Vin at the inputs of com-

parator; thus, the comparator compares the input voltage

with 0 and decides the MSB code (Fig. 4(a)). Hence, the

MSB behaves like a sign bit, which reduces the capacitors by

half. If -Vin[0, 2C is switched to VREFN while the other

capacitors remain connected to VCM, dropping the voltage

at inputs of comparator to -Vin-VREF/2. If -Vin\0, 2C

is switched to VREFP, raising the voltage at inputs of com-

parator to -Vin?VREF/2. All of the remaining decisions

follow the same switching scheme, proceeding to smaller

capacitors. Finally, Vxp and Vxn converge towards VCM.

Note that the tri-level based DAC produces a proper

reference level without the largest capacitor, (4C), owing to

the additional common-mode voltage VCM. In addition,

since the DAC needs no ‘‘trial and error’’, switch-back

operations exist in the conventional design are not required.

Therefore, the MSB capacitor can be removed from the

3-bit DAC array, leading to a reduction by half of the

number of capacitors used in the ADC, and avoiding

the mismatch error at the conventional MSB transition. The

only additional cost of this method is that it uses n more

switches to initially reset all the capacitors to VCM, here, n

is the resolution of the ADC.

C C

256C CC

D0

D1

D11

VREFP

VCMVINP

VCM

VREFN

VINNVCM

Vxp

Vxn

256C

512C

VREFN

VREFP

Main DAC

SubDAC

Con

trol

lerCc

Cc

CALDAC

512C

Tri-level based architecture removesthe MSB capacitor in DAC

10

2

10

Fig. 1 10 or 12 bit programmable and digitally calibrated SAR ADC block diagram

Analog Integr Circ Sig Process (2013) 74:239–254 241

123

2.3 A novel time-domain comparator

Figure 5 shows the circuit schematic of the proposed dig-

ital time-domain comparator. It consists of an improved

voltage-to-time converter (VTC) based on [2] and a time-

to-digital converter (TDC) [19]. The VTC proposed in [2]

is shown in Fig. 6. There are two major differences

between the proposed VTC and the one proposed by

ADC power on

Normal OperationComp.

CAL DAC

Conversion ModeADC

Outputs

Normal Operation

RST

Idle

Idle

Idle

Does not work

Idle Conversion Mode

CLK

11 clock cycles 11 clock cycles

11 1 11 11 1 111

fclk=1.1M @100kS/s

(a)

ADC power on

OffsetCancel

Normal Operation

Normal Operation

Comp.

For Offset Cancel

Conversion Mode

ADCOutputs

Calibration Mode(ADC outputs are invalid)

For MismatchCal.

RST

IdleIdle

Idle

CAL DAC

CLK1 11 1 104 1 13 1 13

Idle Idle

Idle

11 clock cycles 104 clock cycles 13 clock cycles fclk=1.3MS/s@100kS/s

(b)

1

Fig. 2 ADC conversion

waveforms showing a 10-bit

100 kS/s conversion plans and

b 12-bit 100 kS/s conversion

plans

C C

2C CC

VREFP

VCMVINP

VCM

VREFN

VINNVCM

Vxp

Vxn

2C

VREFN

VREFP

VREFN

VREFP

C

2C C

VREFPVINP

VCM

VREFN

VINN

Vxp

Vxn

2C4C

4C

C

C

(a) (b)

Fig. 3 DAC during sampling

phase: a tri-level based

b conventional


123

Agnes. The most important one is that the proposed VTC

achieves smaller offset by combining two discharge bran-

ches into one, as shown in Fig. 5(a), then the input-referred

offset caused by the deviation of resistors RD in Fig. 6 can

be avoided. Moreover, the proposed time-domain com-

parator can be applied to both single-ended and differential

SAR ADC, while the time-domain comparator in [2] can

only be applied to single-ended SAR ADC. TDC detects

phase difference between Outp and Outn, and manifests

this result in Out, which is also the output of the compar-

ator. TDC with symmetrical input paths proposed in [19] is

adopted in this work. However, the simple back-to-back

NAND SR-latch in [19] suffers from asymmetrical delays

between rising and falling edges. This latch can be further

replaced by a more symmetrical and faster one presented in

[25]. The operation of the time-domain comparator is as

follows: When the signal CLK is high, the nominally equal

capacitors C1 and C2 will be charged to VDD through

transistors M5 and M6, while node A is discharged to

remove any residual charge. The nodes Outp and Outn,

which are the outputs of voltage to time converter as well

as the inputs of binary phase detector, are reset to 0. The

nodes B, C, D and E are initially set to high. When CLK

makes transition to low, transistors M1 and M2 become

constant current generators and discharge capacitors C1

and C2 at a constant rate, the VTC generate a pulse delay

difference proportional to the input voltage difference. The

time-domain comparator obviates the need of preamplifier

that dissipates static power and the highly digital con-

struction of comparator offers all the benefits of the digital

CMOS technology.

The accuracy of the comparator is mainly determined by

KT/C noise voltage across C1, C2 and the latch time

margin DT .

The minimum input voltage error DVin caused by the

time error DT can be calculated as follows. When inputs of

the VTC approach to 0 (i.e. VINN & VINP = VCM),

according to iDt ¼ CDVth;INV (C1 = C2 = C), here

DVth;INV is the voltage drop across the capacitor, we can get

VINP � Vgs1

2RDDt1 ¼ CDVth;INVA ð1Þ

VINN � Vgs2

2RDDt2 ¼ CDVth;INVB ð2Þ

here VINN & VINP = VCM, we can get DVth;INVA �DVth;INVB ¼ DVth;INV )

Dt1 ¼ 2RDCDVth;INV

VINP � Vgs1

ð3Þ

Dt2 ¼ 2RDCDVth;INV

VINN � Vgs2

ð4Þ

According to (3) and (4), we can get

DT ¼ Dt1� Dt2 � 2RDCDVth;INVDVin

ðVCM � Vgs1;2Þ2ð5Þ

So the error voltage DVin caused by time error DT is equal

to:

DVin ¼ DTðVCM � Vgs1;2Þ2

2RDCDVth;INVð6Þ

The KT/C error voltage caused by charging and

discharging capacitance is equal to

VC;noise ¼ffiffiffiffiffiffiffi

KT

C

r

ð7Þ

Which is referred to the input, we can get

(a) (b)

C C

2C CC

VREFP

VCMVINP

VCM

VREFN

VINNVCM

Vxp

Vxn

2C

VREFN

VREFP

C

2C C

VREFPVINP

VCM

VREFN

VINN

Vxp

Vxn

2C4C

4C

VREFN

VREFP

C

C

0 0

Fig. 4 DAC during MSB

decision phase: a tri-level based

b conventional


123

VC;noise in ¼

ffiffiffiffiffi

KTC

q

Gain¼

ffiffiffiffiffiffiffi

KT

C

r

IRDRD

Vth;INV¼

ffiffiffiffiffiffiffi

KT

C

r

VRD

Vth;INVð8Þ

Then, the accuracy of the comparator Vaccu comp can be

estimated according to (6) and (8)

Vaccu comp ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

ðVc;noise inÞ2 þ ðDVinÞ2

q

ð9Þ

In conclusion, the accuracy of the comparator can be improved

by changing the value of C and RD. What should be mentioned

is that, a possible mismatch between the two discharge bran-

ches causes an input-referred offset, which is identical to that

of the conventional voltage comparator; offset cancellation of

this comparator is described in a later subsection.

3 Digital calibration

3.1 Comparator offset cancellation

The offset in the comparator of the SAR ADC limit the

system’s performance because any input signal that is

smaller than the input offset leads to unpredictable ADC

output. Capacitor mismatch measurement also heavily

relies on the accuracy of the comparator. So the comparator

offset cancellation becomes critical. Various comparator

offset cancellation techniques have been published. One

common solution for suppressing the offset of the com-

parators is adding a preamplifier but suffers from static

power dissipation and offset from itself, which leads to the

CLK

M1VINP

VDD

C2

CLK

C1

M2

RD

VINN

Outp

M3 M4

M6M5

M7

A

INVA INVB Outn

(a)

IRD

OutOut

VDD VDD

VDD VDD

B C

M9 M8

M10 M11

D E

OutpOutn

Outn

(b)

Outp

Fig. 5 Schematic of proposed

differential time-domain

comparator a voltage-to-time

converter and b time-to-digital

converter


123

limited performance of the comparator [28]. Instead of

using preamplifier, the error tolerant 1.5-bit-per-stage

conversion scheme in pipelined ADCs is a feasible method,

where wrong decisions made in earlier stages can be

compensated as long as they are within the error tolerance

range. Redundant 1.5-bit-per-stage allows large offset

calibration range, but it doubles the number of comparators

and the structure of ADC must be altered, leading to

increase in design complexity and die area [10]. Another

offset cancellation technique [8] adjusts capacitance of the

output nodes of comparator to balance the output current,

which dissipates no static power; the minimum offset step

is controlled by unit capacitance of the output nodes;

however, to keep the calibrated offset resolution, the

smallest variable step of capacitance is always smaller than

1fF [8], which is hard to realize using high precision MIM

capacitors, so it can only be implemented with voltage-

controlled variable capacitor, such as PMOS transistor. It is

difficult to control the small capacitance under process

variations, so this method is usually applied to SAR ADC

with resolution smaller than 10 bits [24].

Offset cancellation techniques that are more suitable for

low voltage and high resolution design are expected for this

SAR ADC design. An open loop successive approximation

based offset cancellation method can be used to cancel the

offset of the time-domain comparator. The offset cancel-

lation is done by shorting all capacitors at the comparator

input to the common level VCM for offset storage

(Fig. 7(a)); once the offset is known, the 10 bit calibration

DAC generates a voltage successively converging to the

stored offset through capacitive coupling (Fig. 7(b)). The

final input word of the DAC is then stored as the digital

representation of the input referred offset of the compara-

tor. Eq. (10) indicates how DAC’s outputs converge to the

stored offset, where, Vos is the offset voltage of the time-

domain comparator, DOFF is the final input word of the

DAC. VREF is difference of VREFP and VREFN, Ctotal

represents the total capacitance of the main DAC, Ccal

represents the total capacitance of the calibration DAC and

Cc is the coupling capacitor. It is clear that the maximum

offset voltage that the cancellation technique can accom-

modate is proportional to the size of the coupling capacitor

Cc. To maximize the calibration efficiency, the coupling

capacitor Cc is adjustable in order to change the calibration

range, which prevents the unexpectedly poor matching due

to limited production properties; proper value of Cc was

chosen to guarantee the offset cancellation is capable of

flexibly handling any case of comparator input offset.

Vxp� Vxn ¼ VosþCcalCc

CcalþCc VREF

Ctotalþ CcalCcCcalþCc

2DOFF;MSB � 1

21þ . . .þ 2DOFF;LSB � 1

210

� �

ð10Þ

During the capacitor mismatch measurement and ADC

normal conversion, the digital offset word is retrieved from

registers to cancel the comparator input referred offset.

Thanks to offset cancellation, device sizing of the

VDD

CLK

CLK

Vin

M5

M3

M1

M11 RD

C1

VDD

VB M2

M4

M12 RD

C2

CLK

CLK

M9

M8

M13

M7

VDD

CLK

VDD

M6

CLK

Outp

Outn

QD

CK

Out

Fig. 6 Schematic of time-

domain comparator proposed by

Agnes


123

comparator is not constrained by any matching require-

ment. This is beneficial because the charge sharing between

the comparator input capacitance and the sampling

capacitor attenuates the sampled signal, so degrades the

SNR.

3.2 Capacitor mismatch calibration

The main DAC is composed of capacitors sized to produce

ratios in powers of 2, or binary ratios. Errors in these ratios

correspond to errors in conversion. Typically, the dominant

source of the largest ADC error is the DAC capacitor

mismatch error. The static linearity of SAR ADCs is usu-

ally limited to around 10 bits, so several techniques have

been reported in an attempt to improve the linearity of

ADC’s beyond the limit of matching to achieve intrinsic

linearity of 12 bits and beyond.

One approach is to simply size the capacitors large

enough and use complicated common centroid layout

technique to build a 12-bit accurate capacitor array [25].

However, as described in [12], this can impose severe die

area and power dissipation penalties.

(a)

(b)

C C

256C CC

VREFPVCMVINP

VCM

VREFN

VINNVCM

Vxp

Vxn

256C

VREFN

VREFP

Main DACP

Cc

Cc

CALDACP

CCALP

VOFFSET

CALDACN

Con

trol

ler

CCALN

Main DACN

C C

256C CC

VREFPVCMVINP

VCM

VREFN

VINNVCM

Vxp

Vxn

256C

VREFN

VREFP

Main DACP

Cc

Cc

CALDACP

CCALP

VOFFSET

CALDACN

Con

trol

ler

CCALN

Main DACN

Fig. 7 Comparator offset error

measurement


123

Trimming is another technique, but it is costly in terms

of fabrication processing and chip area. Additionally, it

cannot track variations over time caused by component

aging, temperature variations, and supply voltage changes.

An example of foreground calibration is given in [23],

which requires a separate calibration reference source, and

the resistor ladder needs static current and consumes large

area and power.

Another example of foreground calibration was reported

[15] as a way to align the mismatch of capacitors using

capacitive calibration DAC, but the actual calibration was

done via off-chip FPGA.

An example of a background calibration is given in [21],

nonbinary design with radix = 1.86 can correct the mis-

match of the radix between each bit by using the pertur-

bation technique; however, in that structure, the non-

integer ratio of the capacitor significantly increases layout

complexity and needs sophisticated post-processing, and

the actual calibration was also done via off-chip software

approach.

To ease system complexity, and obviate the need of

complicated post-processing and maximally exploit the

architectural advantages of SAR, the foreground mismatch

self calibration based on tri-level DAC is introduced.

During the startup calibration, the mismatches of the

capacitor are measured by a calibration ADC after the

comparator offset cancellation is completed. The central

idea behind self-calibration is that the sum of all mis-

matching errors is 0 [17]. Each weighted capacitor Cn is

assumed to be off a factor of ð1þ enÞ from the ideal value

due to process variations. The total linearity error consists

of contributions from each capacitor ratio error [18].

It should be mentioned that because the main DAC is

tri-level based, the measurement of capacitive mismatch is

somewhat different from the conventional method. The

measurement of capacitor mismatch error is executed using

a 3-bit example shown in Fig. 8. The calibration cycle

begins by measuring the nonlinearity due to the MSB

capacitor 2C. First, MSB capacitor 2C is switched to the

VREFP and all the other capacitors are connected to VCM,

Vxp and Vxn are shorted to VCM at the same time. Then,

the bottom plate voltages are exchanged between 2C and

all the other capacitors, and the short switches are open. At

this time, the ideal residual voltage Vxp-Vxn is 0; however,

due to the MSB capacitor mismatch eMSB, the actual

residual voltage is [17]:

VresMSB ¼ Vxp� Vxn ¼ eMSBðVREFP� VREFNÞ ð11Þ

If the MSB capacitor is perfect, it will have exactly half of

the total array capacitance, the weight of MSB capacitor is

exactly 12. A ratio error in the MSB will cause a weight error,

the error voltage VeMSB due to MSB capacitor ratio error is

VeMSB ¼1

2eMSBðVREFP� VREFNÞ ð12Þ

It can be easily shown that the general relation between

residual voltage Vres and the error voltage due to MSB

capacitor ratio error is

VresMSB ¼ 2VeMSB ð13Þ

or in digital domain

DVeMSB ¼DVresMSB

2ð14Þ

Where DVeMSB and DVresMSB stand for digitized error

voltages and digitized residual voltages, respectively. Once

the first capacitor is measured, the same procedure can be

repeated to measure other capacitors one by one.

It is worth noting that the capacitor mismatch calibration

and the comparator offset calibration make use of the same

auxiliary calibration capacitive DAC to decrease die area

and complexity of layout, so the digitized offset must be

subtracted from Eq. (14), then, Eq. (14) becomes

DVeMSB ¼ ðDVresMSB � DOFFÞ � 1 ð15Þ

C C

2C CC

VREFPVCM

VCM

VREFN

VCM

Vxp

Vxn

2C

VREFN

VREFP

C C

2C CC

VREFPVCM

VCM

VREFN

VCM

Vxp

Vxn

2C

VREFN

VREFP

Fig. 8 MSB capacitor

mismatch error measurement


123

Here, ‘‘ �’’ 1 represents shift right operation, and DOFF is

the digital representation of the offset voltage.

Similarly, errors due to smaller capacitors are measured

DVeMSB�1 ¼ ðDVresMSB�1 � DOFF � DVeMSBÞ � 1 ð16Þ

DVeMSB�2 ¼ðDVresMSB�2 � DOFF�DVeMSB � DVeMSB�1Þ � 1

ð17Þ

..

.

DVeLSB ¼ ðDVresLSB�DOFF �X

8

i¼2

DVeiÞ � 1ð18Þ

After each residue voltage has been digitally captured

using calibration DAC, all these error terms are stored in

digital memory.

The calculations involved in this measurement consist of

simple addition, subtraction, in combination with shift right

operations, enabling a small and efficient on-chip digital

calibration engine.

It is worth noting that the mismatch calibration logic

based on tri-level DAC is simpler than the conventional

calibration logic which must be in step with ‘‘trial and error’’

search procedure. In conventional SAR ADC, when the nth

bit is being tested, at first, the corresponding capacitor is

switched to VREFP by giving a test bit of 1, and the cor-

rection term DVen is added to the correction terms accumu-

lated from the first bit (MSB) through the (n - 1)th bit. If the

bit decision is 1, the added result is stored in the accumulator.

Otherwise, DVen is dropped, leaving the accumulator with

the previous result [18]. However, in tri-level based charge

redistribution SAR ADC, the straightforward DAC switch-

ing avoids the switch-back operations in the conventional

design, the computation of correction term just needs to be

directly performed. Assuming that the ones equal in average

to the zeros, 6 times of unnecessary subtraction operations

are avoided.

Capacitor mismatch calibration provides the opportunity

to minimize the capacitor sizes, resulting in compact

design, layout, smaller area in turn contributes to smaller

power consumption, because the smaller parasitic capaci-

tance reduces the required drive power.

4 Experimental results

4.1 ADC test setup

The prototype was fabricated in a 0.18-lm six-metal one-

polysilicon (6M1P) CMOS process with MIM capacitors.

A micrograph of the entire ADC is shown in Fig. 9. The

active area of the ADC is 1,565 9 1,772 lm with digital

circuits implemented on-chip. All measurement results

described in this section were obtained at room tempera-

ture. The testing was carried out using Printed-Circuit-

Boards (PCBs). Major testing equipments include signal

generators, power supplies and logic analyzer. Agilent

33120A was used to generate high performance system

clock signal. Firstly, when the start signal is active, the

digital circuits will start to generate control signals and

DATAREADY signal. Thus, by observing the DATA-

READY signal, it can be initially checked if digital circuits

are operated as expected. Secondly, the sine wave is gen-

erated by an ultra-low distortion function generator DS360,

which can provide better than -100 dB distortion over the

audio frequency range, and no filter was used. The sine

input voltage is sampled and converted into 12-bit digital

codes by the proposed data converter. The output codes of

D0 to D11 were captured by Logic Analyzer, and then

transferred to a PC to obtain the ENOB, SNDR and SFDR

using matlab. Table 1 lists all the details of all the equip-

ments used during the SAR ADC testing.

4.2 Dynamic performance

The dynamic performance test of the prototype SAR ADC

was conducted using a full-swing, differential sinusoidal

input with amplitude of 1.2 V. To test the 10-bit mode

Cal

ibra

tion

DA

C

MA

IN-D

AC

Com

para

tor

Con

trol

ler

Sub

-DA

C

1772 m1565

m

Fig. 9 Micrograph of entire ADC prototype

Table 1 List of test equipments

Function Equipment name

CLK generator Agilent 33120A

Vin generator Standford Research Systems DS360

Power supplies Agilent E3631A

Logic analyzer Agilent 16823A

Evaluation software Matlab

PCB board Custom design


123

linearity, no calibration is performed. In 10-bit mode, Fig. 10

shows the SNDR and SFDR variations of this ADC with

respect to the input frequency. With the input frequencies

increased to the Nyquist frequency, the SNDR and SFDR

maintain over 60.92 and 76.36 dB at 100 kS/s; the SNDR

and SFDR maintain over 60.97 and 76.18 dB at 200 kS/s. A

fast Fourier transform (FFT) of the ADC at Nyquist opera-

tion in 10-bit mode is shown in Fig. 11(a) (fs = 100 kS/s)

and Fig. 11(b) (fs = 200 kS/s). The ADC achieves a

Nyquist SNDR of 61.11dB (9.86 ENOB) and an SFDR

of 77.8 dB when it samples at 100 kS/s, and achieves a

Nyquist SNDR of 60.99 dB (9.84 ENOB) and an SFDR

of 76.18 dB when it samples at 200 kS/s.

In 12-bit mode, Fig. 12 presents the dynamic perfor-

mance versus the input frequency measured with a 2.4-Vpp

input. Solid and dashed curves represent the measured

SNDR and SFDR before and after calibration respectively.

In the left figure, the SAR ADC was measured at 100 kS/s,

with a 39.83-kHz input, the peak SNDR and SFDR are

68.92 dB (11.16 ENOB) and 90.64 dB, respectively. In the

right figure, the SAR ADC was measured at 200 kS/s, with

a 18.78-kHz input, the peak SNDR and SFDR are 68.96 dB

(11.16 ENOB) and 89.05 dB, respectively, the SFDR drops

by 4.93 dB with an ENOB loss of 0.1-bit at the Nyquist

frequency (99.78 kHz) with respect to its low frequency

value, this distortion is due to the nonlinearity of the input

switch resistance, the loss of SNDR is likely due to noise

from the substrate and references.

FFT of the ADC at Nyquist operation in 12-bit 100 kS/s

mode is shown in Fig. 13. Before calibration, odd-order

0 10 20 4030 5060

65

70

75

80

Input Frequency(kHz)

(a)

dB

SNDR

SFDR

0 20 10040 60 8060

65

70

75

80


(b)

dB

SNDR

SFDR

Fig. 10 Measured SNDR and

SFDR versus the input

frequency in 10 bit mode

a at fs = 100 kS/s

b at fs = 200 kS/s

0 20 4010 30 50−120

−100

−80

−60

−40

−20

0


(a)

dB

0 20 10040 60 80−120

−100

−80

−60

−40

−20

0


(b)

dB

Fin=99.78kHz@200kS/sSNDR=60.99dBSFDR=76.18dBENOB=9.84


Fig. 11 FFT of ADC in 10 bit

mode with Nyquist input tone

a at fs = 100 kS/s

b at fs = 200 kS/s

0 10 20 30 40 5060

65

70

75

80

85

90


(a)

dB

0 20 10040 60 8065

70

75

80

85

90


(b)dB

SNDR(CAL OFF)SFDR(CAL OFF)SNDR(CAL ON)SFDR(CAL ON)

SNDR(CAL OFF)SFDR(CAL OFF)SNDR(CAL ON)SFDR(CAL ON)

Fig. 12 Measured SNDR and

SFDR versus the input

frequency in 12 bit mode before

and after calibration

a at fs = 100 kS/s

b at fs = 200 kS/s


123

0 10 4020 30 50−120

−100

−80

−60

−40

−20

0Before Calibration

Input Frequency(kHz)dB

0 20 4010 30 50−120

−100

−80

−60

−40

−20

0After Calibration


dB



Fig. 13 FFT of ADC in 12 bit

mode with 49.83 kHz input tone

before (left) and after (right)calibration

0 200 1000400 600 800−0.2

−0.1

0

0.1

0.2

CODE

LSB

DNL

0 200 1000400 600 800−0.2

0

0.2

0.4

0.6

CODELS

B

INLFig. 14 Measured DNL and

INL in 10 bit mode at 100 kS/s

0 1000 2000 3000 4000−1

−0.5

0

0.5

CODE

LSB

DNL

0 1000 2000 3000 4000−1

−0.5

0

0.5

1

1.5

CODE

LSB


INL in 12 bit mode before

calibration at 100 kS/s

0 1000 2000 3000 4000−0.4

−0.2

0

0.2

0.4

CODE

LSB

DNL

0 1000 2000 3000 4000−0.5

0

0.5

CODE

LSB


INL in 12 bit mode after

calibration at 100 kS/s


123

harmonics are clearly visible, the distortion is due to the

capacitor mismatch. The calibration provides around 2-dB

SNDR improvement and almost 13-dB SFDR improvement.

The ADC achieves a Nyquist SNDR of 68.74 dB (11.13

ENOB) and an SFDR of 90.36 dB when it samples at 100 kS/s.

4.3 Static linearity

To test the static linearity, code density test was conducted

using a full-swing, differential sinusoidal input with input

frequency of 288.78 Hz. Figure 14 shows the differential

nonlinearity (DNL) and integral nonlinearity (INL) with

respect to the output code in 10-bit mode. The maximum

DNL is ?0.054 LSB/-0.19 LSB, maximum INL is ? 0.33

LSB/-0.18 LSB at 100 kS/s, while the maximum DNL is

?0.066 LSB/-0.21 LSB, maximum INL is ? 0.32 LSB/

-0.15 LSB at 200 kS/s. In 12-bit mode, without calibra-

tion, the INL plot shows that the INL has a jump at the

middle of output codes, the MSB capacitance might be

responsible for this inference due to technology limitations.

As shown in Fig. 15 and Fig. 16, the calibration improves

the DNL from ?0.2/-0.74 LSB to ?0.23/-0.25 LSB and

INL from ?1.27/-0.97 LSB to ?0.41/-0.4 LSB at

100 kS/s. At 200 kS/s, the calibration improves the DNL

from ?0.25/-0.72 LSB to ?0.23/-0.25 LSB and INL

from ?1.31/-0.81 LSB to ?0.36/-0.43 LSB.

Table 2 ADC performance

summary

[22] FOMa ¼ Power2ENOB�fs

[3] FOMb ¼ Power10SNDR=20�fs

[3] FOMc ¼ Power10SFDR=20�fs

Process 0.18 lm

Area 1565 9 1772 lm

Voltage supply (V) 1.8

Input range (V) 2.4-Vpp

10 Bit mode 12 Bit mode

Sampling Rate 100 kS/s 200 kS/s 100 kS/s 200 kS/s

SNDR (dB) (at Nyquist) 61.11 60.99 68.74 68.4

ENOB (at Nyquist) 9.86 9.84 11.13 11.07

SFDR (dB) (at Nyquist) 77.8 76.18 90.36 84.11

DNL (LSB) ?0.054/-0.19 ?0.066/-0.21 ?0.23/-0.25 ?0.23/-0.25

INL (LSB) ?0.33/-0.18 ?0.32/-0.15 ?0.41/-0.4 ?0.36/-0.43

Power (lW) 498.6 826.2 579.6 946.8

FOMa (pJ/step) 5.3 4.5 2.59 2.2

FOMb (pJ/step) 4.39 3.69 2.12 1.8

FOMc (pJ/step) 0.64 0.64 0.176 0.295

Table 3 Comparison of performance on several ADCs

This work JSSC [22] IJCTA [6] ISSCC [30] ISSCC [2] JSSC [2] ADI [1]

datasheet

ZMDI [33]

datasheet

Bits 12 12 12 12 12 12 12 12

Process (nm) 180 130 250 45 180 180 – –

MS/s 0.1 22.5 0.05 0.5 0.1 0.1 0.1 0.2

DNL/INL 0.25/0.41 – 1/1.945 1.5/1.4 0.5/0.7 0.66/0.68 0.95/1 1/1

SFDR 90.36 90.3 – 82 71.8 71 83 80

ENOB 11.13 11.35 11.01 11 9.4 10.55 11.5 11

FOMa(pJ/step) 2.59 0.051 14.69 0.78 0.056 0.165 10.36 8.79

FOMb(pJ/step) 2.12 0.0417 11.99 0.64 0.046 0.136 8.46 7.17

FOMc(pJ/step) 0.176 0.004 – 0.13 0.01 0.07 2.12 1.8

[22] FOMa ¼ Power2ENOB�fs

[3] FOMb ¼ Power10SNDR=20�fs

[3] FOMc ¼ Power10SFDR=20�fs


123

Table 2 summarizes the experimental results of the pro-

totype chip. Recently published and commercialized CMOS

ADCs with 12 bit resolution are compared with the proposed

ADC in Table 3. The presented ADC achieves the best

SFDR among all the works in Table 3. With on-chip cali-

bration, it achieves a Nyquist 90.36-dB SFDR when it

samples at 100 kS/s. The ADC presented in [22] also

achieves an SFDR of 90.3-dB, however, all calibration cir-

cuits in [22] are realized by using off-chip software rather

than on-chip implementation. The commercialized CMOS

ADCs dissipate more power consumption than other works is

mainly due to the fact that the power supply for commer-

cialized CMOS ADCs is always larger than 2.5 V. The

presented ADC shows smaller power consumption but

higher performance than the work in [6]. Also, the proposed

ADC shows comparable FOM3 to that of ADC presented in

[30]. Wang et al. [30] adopts the most advanced technology

among all the works in Table 3, and it shows better FOM1

and FOM2 than our work. The works such as [2] and [28] are

more efficient. This is mainly due to the fact that no cali-

bration is applied to the ADCs in [2] and [28], so the SFDR in

both works is non-ideal, about 71-dB. Also, ENOB in [2] or

[28] is smaller than all the other works presented in Table 3.

5 Conclusions

This work proposes a 10 or 12 bit programmable SAR ADC

for sensor interface applications such as bridge stress mon-

itoring systems. Tri-level based switching approach used in

the improved capacitor–resistor network saves capacitor

area by half and simplifies the control logic circuits. The

proposed novel digital time-domain comparator with no

static power consumption can be applied to both single-

ended and differential SAR ADC. The digital time-domain

comparator has obviated the only analog part of SAR ADC.

Since scaling of CMOS device dimensions offers clear

advantages for digital circuitry in terms of density, speed,

and integration, it is advantageous to move the whole SAR

operation into digital domain. The Digital calibration cancels

the offset of time-domain comparator and improves ADC

linearity, which is affected by different parasitic capaci-

tances between capacitors and neighboring signal lines. The

calibration scheme is implemented on-chip without com-

plicated post-processing, which is important for SOC

applications. In 12-bit mode, the SAR ADC achieves a

remarkable Nyquist SFDR of 90.36 dB and 11.13 ENOB at

100 kS/s after calibration. Using a 1.8-V supply voltage, the

achieved power consumption is 579.6 lW.

As a continuation of the work presented in this paper,

the priority of the future improvement is to design a more

efficient SAR ADC with a lower supply voltage. Since

lowering the supply voltage is the most effective way to

reduce power consumption assuming that the signal power

is proportional to VDD2. Then the low voltage time-domain

comparator needs to be further developed to achieve higher

accuracy and lower complexity. We have already done

some research and made some progress on low voltage

time-mode SAR ADC. For example, a 0.8 V ultra low

power SAR ADC has been proposed [14]. In addition,

discharge currents of C1 and C2 can be terminated as soon

as the comparison result is available [13] to obtain further

energy reductions. On the other hand, the simple back-

to-back NAND SR-latch in Fig. 5(b) suffers from asym-

metrical delays between rising and falling edges, this latch

can be further replaced by a more symmetrical and faster

one presented in [26]. Therefore, the plan for the next step

is to introduce these verified low power technique into our

design. Finally, considering longer term plan for higher

speed and resolution, the SAR ADC with multistage

pipelined architecture is attractive because of the area and

power efficiency [16, 10]. To the best of our knowledge,

pipelined SAR ADC previously published are all based on

voltage mode. If possible, we hope that we can introduce

low power time-mode technique to the pipelined SAR

ADC to obtain further energy reductions.

Acknowledgements This work was supported by the Ph.D. pro-

grams foundation of ministry of education of China (No.

20111011315), and the National Science and Technology Important

Project of China (No. 2010ZX03006-003-01)

References

1. ADI. (2005). Low power, pseudo differential, 100ksps 12-bit adc

in an 8-lead sot-23. Analog Devices datasheet.

2. Agnes, A., Bonizzoni, E., Malcovati, P., Maloberti, F. (2008).

A 9.4-enob 1v 3.8 lw 100 ks/s sar ADC with time-domain

comparator. In: Solid-State Circuits Conference, 2008. ISSCC2008. Digest of Technical Papers. IEEE International, IEEE

(pp. 246–610).

3. Ali, A., Dillon, C., Sneed, R., Morgan, A., Bardsley, S., Kornb-

lum, J., Wu, L. (2006). A 14-bit 125 ms/s IF/RF sampling

pipelined ADC with 100 db SFDR and 50 fs jitter. IEEE Journalof Solid-State Circuits 41(8), 1846–1855.

4. Chan, C., Zhu, Y., Chio, U., Sin, S., Seng-Pan, U., Martins, R.

(2009). A voltage-controlled capacitance offset calibration tech-

nique for high resolution dynamic comparator. In: SoC DesignConference (ISOCC), 2009 International. IEEE (pp. 392–395).

5. Chen, Y., Tsukamoto, S., Kuroda, T. (2009). A 9b 100 Ms/s 1.46

mW SAR ADC in 65 nm CMOS. In: Solid-State Circuits Con-ference, 2009. A-SSCC 2009. IEEE Asian, IEEE, pp 145–148.

6. Chiang, C. T., Chang, W. H. (2011). A 12-bit multi-channel dual-

mode successive approximation ADC for power management bus

(Pmbus) devices. International Journal of Circuit Theory andApplications, 1–16.

7. Cho, S., Lee, C., Kwon, J., Ryu, S. (2011). A 550-lw 10-b 40-ms/s

SAR ADC with multistep addition-only digital error correction.

IEEE Journal of Solid-State Circuits (99), 1–1.


123

8. Cho, T., Lee, K., Kong, J., Chandrakasan, A. (2009). A 32-lW

1.83-ks/s carbon nanotube chemical sensor system. IEEE Journalof Solid-State Circuits, 44(2), 659–669.

9. Craninckx, J., Van der Plas, G. (2007). A 65fj/conversion-step

0-to-50 Ms/s 0-to-0.7 mW 9b charge-sharing SAR ADC in

90 nm digital CMOS. In: Solid-State Circuits Conference, 2007.ISSCC 2007. Digest of Technical Papers. IEEE International,

IEEE (pp. 246–600).

10. Furuta, M., Nozawa, M., Itakura, T. (2011). A 10-bit, 40-Ms/s,

1.21 mW pipelined SAR ADC using single-ended 1.5-bit/cycle

conversion. IEEE journal of solid-state circuits, 46(6).

11. Hamade, A. (1978). A single chip all-MOS 8-bit A/D converter.

IEEE Journal of Solid-State Circuits, 13(6), 785–791.

12. Kinget, P. (2005). Device mismatch and tradeoffs in the design of

analog circuits. IEEE Journal of Solid-State Circuits, 40(6),

1212–1224.

13. Kobenge, S., Yang, H. (2009). A novel low power time-mode

comparator for successive approximation register ADC. IEICEElectronics Express 6(16), 1155–1160.

14. Kobenge, S., Yang, H. (2010). A 250 KS/s,0.8 v ultra low power

successive approximation register ADC using a dynamic rail-

to-rail comparator. IEICE Electronics Express 7(4), 261–267.

15. Kuramochi, Y., Matsuzawa, A., Kawabata, M. (2009). A 0.027-mm2

self-calibrating successive approximation ADC core in 0.18-lm

CMOS. IEICE Transactions on Fundamentals of Electronics Com-munications and Computer Sciences, 92, 360–366.

16. Lee, C., Flynn, M. (2011). A SAR-assisted two-stage pipeline

ADC. IEEE Journal of Solid-State Circuits (99), 1.

17. Lee, H., Hodges, D. (1983). Self-calibration technique for a/d con-

verters. IEEE Transactions on Circuits and Systems, 30(3), 188–190.

18. Lee, H., Hodges, D., Gray, P. (1984). A self-calibrating 15 bit

CMOS A/D converter. IEEE Journal of Solid-State Circuits,19(6), 813–819.

19. Lee, S., Park, S., Suh, Y., Park, H., Sim, J. (2009). A 1.3 lw 0.6 v

8.7-enob successive approximation ADC in a 0.18 lm CMOS.

In: VLSI Circuits, 2009 Symposium on IEEE (pp. 242–243).

20. Liu, C., Chang, S., Huang, G., Lin, Y. (2010a). A 10-bit 50-MSs/s

SAR ADC with a monotonic capacitor switching procedure.


21. Liu, W., Huang, P., Chiu, Y. (2010b). A 12b 22.5/45 MS/s 3.0

mW 0.059 mm2 CMOS SAR ADC achieving over 90 db SFDR.

In Solid-State Circuits Conference Digest of Technical Papers(ISSCC) IEEE International, IEEE (pp. 380–381).

22. Liu, W., Huang, P., Chiu, Y. (2011). A 12-bit, 45-MS/s, 3-mW

redundant successive-approximation-register analog-to-digital

converter with digital calibration. IEEE Journal of Solid-StateCircuits (99), 1.

23. Maio, K., Hotta, M., Yokozawa, N., Nagata, M., Kaneko, K.,

Iwasaki, T. (1981). An untrimmed D/A converter with 14-bit

resolution. IEEE Journal of Solid-State Circuits, 16(6), 616–621.

24. Promitzer, G. (2000). 12 bit low power fully differential switched

capacitor non-calibrating successive approximation ADC with

1MS/s. In IEEE Solid-State Circuits Conference, 2000. ESS-CIRC’00. Proceedings of the 26th European (pp. 176–179).

25. Ueda, Y., Yamauchi, H., Mukuno, M., Furuichi, S., Fujisawa, M.,

Qiao, F., Yang, H. (2006). 6.33 mW MPEG audio decoding on a

multimedia processor. In IEEE International Solid-State CircuitsConference, 2006. ISSCC 2006. Digest of Technical Papers(pp. 1636–1645).

26. Van der Plas, G., Decoutere, S., Donnay, S. (2006). A 0.16 pJ/

conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital

CMOS process. In IEEE International Solid-State CircuitsConference, 2006. ISSCC 2006. Digest of Technical Papers(p. 2310).

27. Van Elzakker, M., Van Tuijl, E., Geraedts, P., Schinkel, D.,

Klumperink, E., Nauta, B. (2010). A 10-bit charge-redistribution

ADC consuming 1.9 lW at 1 MS/s. IEEE Journal of Solid-StateCircuits, 45(5), 1007–1015.

28. Verma, N., Chandrakasan, A. (2007). An ultra low energy 12-bit

rate-resolution scalable SAR ADC for wireless sensor nodes.


29. Wang, Z. (2009). A 45 nm CMOS temperature sensing interface

for crystal frequency temperature compensation. PhD thesis,

Carnegie Mellon University.

30. Wang, Z., Lin, R., Gordon, E., Lakdawala, H., Carley, L., Jensen,

J. (2010). An in-situ temperature-sensing interface based on a

SAR ADC in 45 nm LP digital CMOS for the frequency-tem-

perature compensation of crystal oscillators. In IEEE Interna-tional Solid-State Circuits Conference Digest of TechnicalPapers (ISSCC) (pp. 316–317).

31. Zhu, Y., Chan, C., Chio, U., Sin, S., Seng-Pan, U., Martins, R.

(2010a) Parasitics nonlinearity cancellation technique for split

dac architecture by using capacitive charge-pump. In 53rd IEEEInternational Midwest Symposium on Circuits and Systems(MWSCAS) (pp. 889–892).

32. Zhu, Y., Chan, C., Chio, U., Sin, S., Seng-Pan, U., Martins, R.,

Maloberti, F. (2010b) A 10-bit 100-MSs/s reference-free SAR

ADC in 90 nm CMOS. IEEE Journal of Solid-State Circuits,45(6), 1111–1121.

33. ZMDI (2010). 12-bit, 200ksps, 8-channel, serial output ADC

datasheet. ZMDI datasheet.

Fan Hua was born in Ziyang,

Sichuan Province, P.R. China,

on December 31, 1981. She

received the B.S. degree in

communications engineering

and the M.S. degree in Com-

puter science and technology,

both from Southwest Jiaotong

University, Chengdu, China, in

2003 and 2006, respectively.

Now she is a Ph.D. student of

Huazhong Yang in NICS labo-

ratory at department of Elec-

tronic Engineering of Tsinghua

University, Beijing, China. Her

research interests include low-power, high-resolution A/D converter

designs.

Han Xue was born in Baicheng,

Jilin Province, P.R. China, on

April 19, 1988. She received

B.S. degree at Beijing Jiaotong

University in 2010. Now she is a

Ph.D. student of Huazhong

Yang and Hui Wang in NICS

laboratory at Department of

Electronic Engineering of

Tsinghua University, Beijing,

China. Her current research is

the realization and application

of high-speed SAR ADC,

focusing on asynchronous cir-

cuit and time interleaving

technique.


123

Wei Qi was born in Ningxia

province, in 1983. He received

the B.S. degree in electrical

engineering, from Northwestern

Polytechnical University, XiAn,

in 2005. He received the Ph.D.

degree from Tsinghua Univer-

sity, Beijing, in 2010. He is

currently a postdoctor in

Department of Electronic Engi-

neering of Tsinghua University.

His research interests focus on

analog IC design and high

performance data convert,

including high performance

operational amplifier, Pipeline ADC, SAR ADC, and current steer

DAC.

Yang Huazhong was born in

Ziyang, Sichuan Province,

P. R. China, on August 18, 1967.

He received B.S. degree in

micro-electronics in 1989, M.S.

and Ph.D. degree in electronic

engineering in 1993 and 1998,

respectively, all from Tsinghua

University, Beijing. In 1993, he

joined the Department of Elec-

tronic Engineering, Tsinghua

University, Beijing, where he has

been a Full Professor since 1998.

Dr. Yang was recognized as 2000

National Palmary Young

Researcher by NSFC. His research interests include chip.


123

a 12-bit self-calibrating sar adc achieving a nyquist 90.4-db sfdr

Documents