a-1 appendix a- digital logic computer architecture and...

A-1 Appendix A - Digital Logic

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring

Computer Architecture andOrganization

Miles Murdocca and Vincent Heuring

Appendix A – DigitalLogic



Chapter Contents

A.1 IntroductionA.2 Combinational LogicA.3 Truth TablesA.4 Logic GatesA.5 Properties of Boolean

AlgebraA.6 The Sum-of-Products Form

and Logic DiagramsA.7 The Product-of-Sums FormA.8 Positive vs. Negative LogicA.9 The Data SheetA.10 Digital Components

A.11 Sequential LogicA.12 Design of Finite State

MachinesA.13 Mealy vs. Moore MachinesA.14 RegistersA.15 CountersA.16 Reduction of Combinational

Logic and Sequential LogicA.17 Reduction of Two-Level

ExpressionsA.18 State Reduction



Some Definitions• Combinational logic: a digital logic circuit in which logical decisions

are made based only on combinations of the inputs. e.g. an adder.• Sequential logic: a circuit in which decisions are made based on

combinations of the current inputs as well as the past history ofinputs. e.g. a memory unit.

• Finite state machine: a circuit which has an internal state, andwhose outputs are functions of both current inputs and its internalstate. e.g. a vending machine controller.



The Combinational Logic Unit• Translates a set of inputs into a set of outputs according to one or

more mapping functions.• Inputs and outputs for a CLU normally have two distinct (binary)

values: high and low, 1 and 0, 0 and 1, or 5 V. and 0 V. for example.• The outputs of a CLU are strictly functions of the inputs, and the

outputs are updated immediately after the inputs change. A set ofinputs i0 – in are presented to the CLU, which produces a set ofoutputs according to mapping functions f0 – fm.



Truth Tables• Developed in 1854 by George Boole• further developed by Claude Shannon (Bell Labs)• Outputs are computed for all possible input combinations (how

many input combinations are there?Consider a room with two light switches. How must they work†?

†Don't show this to your electrician, or wire your house this way. This circuit definitelyviolates the electric code. The practical circuit never leaves the lines to the light "hot"when the light is turned off. Can you figure how?



Alternate Assignments of Outputs toSwitch Settings

• Logically identical truth table to the original (see previous slide), ifthe switches are configured up-side down.



Truth Tables Showing All PossibleFunctions of Two Binary Variables

• The more frequently used functions have names: AND, XOR, OR,NOR, XOR, and NAND. (Always use upper case spelling.)



Logic Gates and Their Symbols

• Note the use of the “inversion bubble.”• (Be careful about the “nose” of the gate when drawing AND vs. OR.)

Logic symbolsfor AND, OR,buffer, and NOTBooleanfunctions



Logic symbols for NAND, NOR, XOR,and XNOR Boolean functions



Variations of Basic Logic GateSymbols



The Inverter at the Transistor Level

Transistor Symbol

PowerTerminals A Transistor Used

as an InverterInverter TransferFunction



Allowable Voltages in Transistor-Transistor-Logic (TTL)

• Assignments of logical 0 and 1 to voltage ranges (left) at the output of alogic gates, (right) at the input to a logic gate.



Transistor-Level Circuits For2-Input NAND and NOR Gates



CMOS Configurations

• CMOS configurations for (a) NOT, (b) NOR, and (c) NAND gates.

• Schematic symbols for (left) n-channel transistor and (right) p-channeltransistor.



Tri-State Buffers• Outputs can be 0, 1, or “electrically disconnected.”



The Basic Properties of BooleanAlgebra

A, B, etc. areliterals; 0 and 1are constants.

Principle ofduality: The dualof a Booleanfunction is madeby replacing ANDwith OR and ORwith AND,constant 1s by 0s,and 0s by 1s



DeMorgan’s Theorem

Discuss: Applying DeMorgan’s theorem by “pushing the bubbles,”and “bubble tricks.”



NAND Gates Can Implement AND andOR Gates

Inverted inputs to a NAND gate are implemented with NAND gates.



The Sum-of-Products (SOP) Form

• Transform the function into a two-level AND-OR equation• Implement the function with an arrangement of logic gates from the

set {AND, OR, NOT}• M is true when A=0, B=1, and C=1, or when A=1, B=0, and C=1,

and so on for the remaining cases.• Represent logic equations by using the sum-of-products (SOP)

form

Truth Table for TheMajority Function



The SOP Form of the Majority Gate

• The SOP form for the 3-input majority gate is:

• M = ABC + ABC + ABC + ABC = m3 + m5 +m6 +m7 = Σ (3, 5, 6, 7)

• Each of the 2n terms are called minterms, running from 0 to 2n - 1

• Note the relationship between minterm number and boolean value.• Discuss: common-sense interpretation of equation.



A 2-Level AND-OR Circuit Implementsthe Majority Function

The encircled “T” intersections are electrically common (see next slide).



Notation Used at Circuit Intersections



A 2-Level OR-AND Circuit Implementsthe Majority Function



Positive vs. Negative Logic• Positive logic: truth, or assertion is represented by logic 1, higher voltage;falsity, de- or unassertion, logic 0, is represented by lower voltage.• Negative logic: truth, or assertion is represented by logic 0 , lowervoltage; falsity, de- or unassertion, logic 1, is represented by lower voltage



Positive and Negative Logic (Cont’d.)



Bubble Matching

• Active low signals are signified by a prime or overbar or /.• Active high: enable• Active low: enable’, enable, enable/• Ex: microwave oven control:• Active high: Heat = DoorClosed • Start• Active low: ? (hint: begin with AND gate as before.)



Bubble Matching (Cont’d.)



The DataSheet



Digital Components• High level digital circuit designs are normally made using collections

of logic gates referred to as components, rather than usingindividual logic gates. The majority function can be viewed as acomponent.

• Levels of integration (numbers of gates) in an integrated circuit (IC):• Small scale integration (SSI): 10-100 gates.• Medium scale integration (MSI): 100 to 1000 gates.• Large scale integration (LSI): 1000-10,000 logic gates.• Very large scale integration (VLSI): 10,000-upward.• These levels are approximate, but the distinctions are useful in

comparing the relative complexity of circuits.• Let us consider several useful MSI components:



The Multiplexer



Gate-Level Layout of Multiplexer



Implementing the Majority Functionwith an 8-1 Mux

Principle: Use the mux select to pick out the selected minterms of thefunction.



Efficiency: Using a 4-1 Mux toImplement the Majority Function

Principle: Use the A and B inputs to select a pair of minterms.The value applied to the MUX input is selected from {0, 1, C, C}to pick the desired behavior of the minterm pair.



The Demultiplexer (DEMUX)



The Demultiplexer is a Decoder withan Enable Input



A 2-to-4 Decoder



Using a 3-to-8 Decoder to Implementthe Majority Function



The Priority Encoder• An encoder translates a set of inputs into a binary encoding,• Can be thought of as the converse of a decoder.• A priority encoder imposes an order on the inputs.• Ai has a higher priority than Ai+1



Programmable Logic Arrays (PLAs)

• A PLA is acustomizable ANDmatrix followed by acustomizable ORmatrix:



Using a PLA to Implement the MajorityFunction



Using PLAs to Implement an Adder



A Multi-Bit Ripple-Carry Adder

PLA Realization of aFull Adder



Sequential Logic• The combinational logic circuits we have been studying so far haveno memory. The outputs always follow the inputs.

• There is a need for circuits with memory, which behave differentlydepending upon their previous state.

• An example is a vending machine, which must remember how manycoins and what kinds of coins have been inserted. The machineshould behave according to not only the current coin inserted, but alsoupon how many coins and what kinds of coins have been insertedpreviously.

• These are referred to as finite state machines, because they canhave at most a finite number of states.



Classical Model of a Finite StateMachine

• An FSM iscomposed of acombinational logicunit and delayelements (called flip-flops) in a feedbackpath, whichmaintains stateinformation.



NOR Gate with Lumped Delay

• The delay between input and output (which is lumped at the outputfor the purpose of analysis) is at the basis of the functioning of animportant memory element, the flip-flop.



S-R Flip-Flop• The S-R flip-flop is an active high (positive logic) device.



NAND Implementation of S-R Flip-Flop

• A NOR implementation of an S-R flip-flop is converted into a NANDimplementation.



A Hazard

• It is desirable to be able to “turn off” the flip-flop so it does not respondto such hazards.



A Clock Waveform: The Clock Pacesthe System

• In a positive logic system, the “action” happens when the clock ishigh, or positive. The low part of the clock cycle allows propagationbetween subcircuits, so that the signals settle at their correct valueswhen the clock next goes high.



Scientific Prefixes• For computer memory, 1K = 210 = 1024. For everything else, like clockspeeds, 1K = 1000, and likewise for 1M, 1G, etc.



Clocked S-R Flip-Flop

• The clock signal, CLK, enables the S and R inputs to the flip-flop.



Clocked D Flip-Flop

• The clocked D flip-flop, sometimes called a latch, has a potentialproblem: If D changes while the clock is high, the output will alsochange. The Master-Slave flip-flop (next slide) addresses this problem.



Master-Slave Flip-Flop

• The rising edge of the clock loads new data into the master, while theslave continues to hold previous data. The falling edge of the clockloads the new master data into the slave.



Clocked J-K Flip-Flop• The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-Rflip-flop, because Q enables J while Q’ disables K, and vice-versa.• However, there is still a problem. If J goes momentarily to 1 and thenback to 0 while the flip-flop is active and in the reset state, the flip-flop will“catch” the 1. This is referred to as “1’s catching.”• The J-K Master-Slave flip-flop (next slide) addresses this problem.



Master-Slave J-K Flip-Flop



Clocked T Flip-Flop

• The presence of a constant 1 at J and K means that the flip-flop willchange its state from 0 to 1 or 1 to 0 each time it is clocked by the T(Toggle) input.



Negative Edge-Triggered D Flip-Flop• When the clock is high,the two input latchesoutput 0, so the Mainlatch remains in itsprevious state, regardlessof changes in D.• When the clock goeshigh-to-low, values in thetwo input latches willaffect the state of theMain latch.• While the clock is low,D cannot affect the Mainlatch.



Example: Modulo-4 Counter• Counter has a clock input (CLK) and a RESET input.• Counter has two output lines, which take on values of 00, 01, 10, and 11on subsequent clock cycles.



StateTransition

Diagram forMod-4

Counter



State Table for Mod-4 Counter



State Assignment for Mod-4 Counter



Truth Table for Mod-4 Counter



Logic Design for Mod-4 Counter



Example: A Sequence Detector

• Example: Design a machine that outputs a 1 when exactly two of the lastthree inputs are 1.• e.g. input sequence of 011011100 produces an output sequence of001111010.• Assume input is a 1-bit serial line.• Use D flip-flops and 8-to-1 multiplexers.• Start by constructing a state transition diagram (next slide).



Sequence Detector State TransitionDiagram

• Design a machine thatoutputs a 1 when exactlytwo of the last three inputsare 1.



Sequence Detector State Table



Sequence Detector State Assignment



Sequence Detector Logic Diagram



Example: A Vending MachineController

• Example: Design a finite state machine for a vending machine controllerthat accepts nickels (5 cents each), dimes (10 cents each), and quarters(25 cents each). When the value of the money inserted equals or exceedstwenty cents, the machine vends the item and returns change if any, andwaits for next transaction.• Implement with a PLA and D flip-flops.



Vending Machine State TransitionDiagram



Vending Machine State Table andState Assignment



PLA Vending Machine Controller



Moore Counter• Mealy Model: Outputs are functions of Inputs and Present State.• Previous FSM designs were Mealy Machines, in which next state wascomputed from present state and inputs.• Moore Model: Outputs are functions of Present State only.



Four-Bit Register• Makes use of tri-state buffers so that multiple registers can gang theiroutputs to common output lines.



Left-Right Shift Register with ParallelRead and Write



Modulo-8 Counter• Note the use of the T flip-flops, implemented as J-K’s. They are used totoggle the input of the next flip-flop when its output is 1.



Reduction (Simplification) ofBoolean Expressions

• It is often possible to simplify the canonical SOP (or POS) forms.

• A smaller Boolean equation generally translates to a lower gate count inthe target circuit.

• We cover three methods: algebraic reduction, Karnaugh map reduction,and tabular (Quine-McCluskey) reduction.



Reduced Majority Function Circuit• Compared with the AND-OR circuit for the unreduced majority function,

the inverter for C has been eliminated, one AND gate has beeneliminated, and one AND gate has only two inputs instead of threeinputs. Can the function by reduced further? How do we go about it?



The Algebraic Method• Consider the majority function, F. We apply the algebraic method to

reduce F to its minimal two-level form:



The Algebraic Method• This majority circuit is functionally equivalent to the previous majority

circuit, but this one is in its minimal two-level form:



Karnaugh Maps: Venn DiagramRepresentation of Majority Function

• Each distinct region in the “Universe” represents a minterm.

• This diagram can be transformed into a Karnaugh Map.



K-Map for Majority Function• Place a “1” in each cell that corresponds to that minterm.

• Cells on the outer edge of the map “wrap around”



Adjacency Groupings for MajorityFunction

• F = BC + AC + AB



Minimized AND-OR MajorityCircuit

• F = BC + AC + AB

• The K-map approach yields the same minimal two-level form as thealgebraic approach.



K-Map Groupings• Minimal grouping is on the left, non-minimal (but logically equivalent) grouping

is on the right.

• To obtain minimal grouping, create smallest groups first.



K-Map Corners are LogicallyAdjacent



K-Maps and Don’t Cares• There can be more than one minimal grouping, as a result of don’t

cares.



3-Level Majority Circuit• K-Kap Reduction results in a reduced two-level circuit (that is, AND

followed by OR. Inverters are not included in the two-level count).Algebraic reduction can result in multi-level circuits with even fewerlogic gates and fewer inputs to the logic gates.



Truth Table with Don’t Cares

• A truth tablerepresentation of asingle function withdon’t cares.



Tabular (Quine-McCluskey)Reduction

• Tabular reduction beginsby grouping minterms forwhich F is nonzeroaccording to the numberof 1’s in each minterm.Don’t cares areconsidered to benonzero.

• The next step forms aconsensus (the logicalform of a cross product)between each pair ofadjacent groups for allterms that differ in onlyone variable.



Table of Choice• The prime implicants form a set that completely covers the function,

although not necessarily minimally.• A table of choice is used to obtain a minimal cover set.



Reduced Table of Choice• In a reduced table of choice, the essential prime implicants and the

minterms they cover are removed, producing the eligible set.

• F = ABC + ABC + BD + AD



Multiple Output Truth Table• The power of tabular reduction comes into play for multiple functions,

in which minterms can be shared among the functions.



Multiple Output Table of ChoiceF0(A,B,C) = ABC + BCF1(A,B,C) = AC + AC + BCF2(A,B,C) = B



Speed and PerformanceThe speed of a digital system is governed by:

the propagation delay through the logic gates, andthe propagation delay across interconnections.

We will look at characterizing the delay for a logic gate, and a methodof reducing circuit depth using function decomposition.



Propagation Delay for a NOT Gate• (Adapted from: Hamacher et. al. 2001)



MUX Decomposition



OR-Gate Decomposition• Fanin affects circuit depth.



State Reduction• Description of state machine M0 to be reduced.



Distinguishing Tree• A next state tree for M0.



Reduced State Table• A reduced state table for machine M1.



Sequence Detector StateTransition Diagram



Sequence Detector State Table



Sequence Detector Reduced StateTable



Sequence Detector StateAssignment



Sequence Detector K-Maps

• K-map reductionof next state andoutput functionsfor sequencedetector.



SequenceDetectorCircuit

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