8/2/2019 A 0529

1/11

Seminar onHyperTransport Technology

PRESENTED BY:

G.NAGARJUNA(08711A0529)

C.S.E

8/2/2019 A 0529

2/11

ABSTRACT:

It is a new I/O architecturefor personal computers, workstations, servers,embedded applications etc.

It is a scalable architecture can provide

significantly increased.bandwidth over existing bus architectures .

It simplify in-the-box connectivity

by replacing legacy buses and bridges andprogramming model is compatible with existingmodels with no changes.

8/2/2019 A 0529

3/11

INTRODUCTION

The demand for faster processors, memory andI/O is a familiar refrain in market applicationsranging from personal computers and servers tonetworking systems and from video games to

office automation equipment Once information is digitized, the speed at which

it is processed that determines the productsuccess. Faster system speed leads to faster

processing. Faster processing leads to fastersystem performance.Faster system performanceresults in greater success in the marketplace

8/2/2019 A 0529

4/11

The I/O Bandwidth Problem

While microprocessor performance continues todouble every eighteen months, the performanceof the I/O bus architecture has lagged, doublingin performance approximately every three years.

Every time processor performance doubles,latency only increases by a factor of 1.2.

8/2/2019 A 0529

5/11

The I/O Bandwidth Problem

8/2/2019 A 0529

6/11

The HyperTransport TechnologySolution

HyperTransport is intended to support in-the-box connectivity

High-speed, high-performance, point-to-point

link for interconnecting integrated circuits on aboard.

Max signaling rate of 1.6 GHz on each wire pair,a HyperTransport technology link can support a

peak aggregate bandwidth of 12.8 Gbytes/s.

8/2/2019 A 0529

7/11

Hyper Transport Design Goals

This technology wanted to develop a new I/O

protocol for in-the-box I/O connectivity that would:

1. Improve system performance

- Provide increased I/O bandwidth- Reduce power consumption

2.Simplify system design

- Reduce the number of buses within the

system3. increase I/o flexibility

providing modular bridge

8/2/2019 A 0529

8/11

HyperTransport Design Goals

3. Increase I/O flexibility- Provide modular bridgearchitecture

6. Provide highly scalable multiprocessingsystems

8/2/2019 A 0529

9/11

Flexible I/O Architecture

The physical layer defines the physical and electricalcharacteristics of the protocol. This layer interfaces tothe physical world and includes data, control, and clocklines.

The data link layer includes the initialization andconfiguration sequence, periodic Cyclic redundancycheck (CRC), disconnect/reconnect sequence,information packet for flow control and errormanagement, and double word framing for other packets

The protocol layer includes the commands, the virtualchannels in which they run, and the ordering rules thatgovern their flow.

8/2/2019 A 0529

10/11

IMPLEMENTATION

Hyper Transport technology supportsmultiple connection topologies includingdaisy chain topologies, switch topologies

and star topologies.

8/2/2019 A 0529

11/11

CONCLUSION:

Hyper Transport technology is a new high-speed, high-performance, point-to-point link forintegrated circuits.

It provides a universal connection designed toreduce the number of buses within the system,provide a high-performance link for embeddedapplications, and enable highly scalable

multiprocessing systems. Hyper Transport technology is truly the universal

solution for in-the-box connectivity.