1

A 0.2-to-1.45GHz Subsampling

Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur

Cancellation and In-Situ Timing Mismatch Detection

Somnath Kundu1, Bongjin Kim1,2, Chris H. Kim1

1Dept. of ECE, University of Minnesota, Minneapolis, MN2Rambus Inc., Sunnyvale, CA

2

Outline

• Background: PLL vs. MDLL

• Reference Spur Cancellation

• In-situ Reference Spur Detection

• 65nm Test Chip Architecture

• Measurement Results

• Conclusion

3

PLL based Clock Generation

• VCO phase noise is filtered by PLL loop

bandwidth

• Maximum PLL bandwidth is roughly fREF/10

4

Multiplying DLL (MDLL) based PLL

• VCO phases are periodically replaced by

reference phases

• Main advantage: Phase noise suppression

above the PLL bandwidth

Ref: S. Ye, et al., JSSC’2000

5

Reference Spur Issue in MDLL

• Mismatch in phase detection and reference

injection path causes reference spur

• Divider delay and phase detector (PD) fixed

offset are significant source of mismatch

PD

Multiplexed

Ring VCO

Divider

REF

OUTDIV

ΔT1

ΔT2

ΔT1: PD offset

ΔT2: Divider delay

REF

OUT

DIV

ΔT=ΔT1+ΔT2

2T

T+ΔT T-ΔT

ΔT

fOUT +fREF-fREF

spurspurOutput

Spectrum

6

Outline

• Background: PLL vs. MDLL

• Reference Spur Cancellation

• In-situ Reference Spur Detection

• 65nm Test Chip Architecture

• Measurement Results

• Conclusion

7

Reference and DCO Phase Realignment

PD

Divider

REF

OUTDIV

DTC

ΔT

REF'

• Additional reference delay in phase detection

path cancels spur

• Challenge: Delay should be adjusted and

tracked precisely

8

Reference and DCO Phase Realignment

• Phase detector for reference and DCO phase

realignment should have no inherent phase

offset

9

Zero-offset Aperture Phase Detector

• Latch based PD has ideally

zero phase offset

10

Outline

• Background: PLL vs. MDLL

• Reference Spur Cancellation

• In-situ Reference Spur Detection

• 65nm Test Chip Architecture

• Measurement Results

• Conclusion

11

Drawback in Off-chip Measurement

• Requires high frequency probes or packages,

off-chip drivers and connectors

• Each of these components introduces

inaccuracy in the measurement

12

Error Rate Calculation

D Q

CK

Prog. delay

(Tp)

CKOUT

Error Rate =Avg(TOUT)

TCK

• Error pulse generated when programmable

delay is larger than clock period

TCK1

TpTCK1

13

Error Rate Calculation

• Skew between two error rate plot is the time

period difference

TCK1

TpTCK1

TpTCK2

TCK2

ΔT

ΔT

D Q

CK

Prog. delay

(Tp)

CKOUT

Error Rate =Avg(TOUT)

TCK

14

Timing Mismatch Detection from Error Rate Calculation

• S0 selects 1st clk period, S1 selects 2nd, and so on

• Error rate is calculated for each selection

15

Timing Mismatch Detection from Error Rate Calculation

Err

or

rate

Err

or

rate

• In-situ time domain measurement of phase

mismatch in MDLL

16

Outline

• Background: PLL vs. MDLL

• Reference Spur Cancellation

• In-situ Reference Spur Detection

• 65nm Test Chip Architecture

• Measurement Results

• Conclusion

17

Proposed MDLL Architecture

OUTREF

Sel.

logic

5

Zero-

offset

APD

ʃ 10

5:1

Fractional FD

Edge

counter

Sel.

logicFRAC<1:0>

Phase locking path

INT<7:0>

5

ʃ

Frequency

locking path

Ref. injection path

D Q

CK

KFKP

KI ʃ

DLF1-bit

SSPD

In-situ time

domain

mismatch

detection

DOUT

REF

MDLL operation sequence

FLL PLLSpur

cancellationMDLL

One time operation

LDO

Spur

cancellation

circuit

ΔΣ

S0-S4

6

Spur

cancellation

18

Frequency Locking

OUTREF

Sel.

logic

5

Zero-

offset

APD

ʃ 10

5:1

Fractional FD

Edge

counter

Sel.

logicFRAC<1:0>

INT<7:0>

5

ʃ

Frequency

locking path

D Q

CK

KFKP

KI ʃ

In-situ time

domain

mismatch

detection

DOUT

REF

MDLL operation sequence

FLL PLLSpur

cancellationMDLL

LDO

ΔΣ

S0-S4

6

19

Phase Locking

OUTREF

Sel.

logic

5

Zero-

offset

APD

ʃ 10

5:1

Edge

counter

Sel.

logicFRAC<1:0>

Phase locking path

INT<7:0>

5

ʃ

D Q

CK

KFKP

KI ʃ

DLF1-bit

SSPD

In-situ time

domain

mismatch

detection

DOUT

REF

MDLL operation sequence

FLLSpur

cancellationMDLL

LDO

ΔΣ

S0-S4

6

PLL

20

Spur Cancellation

OUTREF

Sel.

logic

5

Zero-

offset

APD

ʃ 10

5:1

Edge

counter

Sel.

logicFRAC<1:0>

INT<7:0>

5

ʃ

D Q

CK

KFKP

KI ʃ

DLF1-bit

SSPD

In-situ time

domain

mismatch

detection

DOUT

REF

MDLL operation sequence

FLLSpur

cancellationMDLL

LDO

ΔΣ

S0-S4

6

PLL

21

Reference Injection

OUTREF

Sel.

logic

5

Zero-

offset

APD

ʃ 10

5:1

Edge

counter

Sel.

logicFRAC<1:0>

INT<7:0>

5

ʃ

D Q

CK

KFKP

KI ʃ

DLF1-bit

SSPD

In-situ time

domain

mismatch

detection

DOUT

REF

MDLL operation sequence

FLLSpur

cancellationMDLL

LDO

ΔΣ

S0-S4

6

PLL

Ref. injection path

22

Key Design Features

• Subsampling 1-bit phase detector for in-band

noise reduction

• Fractional-N MDLL by periodic rotation of

multiple DCO phases

• Phase mismatch cancellation loop with zero-

offset aperture phase detection

• In-situ phase mismatch detection in time

domain

23

Reference Realigned DCO

Fine<9:0>

x10240

1

0

1

0

1

Φ0

S3 S2S0

Φ3 Φ2

Distributed switched capacitor elements

x16

REF 0

1

Enable MDLL

Replica path

...

...

...

Fre

qu

en

cy (

MH

z)

• Replica path matches the

rise time of injected

reference and DCO phase

24

Outline

• Background: PLL vs. MDLL

• Reference Spur Cancellation

• In-situ Reference Spur Detection

• 65nm Test Chip Architecture

• Measurement Results

• Conclusion

25

Measured Error Rate for Mismatch

Detection

26

MDLL Fractional Spur

• Spurs at the multiple of fREF/5 are cancelled

by the cancellation circuit

27

Measured Output Spectrum and Phase Noise

Output Spectrum Phase Noise

• Input frequency 87.5MHz, output frequency

1.4175GHz

• MDLL shows 9dB lower noise than PLL at

100kHz offset

28

Performance Comparison Table

This

Work

[6]

ISSCC’15

[1]

ISSCC’14

[3]

ISSCC’12

Architecture MDLL Soft IL-PLL MDLL IL-PLL

Process 65nm 65nm 65nm 65nm

Output frequency/Range (GHz)

1.4175/(0.2 –1.45)

1.5222/(0.8 –1.7)

1.651/(1.6 – 1.9)

0.581/(0.58 – 0.611)

Ref. frequency

(MHz)87.5 380 50 32

Power (mW) 8 3 3 10.5

Intg. RMS jitter

(ps)2.8 (0.39%)

(10kHz – 10MHz)

3.6 (0.55%)(1kHz – 100MHz)

1.4 (0.23%)(30kHz – 30MHz)

8 (0.46%)(100Hz – 40MHz)

FoM * (dB) -222 -224 -232 -211

Area (mm2) 0.054 0.048 0.4 0.083

*FoM=20log(σ/1s)+10log(P/1mW)

29

Die Photo and Result Summary

PLL MDLL

Technology CMOS 65nm, 1.2V

Output frequencyInteger: 1.4GHz

Fraction: 1.4175GHz

Frequency range 0.2 –1.45 GHz

DCO type 5-stage ring oscillator

In-band PN(dBc/Hz

@100kHz)

Integer -92 -108

Fraction -87 -96

Integ. RMSjitter

(10kHz-10MHz)

Integer 8.1ps 2ps

Fraction 11.7ps 2.8ps

Power

(mW)

DCO 4.5

Total 8.0

FOM

(dB)

Integer -212.8 -225

Fraction -209 -222

AreaCore 180µm x 300µm

Total 300µm x 400µm

30

Conclusion

• Subsampling fractional-N all-digital MDLL

designed in 65nm CMOS

• Zero-offset aperture phase detector based

spur cancellation circuit is implemented for

reference and DCO phase alignment

• First in-situ detection circuit to measure the

mismatch between reference and DCO phase

in time domain

• MDLL measurement result shows 9dB lower

phase noise than PLL at 100kHz offset