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MIT Lincoln Laboratory

APS-2 Diode SimulationFirst Look

V. Suntharalingam

27 July 2007

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APS2 Tier-1 Photodiode Layout

Channel Stop (n)

p+

Graded p+

24 m

9 m 1.5 m

12 m

Pixel Layout(Showing Implants only)

Mask Layout View(Showing Metal Fill)

Metal FillPixel with contacts leading to 3D Via

Substrate is 3000 ohm-cm FZ n-type

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APS2 Tier-1 Pixel Array Layout

256 x 256 pixel array(p+ side of each diode connected

to Tier-2 SOI circuit)

Scupper Pixels

Substrate Contact (n+) Ring

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Mask Layout – Tier-1 DiodesPartial View of Pixel Array Top Left Corner

256 x 256 pixel array

4-pixel-wide inner frame, tied together as ScupperPresently biased to VRST1=VRST2

4-pixel-wide outer frame, tied together for substrate (n+) contactImplant layer shown as yellow

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Two-Dimensional Simulation – Description

• Initial questions:– At what voltage is the silicon

depleted?– What is the Electric field profile

under the wide channel stops?

• Simulation Setup:– 50-um thick silicon– 5 x 24-um pixels– Simplified doping profile

Process simulator (Athena) was run to obtain general values

– Positive bias applied to substrate and all channel stops (n-CS regions common with substrate)

– Photodiode nodes (p+) held at 0V

– No photogeneration - these are “empty well” profiles

Pixel #3

(p+)n-CS n-CS

n-3000 ohm-cm(3e12)

50 u

m D

epth

n-substrate contact

5 x 24 um Width

Caution: Aspect Ratio is severely distorted in these plots!

Doping Profiles

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Two-Dimensional Simulation of 5 PixelsPotential Contours Show Effect of Varying Substrate Bias

Vsub=0V Vsub=2V Vsub=5V

Vsub=10V Vsub=14V0V

2V

5V

10V

Vsub=14V

Pot

entia

l (V

)Potential profile at center of pixel-3 (vertical “cut-line”)

Depth into Si

“cut

-line

”

(filename error)

50

50

10

50

10

For Vsub=10V, 15V: E-field is vertical from ~25 to 50 um depth into silicon. Nearer to the frontside we observe the lateral influence of the Channel Stops

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Electric Field Vectors & Potential ProfileCenter Pixel (#3)

• Center Pixel is isolated from simulation artifacts arising from left and right boundary conditions

Vsub=10V (at backside) Vsub=15V (at backside)

10V 10V 15V 15V0V0V

Pixel #3 Pixel #3

Vertical Field Transition at ~9um (Lowest Field in CS) 24 um

18 18

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Reverse Bias of 15VSimilar to Previous Slide

Vsub=15V (at backside)

15V 15V0V

8.5 um

18

Mic

ron

s

0V0V

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Substrate Bias Influence on Vertical Profile

5V

10V

Vsub=15V

Po

ten

tia

l (V

)

Depth into Si 50

Po

ten

tia

l (V

)E

lect

ric

Fie

ld (

V/c

m)

Ele

ctri

c F

ield

(V

/cm

)

Depth into Si

5V

10V

Vsub=15V

Vertical Cut Through Pixel Center (p+) Vertical Cut Through Channel Stop

We should try testing with 15V

5V

10V

Vsub=15V

Note direction of Field

EE

E

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Substrate Bias Influence on Horizontal ProfileDepth = 9um

Po

ten

tia

l (V

)

Ele

ctri

c F

ield

(V

/cm

)

Pixel #3

5V

10V

Vsub=15V

Horizontal Cut Across Pixel #3 and Neighbors @ y=9um

Channel Stop

5V

10V

Vsub=15V

Pixel #3

Center

#2 #4

note scale