950 Theory of Operation

CPU, Timing and Control

(Refer to Figure 1) The 23.814 Mhz oscillator (Osc 1) is used to generate all timing for the terminal. It is used directly as the dot clock (Shift Clock), divided by 13 to drive the UARTs, and divided by 14 (1.701 Mhz) to.drive the CRT controller (CCLK) and the CPU (via the clock stretch circuit).

The clock stretch circuit is capable, upon command, of generating clock periods twice the normal length (588 ns versus 1175 ns) for accessing slow memory or peripheral devices. Its output drives the 10 input of the 6502 CPU. The CPU then outputs 12, which controls the timing of the CPU bus. 12 is a slightly delayed ver.sion of 10 •

The result of these circuits are 12 and CCLK, two signals of identical frequency but opposite phase, (except during clock stretched cycles). The importance of this will be made clear later in our discussion of the display controller.

The CPU fetches its program from the ROMs (Read Only Memory) A41-43. It uses the 6522 (A54) to sense switches Sl and S2 and to generate control signals for the test of the terminal.

Display Controller

(Refer to Figure 2) Timer T2, part of the 6522, and the 6545 (A55) are used to generate the memory address, in Display RAM, of each character as it is about to be displayed, and the horizontal and vertical synchronization pulses necessary to con­trol the deflection circuits of the monitor.

Timer T2 is used to count horizontal scan lines and interrupt the processor (via NMI) when a specified number of scans has occurred. The processor then loads the memory address of the next data row into the CRT Controller and "sets" this address by generating a carefully-timed reset to the 6545.

At this same time the processor loads a 4 bit value into latch, A61. At the time of the CRT reset this value is transferred to counter A60 and becomes the Row Address of the next data row. This value is then incremented by each horizontal sync pulse until the start of the next data row when it is again preset to a value determined by the CPU.

The CPU and the display controller share access to the System and Display RAM (Random Access Memory). This is done during alternate phases of the 12 clock. During the positive portion of 12 the CPU address may be gated onto the RAM address bus by Multiplexers A43-46, and bidirectional transceiver A14 is enabled to pass data between the CPU data bus and the RAM data bus.

During the negative portion of 12 the 6545 address bus is gated onto the RAM address bus allowing the video data to be latched by A24 and held for the display generator.

This alternating access or "interleaved" access allows the processor to operate at normal-speed, without wai't_s of any kind, yet prevents degradation of the display quality that could be caused by inadvertant appropriation of the display bus by the processor to access data.

The only penalty for this scheme is the necessity for fast RAM (150 ns or faster).

Video Generation

(Refer to Figure 3) This Display Data and the Row Address (or scan address) are used to obtain the dots for the next character to be displayed from the character generator ROMs A32 and A33.

These dots are then fed in parallel to shift registers A22 and A23 and emerge serially as raw video.

Additionally, bits 0-3 of Display data and bit 7 of A33 are combined to generate the attribute signals Underline, Blink, Blank, and Reverse. ICs A19, 20, 21 and 30 latdhand delay the decoded attributes from the previous data row for carry-over into the next.

Bit 6 of A33 controls the intensity of the character to be displayed. ~

Gates AI, 2, 10 and 11 are used to modify the raw video to the proper intensity and polarity, and gate it on or off in response to the attribute signals and control signals BOW (used to reverse the entire display), cursor, BLI-RATE (used to blink the video) and FORCE BLANK (used to blank the entire screen).

Transistor Ql is used to dr.ive the video to the proper voltage and current levels to drive the video module and/or an external mon.itor (using the composite video jumpers) .

I/O Circuits

(Refer to Figure 4) UART A49 is used to receive (and optionally transmit) serial data from (and to) the keyboard. The transmit path to the keyboard is normally used to conduct the bell tone from the 6522 (via driver Q4) to the speaker in the keybo~rd.

UARTs A50 (Main Port, P3) and A5l (Printer Port, P4) are used to send and receive ser ial data from P·3 and P4 via the dr ivers, receivers and switching circuits A39, 40, 47, 48, 56, 57, 58 and 59.

The UARTs A49, 50 and A5l (655ls) are connected to the CPU Bus and generate IRQ interrrupts when commanded by the CPU to send or receive data. Additionally these parts contain internal baud (" . rate generators that must be programmed by the CPU to control the baud rates.

General Debugging Guidelines

The following procedures are usually 90ne when there is no initial beep at turn on. To debug any microprocessor with­out an emulator, remove as mahy devices as possible from the bus •. This includes the CPU, CRT controller, VIA, UARTs, and Program, User, and Character Generator ROMs. The address and data lines can then be checked for proper operation.

Field component failures will generally be the most complicated integrated circuits. In case of a failure of this type, first replace any of the socketed components associated with the failure symptoms. Should the problem persist, check the RAM, RS232 components, bus transceiver, and multiplexers. This failure group is the most difficult to troubleshoot. An effective way to check the RAM is to use a test wire with two clips. Connect one end to the R4/Dl junction in the video section of the logic and the other end touching the outputs of the RAM. This, in essence, uses the monitor as a scope. Compare the response on the screen with a good terminal, and using this method, a faulty terminal can be debugged quickly. Should the problem not be found in the second f~jlure group, a simple hard failure in any area could be the cause of the problem. .

1/26/81

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DOCUMENT NO. 29000 039 REV. 3, FEBRUARY 1979

PART NUMBER R650X and R651X

'1' Rockwell R6500 Microcomputer System

DATA SHEET

R6500 MICROPROCESSORS (CPU's)

SYSTEM ABSTRACT

The S-bit R6500 microcomputer system is produced with N­Channel, Silicon Gate technology. Its performance speeds are enhanced by advanced system architecture. This innovative architecture results in smaller chips - the semiconductor threshold to cost-effectivity. System cost-effectivity is further enhanced by providing a family of 10 software-compatible microprocessor (CPU) devices, described in this document. Rockwell also pro­vides memory and microcomputer system ... as well as low-cost design aids and documentation.

R6500 MICROPROCESSOR (CPU) CONCEPT Ten CPU devices are available. All are software-compatible. They provide options of addressable memory, interrupt input, on-chip clock oscillators and drivers. All are -b'us-compatible with earlier generation microprocessors like the M6S00 devices.

The family includes six microprocessors with on-board clock oscillators and drivers and four microprocessors driven by external clocks. The on-chip clock versions are aimed at high performance, low cost applications where single phase inputs, crystal or RC inputs provide the time base. The external clock versions are geared for multiprocessor system applications where maximum timing control is mandatory. All R6500 microprocessors are also available in a variety of packaging (ceramic and plastic), operating frequency (1 MHz and 2 MHz) and temperature (com­mercial, industrial and military) versions.

MEMBERS OF THE R6500 MICROPROCESSOR (CPU) FAMILY Microprocessors with On-Chip Clock Oscillator

Model

R6502 R6503 R6504 R6505 R6506 R6507

Addressable Memory

65K Bytes 41< Bytes SK Bytes 4K Bytes 4K Bytes SK Bytes

Microprocessors with External Two Phase Clock Output

Model

R6512 R6513 R6514 R6515

Addressable Memory

65K Bytes 4K Bytes SK Bytes 4K Bytes

@ Rockwell International Corporation 1979 All Rights Reserved Printed in U.S.A.

FEATURES

• Single +5V supply • N channel, silicon gate, depletion load technology • Eight bit parallel processing • 56 InstrUctions • Decimal and binary arithmetic • Thirteen addressing modes • True indexing capability • Programmable stack pointer • Variable length stack • Interrupt capabil ity • Non-maskable interrupt • Use with any type of speed memory • S-bit Bidirectional Data Bus • Addressable memory range of up to 65K bytes

• "Ready" input • Direct Memory Access capability • Bus compatible with M6S00 • 1 MHz and 2 MHz operation • Choice of external or on-chip clocks • On·the-chip clock options

External single clock input - RC time base input - Crystal time base input

• Commercial, industrial and military temperature versions

• Pi'peline architecture

Ordering Information

Order Number: R65XX __ _

lTemperature Range: No suffix = OOC to +700 C

E = -40oC to +S50 C (I ndustriall

MT = -550 C to +1250 C (Military)

Package:

M = MIL.sTD~3, Class B

C = Ceramic; P = Pla~ (Not AVaible for M 'or MT suffix)

Ff'8t/uency Range: No suffix = 1 MHz

A = 2 MHz Model Designator:

XX = 02,03,04, ... 15 NOTE: Contact your local Rockwell Representative

concerning availability.

SpeclflCiition. tubJect to change without notice

R6600 Signal Description

Clocks (411, 41 2)

The R651X requires a two phase non-overhipping clock that runs at the V CC voltage level.

The R650X clocks are suPPlied with ali internal clock generator. The frequency of these clocks is externally controlled.

Add,.. BUI (AO...A15)

These outputs are TTL compatible. capable of driving one standard TTL load and 130 pF.

Data BUI (00·1)7)

Eight pins are used for the data bus. This is a bidirectional bus. transferring data to and from the device end peripherals. The out· puts are trioState buffers capable of driving one standard TTL load and 130pF.

Data BUI Enable (DBEt

This TTL compatible input allows external control of the trioState data output buffers and will enable the microprocessor bus driver when in the high state. In normal operation DBE would be driven by the phase ~ (41 2) clock. thus allowing data output from microprocessor only during 41 • During the read cycle. the data bus drivers are internally disa~ed. becoming .essentially an. open circuit. To disable data bus drivers externally.DBE should be held low.

Ready (ROY)

This input signal allows the user to halt or single cycle the micro­processor on all cycles except write cycles. A negative transition

• to the low state during or coincident with phase one (41,) will halt the microprocessor with the output address lines reflecting the current address being fetChed. If Ready is low during a write cycle, it is ignored until the foUowing read operation. This con­dition will remain through a subsequent phase two (412) in which the Ready signal is low. This feature allows microprocessor inter· facing with the low speed PROMs as well as fast (max. 2 cycle) Direct Memory Access (DMA).

Interrupt Request IIRQ)

This TTL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor will complete the current instruction being executed before recognizing the request. At that time, the interrupt mask bit in the Status Code Register will be examined. If the interrupt mask flag is not set, the micro­processor will begin an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The micro· processor will then set the interrupt mask flag high so that no fur· ther interrupts may occur. At the end of this cycle, the program counter low will be loaded from address FFFE, and program counter high from location FFFF. therefore transferring program control to the memory vector located at these addresses. The RDY signal must be in the high state for any interrupt to be rec· ognized. A 3KO external resistor should be used for proper wire-OR operation.

Non-Maskable Interrupt (liI1l1l.

A negative going edge on this input requests that a non-rnaskable interrupt sequence be generated within the microprocessor.

IiiMi is an unconditional interrupt. Following completion of the current instruction, the sequence of operations defined for i'fiQ . will be performed, regardless of the state interrupt mask flag. The vector address loaded into the progrlilm counter, low and high, are locations fFFA and FFFB respectively, thereby transferring pro· gram·.control to the memory vector located at these addresses. The instructions loaded at these locetions cause the microproc· essor to branch to a non-rnaskable interrupt routine in memory.

NMI 'also requires an external 3K n regis.ter tc:> V CC for proper wire·OR operations.

Inputs iRO and NMI are hardware interrupts,lines that are sam. pled during 412 (phase 2) and will begin the eppropriate interrupt routine on the 41, (phase ,) following the completion of the cur· rent instruction.

Set 0vrrflow Flag (5.0.)

A neg~tive going edge on this input sets the overflow bit in the Status Code Register. This Signal is sampled on the trailing edge of 411 and must be externally synchronized.

SYNC

This output line is provided to identify those cycles in which the microprocessor is doing an OPCODE fetch. The SYNC line goes high during 41, of an OP CODE fetch and stays high for the remainder of that cycle. If the RDY line is pulled low during the 41, clock pulse in which SYNC went high, the processor will stop in its current state and will remain. in the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to cause Single instruction execution.

Reset

This input is used to reset or start the microprocessor from a power down condition. During the time that this line is held low, writing to or from the microprocessor is inhibited. When a posi· tive edge is detected on the input. the microprocessor will imme· diately begin the reset sequence.

After a system initialization time of six clock'cycles, the mask interrupt flag will be set and the microprocessor will load the pro· gram counter from the memory vector locations FFFC and FFFD. This is the start location for program control.

After V CC reaches 4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the R/W and (SYNC) signal will become valid.,

When the reset signal goes high following these two clock cycles. the microprocessor will proceed with the normal reset procedure detailed above.

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ADDRESSING MODES

ACCUMULATOR ADDRESSING - This fonn of addressing is represented with a one byte instruction, implying an operation on the accumulator.

IMMEDIATE ADDRESSING - In immediate addressing, the operand is contained in the second byte of the inStruction, with no further memory addressing required.

ABSOLUTE ADDRESSING - In absolute addressing, ~econd byte of the instruction specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 65K bytes of addressable memory.

ZERO PAGE ADDRESSING - The zero page instructions allow for shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. Careful use of the zero page can result in significant increase in code efficiency.

INDEXED ZERO PAGE ADDRESSING - (X, V indexing) - This form of addressing is used in conjunction with the index register and is referred to as "Zero Page, X" or "Zero Page, V". The effec­tive address is calculated by adding the second byte to the con­tents of the index register. Since this is a fonn of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally due to the "Zero Page" addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur.

INDEXED ABSOLUTE ADDRESSING - (X, V indexing) - This form of addressing is used in conjunction with X and V index reg­ister and is referred to as "Absolute, X", and "Absolute, V". The effective address is formed by adding the contents of X or V to the address contained in the second and third bytes of the instruc­tion. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

IMPLIED ADDRESSING - In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction.

RELATIVE ADDRESSING - Relative addressing is used only with branch instructions and establishes a destination for the con­ditional branch.

The second byte of the instruction becomes the operand which is an "Offset"added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is -128 to + 127 bytes from tha next instruction.

INDEXED INDIRECT ADDRESSING - In indexed indirect addressing (referred to as (Indirect, Xl), the second byte of the instruction is added to the contents of the X index register, dis­carding the carry. The result of this addition points to a memory location on page zero whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero.

INDIRECT INDEXED ADDRESSING - In indirect .indexed addressing (referred to as (Indirect!, V), the second byte of the instruction points to a memory location in page zero. The con­tents of this memory location is added to the contents of the V index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents. of the next page zero memory location, the result being the high order eight bits of the effective address.

ABSOLUTE INDIRECT - The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location is contained in tha third byte of the instruction. The contents of tha fully specified mem­ory location is the low order byte of the effective address. The next memory location contains the high order byte of the effec­tive address which is loaded into the sixteen bits of the program counter.

INSTRUCTION SET - ALPHABETIC SEQUENCE

ADC Add Memory to Accumulator with Carry JMP Jump to New location AND "AND" Memory with Accumulator JSR Jump to New location Saving Return Address ASl Shift left One Bit (Memory or Accumulator)

lOA load Accumulator with Memory

BCC Branch on Carry Clear lOX load Index X with Memory

BCS Branch on Carry Set lDV load Index V with Memory

BEQ Branch on Result Zero lSR Shift One Bit Right (Memory or Accumulator!

BIT Test Bits in Memory with Accumulator NOP No Operation BMI Branch on Result Minus BNE Branch on Result not Zero ORA "OR" Memory with Accumulator

BPl Branch on Result Plus PHA Push Accumulator on Stack BRK Force Break PHP Push Processor Status on Stack BVC Branch on Overflow Clear PlA Pull Accumulator from Stack BVS Branch on Overflow Set PlP Pull Processor Status from Stack

ClC Clear Carry Flag ROL Rotate One Bit Left (Memory or Accumulator)

ClD Clear Decimal Mode ROR Rotate One Bit Right (Memory or Accumulator)

Cli Clear Interrupt Disable Bit RTI Return from Interrupt

ClV Clear Overflow Flag RTS Return from Subroutine

CMP Compare Memory and Accumulator SBC Subtract Memory from Accumulator with Borrow CPX Compare Memory and Index X SEC Set Carry Flag CPV Compare Memory and Index V SED Set Decimal Mode

SEI Set Interrupt Disable Status

DEC Decrement Memory by One STA Store Accumulator in Memory STX Store Index X in Memory

DEX Decrement I ndex X by One STY Store Index V in Memory

DEV Decrement Index V by One TAX Transfer Accumulator to Index X

EOR "Exclusive-or" Memory with Accumulator TAV Transfer Accumulator to Index V TSX Transfer Stack Pointer to Index X

INC Increment Memory by One TXA Transfer Index X to Accumulator INX Increment Index X by One TXS Transfer Index X to Stack Register INV Increment Index V by One TVA Transfer Index V to Accumulator

VSS

ROY

<Pl (OUT)

IRO

N.C. NMi SYNC VCC AO

Al

A2

A3

A4

A5 A6 A7

AS A9

Al0

All

RES

<P2(OUT)

S.O.

<PO(IN)

N.C. N.C. R/Vi DO

01

02

03

04 05

06

07

A15

A14

A13

A12

VSS

R6502 - 40 Pin Package

Features of R6502 (, • 65K Addressable Bytes of Memory (AO.A15) • IRQ Interrupt • On.the-chip Clock

TTL Level Single Phase Input RC Time Base Input . Crystal Time Base Input

• SYNC Signal (can be used for single instruction execution)

• ROY Signal (can be used to halt or single cycle execution)

• Two Phase Output Clock for Timing of Support Chips • NMI Interrupt

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INSTRUCTION SET

INSTRUCTIONS IMMEDIATE ABSOLUTE lERO PAGE ACCUM IMPlIEO (IND. XI (lNDI. y l. PAGE, X "IS. X "'IS. y RElATIvE INOUI£CT Z PAGE, Y "'OC£S$O" STATUS CODES

MNEMONIC OPERATION OP n • OP n • OP n • OF n • OP n • OP n • OP n • OP n • OP n • OF • OP • OP n • OP n 6 5 • 3 2 1 0 MNEMONIC n n • N V B 0 , Z C

AOC A+M+C::;-A (4) (1) 69 2 2 60 4 3 65 3 2 61 6 2 71 5 2 75 4 2 70 4 3 79 • 3 N V Z C AoC

AND AI\M-A 111 29 2 2 20 • 3 25 3 2 21 6 2 3,. 5 2 35 • 2 3D 4 3 39 • 3 N. Z AND

A S L C -u::==.:::QJ - a OE 6 3 06 5 2 OA 2 1 16 6 2 IE 7 3 N. Z C AS L

BCC BRANCH ON C = 0 121 90 2 2 BCC

BCS BRANCH ON C = 1 121 BO 2 2 BCS

BED BRANCH ON Z = 1 121 FO 2 2 .. BEQ B , T AAM 2C 4 3 24 3 2 11.1 1 11.16 • Z B , T

B M , BRANCH ON N = 1 (21 30 2 2 B M ,

B N E BRANCH ON Z = 0 121 00 2 2 B N E

B P L BRANCH ON N = 0 121 1() 2 2 B P L

B R K BREAK 00 7 1 •• 1 1 BAK

BVC BRANCH ON V = 0 (2) 50 2 2 BvC

B V S BRANCH ON V = 1 121 70 2 2 B V 5

CLC O-C 18 2 1 0 CLC

C L 0 0-0 DB 2 1 0 C L 0

C L I 0-' 58 2 1 0 C L ,

C L V O-V B8 2 1 0 C L V

CMP A-M C9 2 2 CD 4 3 C5 3 2 Cl 6 2 01 5 2 05 • 2 DO 4 3 09 • 3 N • Z C CMP

CPX X-M EO 2 2 EC • 3 E' 3 2 N • Z C CPX

CPY Y M CO 2 2 CC • 3 C4 3 2 N Z C C P Y

DEC M - 1-11.1 CE 6 3 C6 5 2 06 6 2 DE 7 3 N Z DEC

oEX X - 1- X CA 2 1 N Z DE X

DEY V-I - Y 8B 2 1 N Z DEY

EO A A'tIM-A 11) 49 2 2 .0 • 3 45 3 2 41 6 2 51 5 2 55 • 2 51) • 3 59 • 3 N Z EOA

, N C M + 1-11.1 EE 6 3 E6 5 2 F6 6 2 FE 7 3 N Z • , N C

I N X X + ,-x E8 2 1 N • Z • I N X

, N Y Y + 1 - Y C8 2 1 N • Z • , N Y

J M P JUMP TO NEW LOC 4C 3 3 6C 5 3 J M P

J 5 A JUMP$UB 20 6 3 J S R

LOA M-A 111 A9 2 2 AD • 3 A5 3 2 Al 6 2 Bl 5 2 B5 4 2 BO 4 3 B9 4 3 ~ . z • LOA

LOX M-x (1) A2 2 2 AE 4 3 A6 3 2 .BE 4 3 B6 4 2 N • Z • LOX

LOY M-Y 111 AO 2 2 AC 4 3 A. 3 2 B. • 2 BC '. 3 N • Z • LOY

L S R o -a::::==:Q}- C 4E 6 3 '6 5 2 'A 2 1 56 6 2 5E 7 3 o • z C L S A

NOP NOPPERATION EA 2 1 NOP

ORA AVM-A 09 2 2 00 4 3 05 3 2 01 6 2 11 5 2 15 4 2 10 • 3 19 • " N • Z • ORA

PH A A-Ms 5 - 1-5 48 3 1 .. PH A

PH P p- Ms S - 1- S 08 3 1 e H P

P L A S + ,-5 Ms-A 68 4 1 N • Z • P L A

P L P S + 1-5 Ms- P 28 4 1 (RESTORED) P L P

AD L [~-{9:J 2E 6 3 26 5 2 2A 2 1 ~6 6 2 3E 7 3 N • Z C ROL

A 0 A L[9-c==!P 6E 6 3 66 5 2 6A 2 1 76 6 2 7E 7 3 N • Z C AOA

AT' AlAN INT '0 6 1 (RESTORED) R T I

A T S RlAN SUB 60 6 1 A T S

S B C A-M-C-A (11 E9 2 2 ED 4 3 E5 3 2 El 6 2 Fl 5' 2 F5 4 2 FD • 3 F9 • 3 N V Z (3) SBC

SEC l-C 3B 2 1 1 SEC

SED 1-0 F8 2 1 1 5 E 0

S E , 1-' 78 2 1 1 S E ,

S T A A-M 80 • 3 85 3 2 91 6 2 91 6 2 95 • 2 90 5 3 99 5 3 S T A

S T X X-M 8E • 3 86 3 2 96 • 2 S T X

STY Y-M 8C • 3 8' 3 2 9' 4 2 STY

T A X A-X AA 2 1 N • Z T A X

T A Y A-Y A8 2 1 N Z T A Y

T S X S-X BA 2 1 N Z T S X

T X A X-A 8A 2 1 N Z T X A

T X S x-s 9A 2 1 T X S

T Y A V-A 98 2 1 N l T Y A

," ADO 1 to '·N·· IF PAGE BOUNDARY IS CROSSED X INDEX X + ADD M .. MEMORY BIT 7 ,2, ADO 1 TO .. N"" IF BRANCH OCCURS TO SAME PAGE Y INDEX Y - SUBTRACT M, MEMORY BIT6 ADD 2 TO .. N"" IF BRANCH OCCURS TO DIFFERENT PAGE

,31 CARRY NOT;:: BORROW A ACCUMULATOR A AND n NO. CYCLES

)4, IF IN DECIMAL MODE. Z FLAG IS INVALID M MEMORY PER EFFECTIVE ADDRESS V OR • NO. BYTES

ACCUMULATOR MUST BE CHECKED FOR ZERO RESUl T Ms MEMORY PER 5T ACK POINTER Y EXCLUSIVE OR

Clock Timing - R6502, 03, 04, 05, 06, 07 Timing for Reading Data from Memory or Peripherals

-j rTFI/>O .0 UN) 1.5V

O.4V - - j~-PW-H-.-:---:'-:'-:':'~+--~ OL

O.4V

1/11 (OUT) ----t=~:.I~---------..J/ Rm

ADDRESS FROM CPU

15

O'4V~1 1.5V . L I--PWHI/I2-1

, . REF "B" ~f O.4V

CREF "A"

Clock Timing - R6512, 13, 14, 15

,REF "A"

~l·~------TCYC------~~

DATAFROM __ -i ___ +-__ -r_~~ MEMORY

ROY, 5.0.

SYNC

Timing for Writing Data to Memory or Peripherals

Rm

ADDRESS FROM CPU

DATAFROM __ ~-------r--c~ CPU

REF "B"

Note: "REF," means Reference Points on clocks.

PROGRAMMING MODEL

7 o 7 o I A '--______ .... 1 ACCUMULATOR A I NIVI IB lOll I ZIClpROCESSOR STATUS REG 'P" 7 o 1 .y

7

~ __ ...;... ___ ~IINDEX REGISTER Y o 1 = TRUE

1 X ,--_______ .... 1 INDEX REGISTER X ZERO 1 = RESULT ZERO

7 o I PCH I PCl

8 7

~CARRY

IRQ DISABLE 1 = DISABLE ,--_~...;;.;.. __ -=-~ __ ~;.;;;... __ ~I PROGRAM COUNTER "PC" o

11 I S 1...-'--_______ -'1 STACK POINTER "s" '-----DECiMAL MODE 1 = TRUE

'------BRK COMMAND. 1= BRK

L--------OVERFlOW 1 = TRUE

L.--_______ NEGATIVE 1 = NEG.

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ADDRESS

BUS

+- REGISTER SECTION CONTROL SECTION ---t.~

AD

r- +t~ .-r--- - INDEX

~ INTERRUPT REGISTER

LOGIC Y

Al ..-A2 ..- INDEX

~ REGISTER '--X

A3 .... ABL

A4 .- ..J STACK t? r- ~~ POINT

..J REGISTER

« IS) A5 .... z

a: w INSTRUCTION I-Z DECODE

A6 .- -~ ~

A7

ALU

~ .... ~ AB

A9

.-r--- :I: 0 ....-- I+-« ACCUMULATOR TIMING ..J Ii. ~ I+- CONTROL « I+-z

+- a: w .--l-

t+--~ ·A1D +- ~

q,1 PCL

~ q,2

All

A12

+- PCH ~ ~ H PROCESSOR I ABH L-< STATUS CLOCK

'" REGISTER GENERATOR ... P

~ INPUT

L. DATA

~ ' ... LATCH IDLI ,I

I+-DATA BUS r: INSTRUCTION

..... - BUFFER REGISTER

'- -

A13

A14

A15

t t t, ~

DO

LEGEND:

11' : 8 BIT LINE

I : 1 BIT LINE

Note: 1. Clock Generator is not included on R6512. 13, 14, 15

2. AddreSSing Capability and control options vary with each

of the R6500 Products.

R6500 Internal Architecture

1 Dl

D2

D3 DATA

D4 BUS

D5

D6

D7

RDY

q,I0NI

) R6512, 13, 14, 15

q,2 0NI

</lOON) R6502, 03, 04, 05, 06, 07

q,1 0UT

q,2 0UT

RIW

DBE

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ROCKWELL INTERNATIONAL - MICROELECTRONIC DEVICES

REGIONAL SALES OFFICES YOUR LOCAL REPRESENTATIVE

SOUTHWEST REGION, U.S.A.- CENTRAL REGION, U.S.A. EUROPE

3310 Miraloma Avenue Contact Robert O. Whitesell & Associates Rockwell Inlernalional GmbH P.O. Box 3669 6691 East Washington Street Microelectronic Devices Anaheim. California 92803 Indianapolis. Indiana 46219 Fraunhoferstrasse 11 (714) 632·0950 (317) 359·9283 0·8033 Munchen·Marlinsried TWX: 910·591·1698 Attn: Milt Gamble. Mgr. (Acting) Germany

TWX: 810·341·3320 (089) 859·9575 NORTHWEST REGION, U. S. A. Telex: 052112650 Rockwell Internatlon,al EASTERN REGION, U.S.A.-1601 Civic Center Drive. Suite 203 Carolier Office Building Santa Clara, CA 95050 850·870 U.S. Route 1 4081984·6070 North Brunswick. New Jersey 08902 FAR EAST Telex: 171135 miSSion snta (201) 246·3630

Rockwell International Overseas Corp. TWX: 7104806261 RECTC NBR Itohpia Hirakawa-cho Bldg. 7·6 Hirakawa-cho 2-chome '1' Rockwell

MIDWEST REGION, U.S.A. Chiyoda·ku. Japan

1011 E. Touhy Avenue, Suite 245 (03) 265·8806 International Des Plaines. Illinois 60018 Telex: J22198

(312) 297·8862 * Also Applications Cenlers Telex: 726353 Rockwell 6-79

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DuCUMENT NO. 29000 047 REVISION 1, OCT. 1978

PART NUMBER R6522

R6500 Microcomputer System

DATA SHEET

VERSATILE INTERFACE ADAPTER (VIA) SYSTEM ABSTRACT The 8-bit R6500 microcomputer system is produced with N­

channel, silicon-gate, depletion-load technology. Its perform­ance speeds are enhanced by advanced system architecture.

Its innovative architecture results in smaller chips - the semi­

conductor threshold to cost-effectivity. System cost-effectivity

is further enhanced by providing a family of 10 software-{;om­

patible microprocessor (CPU) devices, memory and I/O devices ...

as well as low-{;ost design aids and docume~1tation.

DESCRIPTION The R6522 VIA adds two powerful, flexible Interval Timers, a serial-to-parallel/parallel-to-serial shift register and input latch­

ing on the peripheral ports to the capabi I ities of the R6520

Peripheral Interfac~ Adapter (PIA) device. Handshaking capa­bility is expanded to allow control of bidirectional data trans­fers between V lAs in multiple processor systems and between peripherals.

Control of peripherals is primarily through two 8-bit bidirectional

ports. Each of these ports can be programmed to act as an input

or an output. Peripheral I/O lines can be selectively controlled

by the Interval Timers to generate programmable-frequency square

waves and/or to count externally generated pulses. Positive con­

trol of V IA functions is gained through its internal register organi­

zation: Interrupt Flag Register, Interrupt Enable Register, and

two Function Control Registers.

Ordering Information

Order Package Temperature Number Type Frequency Range

R6522P Plastic 1 MHz OoC to +700C R6522AP Plastic 2 MHz OoC to +700C R6522C Ceramic 1 MHz OoC to +700C R6522AC Ceramic 2 MHz OoC to +700C R6522PE Plastic 1 MHz AOoC to +850C R6522APE Plastic 2 MHz AOoC to +850C R6522CE Ceram c 1 MHz AOoC to +850C R6522ACE Ceram c 2 MHz AOoC to +850~ R6522CMT Ceram c 1 MHz -55°C to +125 C

SBIT CONTROL DATA BUS

TO R/W

R6500 112 CLOCK SBIT TO R6522 DATA PORT PERIPHERALS

CPU REGISTER AND CHIP SELECT S

IRQ CONTROL

FEATURES • Organized for simplified software control of many functions

• Compatible with the R650X and R6S1 X family of micro­processors (CPUs)

• Bi-directional, 8-bit data bus for communication with micro­processor

• Two Bi-directional, 8-bit input/output ports for interface with peripheral devices

• CMOS and TTL compatible input/output peripheral ports

• Data Direction Registers allow each peripheral pin to act as

either an input or an output

• Interrupt Flag Register allows the microprocessor to readily determine the source of an interrupt and provides convenient

control of the interrupts within the chip

• Handshake control logic for input/output peripheral data

transfer operations

• Data latching on peripheral input/output ports

• Two fully-programmable interval timers/counters

• Eight-bit Shift Register for serial interface

• Forty-pin plastic or ceramic DIP package.

VSS CAl PAO CA2 PAl RSO PA2 RSl PA3 RS2 PA4 RS3

PA5 REs PA6 DO

PA7 Dl

PBO D2

PBl D3

PB2 D4

PB3 D5

PB4 D6

PB5 D7

PB6 ¢2 PB7 CSl

CB1 Cs2 CB2 R/W VCC iRQ

Pin Configuration Basic R6522 Interface Diagram ,=.-~~~,-~ .. =-"~.",-~~.,".,-."------------,,,

CD Rockwell International Corporation 1978 All Rights Reserved Printed in U.S.A.

Specifications subject to change without notice

:rJ 0) (J1 N N

< m :rJ en l> -I -.­m -2 -I m :rJ '"T1 l> n m l> C l>

" -I m :rJ -< -l> -

OPERATION SUMMARY Register Select Lines I RSO, RS1, RS2, RS31

The four Register select lines are nCfmally connected to the processor address bus lines to allow the processor to select the internal R6522 register which is to be accessed. The sixteen possible combinations access the registers as follows:

RS3 RS2 RS1 RSO Register Remarks RS3 RS2 RS1 RSO Register Remarks

L L L L ORB H L L L T2L-L Write Latch

L L L H ORA Controls Handshake T2C-L Read Counter

L L H L DDRB H L L H T2C-H Triggers T2L-L/T2C-L

Transfer L L H H DORA

H L H SR

L H L L T1L-L Write Latch H L H H ACR T1C-L Read Counter H H L L PCR

L H L H T1C-H Trigger T1 L·UT1 Col H H L H IFR Transfer

H H H L IER L H H L T1L-L

H H H H ORA No Effect on L H H H T1 L-H Handshake

Note: L = O.4V DC, H = 2.4V DC.

Timer 2 Control

RS3 RS2 RS1 RSO R/W= L R/W=H

H L L L Write T2L-L Read T2C-L Clear I nterrupt flag

H L L H Write T2C-H Read T2C-H Transfer T2L-L to T2C-L Clear I nterrupt flag

Writing the Timer 1 Register

The operations which take place when writing to each of the four T1 addresses are as follows:

RS3 RS2 RS1 RSO Operation IR/W = LI

L H L L Write into low order latch

Write into high order latch

L H L H Write into high order counter Transfer low order latch into low order counter Reset T1 interrupt flag

L H H l Write low order latch

X H H H Write high order latch Reset T1 interrupt flag

Reading the Timer 1 Registers

For reading the Timer 1 registers, the four addresses relate directly to the four registers as follows:

RS3 RS2 RS1 RSO Operation IR/W = HI

l H L l Read T1 low order counter Reset T1 interrupt flag

L H l H Read T1 high order counter

L H H l Read T1 low order latch

L H H H Read T1 high order latch

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TIMING CHARACTERISTICS

Read Timing Characteristics (loading 130 pF and one TTL load)

Parameter

Delay time, address valid to clock positive transition

Delay time, clock positive transition to data valid on bus

Peripheral data setup time

Data bus hold time

Rise and fall time for clock input

PHASE TWO CLOCK

Symbol Min Typ

T ACR 180 -

TCDR - -

TpCR 300 -

THR 10 -

T RC - -TRF

Jr-t---t---t---=:..::..-------- 2.4V ADDRESS

-----,-:! .,,----+--t--+-----------O.4V

PERIPHERAL DATA

Jr-..:..;::=---.:.--t--+----------2.4V

T O.4V 1.-__ ,,1_ - _H.!I_ - - - - - - -2.4V

DATA BUS r--"""';1f-- -- - - --O.4V

Read Timing Characteristics

Write Timing Characteristics

Parameter

Enable pulse width

Delay time, address valid to clock positive transition

Delay time, data valid to clock negative transition

Delay time, read/write negative transition to clock positive transition

Data bus hold time

Delay time, Enable negative transition to peripheral data valid

Delay time, clock negative transition to peripheral data valid CMOS (VCC - 30%)

PHASE TWO CLOCK

ADDRESS

Symbol

TC

T ACW

T DCW

TWCW

THW

TCpW

T CMOS

Min Typ

0.47 -

180 -

300 -

180 -

10 -

- -

- -

,.--------2.4V

--::;:o-J ~==::r---1::::"'..4:r,:;;~----O.4V rt-......::C::.:M~O::.:S'--____ 2.4V

READ/WRITE

DATA BUS

PERIPHERAL DATA

T DCW -1----1

-O.4V

- - - -- - - - - O.4V - - - - - - - - - VCC

...Jro-------2.4V

Write Timing Characteristics

Max Unit

- nS

395 nS

- nS

, - nS

25 nS

Max Unit

25 liS

- nS

- nS

- nS

- nS

1.0 J.l.S 1

2.0 liS

I/O Timing Characteristics

Characteristic Symbol Min Typ

Rise and fall time for CA 1, CB 1, CA2 and CB2 input signals TRF - -

Delay time, clock negative transition to CA2 negative TCA2 - -transition (read handshake or pulse mode)

Delay time, clock negative transition to CA2 positive T RS1 - -transition (pulse mode) . Delay time, CA 1 active transition to CA2 positive transition T RS2 - -(handshake mode)

Delay time, clock positive transition to CA2 or CB2 negative TWHS - -transition (write handshake)

Delay time, peripheral data val id to CB2 negative transition T DC 0 -

Delay time, clock positive transition to CA2 or CB2 positive T RS3 - -transition (pulse mode)

Delay time, CB1 active transition to CA2 or CB2 positive T RS4 - -transition (handshake mode)

Delay time, peripheral data valid to CA 1 or CB 1 active TIL 300 -transition (input latching)

Delay time CB1 negative transition to CB2 data valid TSR1 - -(internal SR clock, shift out)

Delay time, ne9ative transition of CB1 input clock to CB2 data TSR2 - -valid (external clock, shift out)

Delay time,CB2 data valid to positive transition of CB1 clock T SR3 - -(shift in, internal or external clock)

Pulse Width - PB6 Input Pulse T IPW 2 -

Pulse Width - CB 1 In'put Clock T ICW 2 -

Pulse Spacing - PB6 I nput Pulse liPS 2 -

Pulse Spacing - CB1 Input Pulse IICS 2 -

PB6 INPUT PULSE COUNTING MODE

C T1PW=:\{"'"_-_-_-_-_-_-_::::

CB2 SERIAL DATA IN

CB1CLOCK

CB2 SERIAL DATA OUT

TICW

\ TSR1

TSR2

~

I/O Timing Characteristics

~TS

~r---2.4V

O.4V R3

2.4V V-~ -- -- O.4V

2.4V

O.4V

Max Unit

1.0 j.ts

1.0 j.ts

1.0 j.ts

\

2.0 j.ts

1.0 j.tS

1.5 j.ts

1.0 j.tS

2.0 j.ts

- ns

300 ns

300 ns

( 300 ns

- j.ts

- j.ts

- j.ts

- j.tS

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Timer 1 Operating Modes

Two bits are provided in the Auxiliary Control Register to allow selection of the Tl operating modes. These bits and the four possible modes are as follows:

ACR7 ACR6

Output "Free-Run"

Enable Enable Mode

0 0 Generate a single time·out interrupt each time Tl is loaded

0 1 Generate) continuous interrupts

1 0 Generate a single interrupt and an output pulse on PB7 for each Tl load operation

1 1 Generate continuous interrupts and a square wave output on PB7

FUNCTION CONTROL Control of the various functions and operating modes within the R6522 is accomplished primarily through two registers, the Peripheral Con· trol Register (PCR), and the Auxiliary Control Register (ACR). The PCR is used primarily to select the operating mode for the four peripheral control pins. The Auxiliary Control Hegister selects the operating mode for the Interval Timers (Tl, T2), and the Serial Port (SRI.

Peripheral Control Register

The Peripheral Control Register is organized as follows:

Bit # 7 I 6 I 5 4 3 I 2 I 1 0

Function CB2 Control CBl CA2 Control CAl Control Control

Typical functions are shown below:

PCR3 PCR2 PCR1 Mode

0 0 0 Input mode - Set CA2 interrupt flag (IFRO) on a negative transition of the input signal. Clear

I FRO on a read or write of the Peripheral A Output Register.

0 0 1 Independent interrupt input mode - Set IFRO on a negative transition of the CA2 input sig· nal. Reading or writing ORA does not clear the CA2 interrupt flag.

0 1 0 Input mode - Set CA2 interrupt flag on a positive transition of the CA2 input signal. Clear I FRO with a read or write of the Peripheral A Output Register.

0 1 1 I ndependent interrupt input mode - Set I FRO on a positive transition of the CA2 input sig-

nal. Reading or writing ORA does not clear the CA2 interrupt flag.

1 0 0 Handshake output mode - Set CA2 output low on a read or write of the Peripheral A Output Register. Reset CA2 high with an active transition on CAl.

1 0 , 1 Pulse output mode - CA2 goes low for one cycle following a read or write of the Peripheral

A Output Register.

1 1 0 Manual output mode - The CA2 output is held low in this mode.

1 1 1 Manual output mode - The CA2 output is held high in this mode.

Auxiliary Control Register

Many of the functions in the Auxiliary Control Register have been discussed previously. However, a summary of this register is presented here as a convenient reference for the R6522 user. The Auxiliary Control Register is organized as'follows:

Bit fI 7 I 6 5 4 I 3 I 2 1 0

T2 PB PA Function Tl Control Control Shift Register Control latch latch

Enable Enable

Shift Register Control

The Shift Register operating mode is selected as follows:

ACR4 ACR3 ACR2 Mode

0 0 0 Shift Register Disabled.

0 0 1 Shift in under control of Timer 2 ..

0 1 0 Shift in under control of system clock.

0 1 1 Shift in'under control of external clock pulses.

1 0 0 Free-running output at rate determined by Timer 2.

1 0 1 Shift out under control of Timer 2.

1 1 0 Shift out under control of the system clock ..

1 1 1 Shift out under control of external clock pulses.

T2 Control

Timer 2 operates In two modes. If ACR5 = 0, T2 acts as an interval timer in the one-shot mode. If ACR5 = 1, Timer 2 acts to count a pre: determined number of pulses on pin PB6,

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ROCKWEll INTERNATIONAL-MICROelECTRONIC DEVICES ~~~Y~O~U~R~L~O~C~A~L~R~EP~R~E~S~E~N~T~A~T~IV7.E~----' REGIONAL SALES OFFICES

HOME OFFICE' CENTRAL REGION, U.S.A.

MIDWEST REGION, U.S.A. Rockwell International Corp. Microelectronic Devices P.O. Box 3669

Contact Robert 0 Whitesell & Associates 6691 East Washington Street Indianapolis. Indiana 46219

1011 E. Touhy Avenue, Suite 245 Des Plaines, IL 60018 .

Anaheim, Ca. 92803 (317) 359-9283 Attn. Milt Gamble. Mgr. Phone: (312) 297-8RI<?

U.S.A. Phone: (,114) 632-0950 1WX: 910-591-1698

EASTERN REGION, U.S.A.' Carolier Office Building 850-870 U.S. Route 1

WESTERN REGION, U.S.A. 3310 Miraloma Avenue P.O. Box 3669

, Also Applications Centers North BrunswiCk, New Jersey 08902 Phone: (201) 246-3630

Anaheim, Ca. 92803 Phone: (714) 632- 0950

EUROPE Rockwell International GmbH Microelectronic Devices Fraunhoferstrasse 11 0-8033 Munchen-Martinsried Germany Phone: (089) 859-9575 Tp.IA~: 0521/2650

FAR EAST Rockwell International Overseas Corp. Ichiban-cho Central Building 22-1 Ichiban-cho, Chiyoda-ku Toyko 102, Japan Phone: 265-8808 Telex: J22198

808

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PART NUMBER A6545-1

'1' Rockwell . R6500 Microcomputer System

DATA SHEET

CRT CONTROLLER (CRTC)

DESCRIPTION The R6545-1 CRT Controller (CRTC) is designed to interface an 8-bit microprocessor to CRT raster scan video displays, and adds an advanced CRT controller to the established and expanding line of R6500 products.

The R6545-1 provides refresh memory addresses and char­acter generator row addresses which allow up to 16K char­

_ acters with 32 scan lines per character to be addressed. A major advantage of the R6545-1 is that the refresh memory may be addressed in either straight binary or by row/column.

Other functions in the R6545-1 include an intemal cursor reg­Ister which generates a cursor output when its contents are equal to the current refresh address. Programmable cursor start and end registers allow a cursor of up to the full char­acter scan in height to be placed on any scan lines of the character. Variable cursor display blink rates are provided. A light pen strobe input allows capture of the current refresh address in an internal light pen register. The refresh address lines are configured to provide direct dynamic memory refresh.

All timing for the video refresh memory signals is derived from the character clock input. Shift register, latch, and mul­tiplex control Signals (when needed) are provided by external high-speed timing. The mode control register allows non­interlaced video display modes at 50 or 60 Hz refresh rate. The internal status register may be used to monitor the R6545-1 operation. The RES input allows the CRTC-gen­erated fi~d rate to be dynamically-synchronized with line fre­quency jitter.

ORDERING INFORMATION Part Package

Number Type

R6545-1P Plastic R6545-1AP Plastic R6545-1C Ce.ramic R6545-1AC Ceramic

o RockwelllntamaIIonaI Corporation 1980 All Rights RaHrved PrInted In U.S.A.

Frequency

1 MHz 2 MHz 1 MHz 2 MHz

Temperature Range

O°C to +70°C O°C to +700C O°C to +70°C O°C to +70°C

FEATURES • Compatible with 8-blt microprocessors

• Up to 2.5 MHz character clock operation • Refresh RAM may be configured in row/column or straight

binary addressing

• Alphanumeric and limited graphics capability

• Up and down scrolling by page, line, or character

• Programmable Vertical Sync Width • Fully programmable display (rows, columns, character

matrix)

• N9n-interlaced scan • 50/60 Hz operation • Fully programmable cursor

• Light pen register • Addresses refresh RAM to 16K characters

• No external DMA required

• Internal status register

• 4Q-Pin ceramic or plastic DIP • Pin-compatible with MC6845

• Single +5 ±5% Volt Power Supply

VSS m LPEN CCO/MAO CC1/MA1 CC2/MA2 CC3/MA3 CC4IMA4 CC5/MA5 CC8/MA8 CC7/MA7 CRO/MAS CR1/MA9 CR2/MA10 CR3/MA11 CR4IMA12 CREI/MA13

DISPLAY ENABLE CURSOR VCC

R6545-1 Pin Configuration

VSYNC HSYNC RAO RA1 RA2 'RA3 RA4, 00 01 02 03 04 DEI 08 07 Ci RS ,2 Rlii CCLK

SpecltlcaIIona subject to change without notice Document No. 21000 DI7 Decemblr1_

INTERFACE SIGNAL DESCRIPTION

CPU INTERFACE

!62 (Phase 2 Clock)

The input clock is the system Phase 2 (_2) clock and is used to trigger all data transfers between the system processor (CPU) and the R6545-1. Since there is no maximum limit to the allow­able _2 clock time, it is not· necessary for it to be a continuous clock. This capability permits the R6545-1 to be easily interfaced to non-6500 compatible microprocessors.

R/W (Read/Write)

The R/W input signal generated by the processor is useri to control the direction. of data transfers. A high on the R/W pin allows the processor to read the data supplied by the R6545-1, a low on the R/W pin allows data on data lines 00-07 to be written into the R6545-1.

CI (Chip Select)

The Chip Select input is normally connected to the processor address bus either directly or through a decoder. The R6545-1 is selected when CS is low.

RS (Register Select)

The Register Select input is used to access intemal registers. A low on this pin permits writes (R/W = low) into the Address Register and reads (R/W = high) from the Status Register. The contents of the Address Register is the identity of the register accessed when RS is high.

00-07 (Data Bus)

00-07 are the eight data lines used to transfer data between the processor and the R6545-1. These lines are bidirectional and are normally high-impedance except during read cycles when the chip is selected (~ = low).

VIDEO INTERFACE

HSYNC (Horizontal Sync)

The HSYNC signal is an active-high output used to determine the· horizontal position of displayed text. It may drive a CRT monitor directly or may be used for composite video generation. HSYNC time position and width are fully programmable.

VSYNC (Vertical Sync)

The VSYNC signal is an active high output used to determine the vertical position of displayed text. Like HSYNC, VSYNC may be used to drive a CRT monitor or composite video generation circuits. VSYNC time position and width are both programmable.

QISPLAYENABLE (Display Enable)

The OISPLA Y ENABLE signal is an active-high output used to indicate when the R6545-1 is generating active display infor­mation. The number of horizontal display characters per row and the number of vertical display rows are both fully program­mable and together are used to generate the OISPLA Y ENABLE signal. DISPLAY ENABLE can be delayed one character time by setting bit 4 of RB equal to 1.

CURSOR (Cursor Coincidence)

The CURSOR signal is an active-high output used to indicate ( when the scan coincides with the programmed cursor position. The cursor position may be programmect to be any character in the address field. Furthermore, within the character, the·our-sor may be programmed to be any block of scan lines, since the start scan line and the end scan line are both programmable. The cursor position may be delayed by one character time by setting Bit 5 of RS to A "1".

LPEN (Light Pen Strobe)

The LPEN signal is an· edge-sensitive input used to load the internal Light Pen Register with the contents of the Refresh . Scan Counter at the time the active edge. occurs. The active edge of LPEN is the low-to-high transition.

CCLK (Clock)

The CCLK signal is the character timing clock input and is used as the time base for all internal count/control functions.

FmI The R'ESsignal is an active-low input used to initialize all in­ternal scan counter circuits. When ~ is low, all intemal counters are stopped and cleared, all scan and video outputs are low, and control registers are unaffected. m must stay low for at least one CCLK period. All scan timing is initiated when RES goes high. In this way, m can be used to syn­chronize display frame timing with line frequency. RES may also be used to synchronize multiple CRTC's in horizontal· and/or ( vertical split screen operation. .

REFRESH RAM AND CHARACTER ROM INTERFACE

MAo-MA13 (Refresh RAM Address Lines)

These 14 signals are active-high outputs used to address the Refresh RAM for character storage and display operations. The starting scan address is fully programmable and the ending scan address is determined by the total number of characters displayed, which is also programmable, in terms of characters/ line and lines/frame.

There are two selectable address modes for MAO~MA 13:

In the straight binary. mode (RB, Mode Control, bit 2 = "0"), characters are stored in successive memory locations. Thus, the software must be designed such that row and column char­acter coordinates are translated into sequentially-numbered ad­dresses. In the row/column mode (RB, Mode Control, bit 2 = "1 "), MAO-MA7 become column addresses CCO-CC7 and MAS­MA 13 become row addresses CRO-CR5. In this case, the soft­ware can manipulate characters in terms of row and column lo­cations, but additional address compression circuits are needed to convert the CCO-CC7 and CRO-CR5 addresses into a mem­ory-efficient binary address scheme.

RAo-RA4 (Raster Address Lines)

These 5 signals are active-high outputs used to select each ras- ( ter scan within an individual character row. The number of raster J

scan lines is programmable and determines the character height, including spaces between character rows.

INTERNAL REGISTER ORGANIZATION

Addr_ Register Read Write Register Bit Reg. IR/W- IR/W-

CS RS 4 3 2 1 0 No. Register Name Register Units Highl Lowl 7 6 5 4 3 2 1 0

1 X X X X X X X 1/ I V V V / / 0 0 X X X X X X Address Register Register No. V V / V 4 3 2 1 0 0 0 X X X X· X X Status Register _ .. V V 6 5V V /' ./ 0 1 0 0 0 0 0 RO Horizontal Total Char No. of Characters/Row V 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 Rl Horizontal Displayed Char No. of Characters/Row V 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 R2 Horizontal Sync Position Character Position V 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 R3 YSYNC, HSYNC Widths No. of Scan Lines, Characters V 7 6 5 4 3 2 1 0 0 1 0 0 1 0 0 R4 Vertical Total Rows No. of Character Rows V /' 6 5 4 3 2 1 0 0 1 0 0 1 0 1 R5 Vertical Total Adjust Lines No. of Scan Lines V /' /' ./ 4 3 2 1 0 0 1 0 0 1 1 0 A6 Vert.ical Displayed Rows No. of Character Rows V V 6 5 4 3 2 1 0 0 1 0 0 1 1 1 R1 Vertical Sync Position No. of Character Rows V V 6 5 4 3 2 1 0 0 1 0 1 0 0 0 RS Mode Control - V 7 6 5 4 3 2 1 0 0 1 0 1 0 0 1 R9 Scan Line No. of Scan Lines V /' V ./ 4 3 2 1 0 0 1 0 1 0 1 0 R10 Cursor Start Line Scan Line No. V V 8 5 4 3 2 1 0 0 1 0 1 0 1 1 Rll Cursor End Line Scan Line No. V /' V ./ 4 3 2 1 0 0 1 0 1 1 0 0 R12 Display Start Address (HI - V /' V 5 4 3 2 1 0 0 1 0 1 1 0 1 R13 Display Start Address (L1 - V 7 6 5 4 3 2 1 0 0 1 0 1 1 1 0 R14 Cursor Position Address (HI - V V ./' V 5 4 3 2 1 0 0 1 0 1 1 1 1 R15 Cursor Position Address (L1 - V V 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 R16 Light Pen Register IHI - V ./' V 5 4 3 2 1 0 0 1 1 0 0 0 1 R17 Light Pen Register (LI - V 7 6 5 4 3 2 1 0

Table 1. Overall Register Structure and Addressing

CPU IIF GND

VIDEO IIF

~D7~~~~--------~--"HSYNC .......... ~VSYNC

cb2---4~ R/W ---II" cs---II" RS - ...... 1.,..r----.,.,J

MAO-MA13 RAO·RA4

DISPLAY ENABLE . CURSOR LPEN CCLK RES

REFRESH RAM AND CHARACTER ROM

R6545·1 Interface Diagram

INTERNAL REGISTER DESCRIPTION

ADDRESS REGISTER

This 5-bit write-only register is used as a "pointer" to direct CATC/CPU data transfers within the CATC. Its contents is the number of the desired register (0-17). When CS and AS are low, then this register may be loaded; when CS is low and AS is high, then the register selected is the one whose identity is stored in this address register. .

STATUS REGISTER (SR)

This 8-bit register contains the status of the CATC. Only two bits are assigned, as follows:

'----__..v ___ --.J'

L.I ----NOT USED

Vertical R. Tree (VRT) o • Scan Is not currently in its vertical .. t..- time. 1 - Scan il currently in its vertiCil .... t,_ time.

Not. the! this bit octulily g_ to I HI H when verti .. 1 re-trece stlrts, but goes to • "0" five char.etar clock tim.. before vertiCal ... ·t..... In., 10 that critical timings for refresh RAM _rations Ire lvoided.

'----- LPEN Register Full (LRF) o - Register R16 Dr R17 h. bUn reod by the CPU.

1 - LPEN strobe h .. bUn ..... ived.

'------ Not Used

NOTE: The Statu. Register tak .. the State, I-I 0 l' 1-1-1-1-1-1 immediately after pOWer (V CCI turn..,n.

Ro-HORIZONTAL TOTAL CHARACTERS

This 8-blt write-only register contains the total of displayed and non-displayed characters, minus one, per horizontal line. The frequency of HSYNC Is thus determined by this register.

R1-HORIZONTAL DISPLAYED CHARACTERS

This 8-bit write-only register contains the number of displayed characters per horizontal line.

R2-HORIZONTALSYNC POSITION

This 8-bit write-only register contains the position of the hori­zontal SYNC on the horizontal line, In terms of the character location number on the line. The position of the HSYNC deter­mines the left to right location of the displayed text on the video screen. In this way, the side margins are adjusted.

R3-HORIZONTAL AND VERTICAL SYNC WIDTHS

This B-bit write-only register contains the widths of both HSYNC and VSYNC, as follows:

HSYNC Pulse Width

The width of the horizontal sync pulse IHSYNC) in the number of character clock times ICCLK).

'--------- VSYNC Pulse Width

The width of the vertical sync pulse IVSYNC) in the number of scan lines. When bits 4·7 are all "0", VSYNC will be 16 scan lines wide.

Control of thes~ parameters allows the R6545-1 to be interfaced to a variety of CRT monitors, since the HSYNC and VSYNC timing signals may be accommodated without the use of exter­nal one shot timing.

R4-VERTICAL TOTAL ROWS

The Vertical Total Register is a 7-bit register containing the total number of character rows in a frame, minus one. This register, along with R5, determines the overall frame rate, which should be close to the line frequency to ensure flicker-free appearance. If the frame time is adjusted to be longer than the period of the line frequency, then RES may be used to provide absolute synchronism.

RS-VERTICAL TOTAL LINE ADJUST

The Vertical Total Line Adjust Register (R5) is a 5-bit write-only register containing the number of additional scan lines needed to complete an entire frame scan and is intended as a fine ad­justment for the video frame time.

R6-VERTICAL DISPLAYED ROWS

This 7-bit write-only register contains the number of displayed character rows in each frame:

R7-VERnCAL SYNC POSmON

This 7-bit write-only register is used to select the character row (­time at which the vertical SYNC pulse is desired to occur and, thus, is used to position the displayed text in the vertical direction.

"RI-MODE CONTROL (MC)

This 8-bit write-only register selects the operating modes of the R6545-1 , as follows:

78543210

MC7 MC8 MC& MC4

- - CSK DES

MC3

0

MC2 MC. MC&

"AD _ 0

L:= M .... Program to "0"

NoIUoed

'---R".'_RA M Add ..... ing Mode fRADI or streight binary o • f .. , or Row/Column

L...--- Mult Protr. mtDUO'"

D ...... E ... ble Skew IDESt no .... ay. o • for

• • to ct.1.., DilpllV EMbie OM ch.rlcter .tIme •

CUrsor Sk. w (CSKI 0- for no delay. , .. to ctet.v CursoI' on. ehllrNtH' tim •.

}~

R9-ROW SCAN LINES

" This 5-bit write~only register contains the number of scan lines, minus one, per character row, including spacing.

R10-CURSOR START LINE R11-CURSOR END LINE

These 5-bit" write-only registers selept the starting and ending scan lines for the cursor. In addition, bits 5 and 6 of R10 are used to select the cursor blink mode, as follows:

Bit

~

o o 1

Bit

...L

o 1 o 1

Cursor Blink Mode

Display Cursor Continuously Blank Cursor Continuously Blink Cursor at 1/16 Field Rate Blink Cursor at 1/32 Field Rate

R12-DISPLAY START ADDRESS HIGH R13-DISPLAY START ADDRESS LOW

These registers form a 14-bit register whose contents is the memory address of the first character of the displayed scan (the character on the top left of the video display, as in Figure 1). Subsequent memory addresses are generated by the R6545-1 as a result of CCLK input pulses, Scrolling of the display is ac­complished by changing R12 and R13 to the memory address ( .. associated with the first character of the desired line of text to be displayed first. Entire pages of text may be scrolled or changed as well via R12 and R13.

NUMBER OF HORIZONTAL TOTAL CHARACTERS CROI ~~ ____________________ -JA~ ____________________ ~,

NUMBER OF HORIZONTAL DISPLAVED CHARACTERS CRt!

r~--------------~A~------------~, Lg::~~ START ADDRESS HIGH CR121*

START ADDRESS LOW CR13I*

~

~ 1\

F l NUMBER 0 SCAN LIN ES CRtl

~CURSO,"

I"""CURSOR

START LINE CR1'1

END LINE CR111

\""D .. nD POSITION AODRESS HIGH CR141 CURSOR POSITION ADDRESS LOW CR1111

NUMBER OF VERTICAL TOTAL ROWS CR41

NUMBER OF VERTICAL' OISPLAV ROWS CRill •

. DISPLAV PERIOD

HORIZONTAL RETRACE PERIOD CNON.oISPLA VI

VERTICAL RETRACE PERIOO CNON.oISPLA VI

VERTICAl. TOTAL { ADJUST CRSI

Figure 1. Video Display Format

R14-CURSOR POsmolt.i HIGH R15-CURSOR PosmON LOW

These registers form a 14-bit register whose contents is the memory address of the current cursor position. When the video display scan counter (MA lines) matches the contents of this register, and when the scan line counter (RA lines) falls within the bounds set by R10 and R11, then the CURSOR output be­comes active. Bit 5 of the Mode Control Register (RS) may be used to delay the CURSOR output by a full CCLK time to ac­commodate slow access memories.

R16-LlGHT PEN HIGH R17..;..LlGHT PEN LOW

These registers form a 14-bit register whose contents is the light pen strobe position, in terms of the video display address at which the strobe occurred. When the LPEN input changes from low to high, then, on the next negative-going edge of CCLK, the contents of the internal scan counter is stored in registers R16 and R17.

REGISTER FORMATS

Register pairs R12/R13, R14/R15, and R16/R17 are formatted in one of two ways:

(1) Straight binary, if register RS, bit 2 = "0".

(2) Row/Column, if register RS, bit 2 = "1". In this case the· low byte is the Character Column and the high byte is the Character Row.

DESCRIPTION OF·OPERATION

VIDEO DISPLAY

Figure 1 indicates the relationship of the various pr09ram reg­isters in the R6545-1 and the resultant video display.

Non-displayed areas of the Video Display are used for horizon­tal and vertical retrace functions of the CRT monitor. The hori­zontal and vertical sync signals, HSYNC and VSYNC, are pro­grammed to occur during these intervals and are used to trigger the retrace in the CRT monitor. The pulse widths are eon­strained by the monitor requirements. The time position of the pulses may be adjusted to vary the display margins (left, right, top, and bottom) ..

REFRESH RAM ADDRESSINO

Shared Memory Mode (RB, bit 3 = "0")

In this mode, the Refresh RAM address lines (MAO-MA 13) di­rectly reflect the Contents of the internal refresh scan character counter. Multiplex control, to permit addressing and selection of the RAM by both the CPU and the CRTC, must be provided external to the CRTC. In the Row/Column address mode, lines MAO-MA7 become character column addresses (CCO-CC7) and MAS-MA13 become character row addresses (CRO-CR5).

ADDRESSING MODES

Row/Column

In this mode, the CRTC address lines (MAO-MA 13) are ganer­atadas 8 column (MAo-MA7) and 6 row (MAS-MA 13) ad­dresses. Extra hardware is needed to compress this addressing into a straight binary sequence in order to conserve memory in the refresh RAM.

Binary

In this mode, the CRTC address lines are straight binary and no compression circuits are needed. However, software com­plexity is increased since the CRT characters cannot be stored in terms of their row and column locations, but must be sequential.

USE OF DYNAMIC RAM FOR REFRESH MEMORY

The R6545-1 permits the use of dynamic RAMS as storage de­vices for the Refresh RAM by continuing to increment memory addresses in the non-display intervals of the scan. This is a vi­able technique, since the Display Enable Signal controls the actual video display blanking. Figure 2 illustrates Refresh RAM addressing for the case of binary addressing for 80 columns and 24 rows with 10 non-displayed columns and 10 non-displayed rows.

TOTAL-go

DISPLAY·80 , . 0 1 2 3 76 71 78 79 80 81 89

80 81 82 83 156 157 158 159 160 161 169

160 161 162 237 2.38 239 240 249

240 241 242 317 318 319 320 329

1680 1681 1682 1757 1758 175.9 1760 1769

1760 1761 1762 1837 1838 1839 1840 1849

1840 1841 1842 1917 1918 1919 1920 1929

1920 1921 1922 1997 1998 1999 2000 2009

2000 2001 2002 2077 2078 2079 2080 2089

2640 2641 2642 2717 2718 2720 2729

Figura 2. Memory Addressing Example (80 x 24)

CURSOR OPERATION

A one character wide cursor can be controlled by storing values into the Cursor Start Line (R10) and Cursor End Une (R11) reg­isters and into the Cursor Position Address High (R14) and Cur­sor Position . Low (R15) registers.

Bits 5 and 6 in the Cursor Start Line High Register (R10) control (-the cursor display and blink rate as follows:

BitS Bit 5 Cursor C)ptInting Mode

0 0 Display Cursor Continuously. 0 1 Blank Cursor Continuously 1 0 Blink Cursor at 1/16 Field Rate 1 1 Blink Cursor at"1/32 Field Rate

The cursor of up to 32 characters in height can be displayed on and between the scan lines as loaded into the Cursor Start Line (R10) and Cursor End Line (R11) Registers.

The cursor is positioned on the screen by loading the Cursor Position Addtess High (R14) and Cursor Position Address Low (R15) registers with the desired refresh RAM address. The cur­sor can be positioned in any of the 16K character positions. Hardware paging and data scrolling is thus allowed without loss of cursor position. Figure 3 is an example of the display cursor scan line.

UNDERLINE CURSOR

OVERLINE CURSOR

BOX CURSOR

o 0 O~~++~-1 1 1~""~~ 2 2 23ElI!~~ 3 3 3 4 4 4

5 5 5~~:t~ 6 6 6~

7 7 73EliliaaE 8 8 8 9 9 9

10 10 10~~++-H-11 11 11-++++t-t-if--

CURSOR START CURSOR START CURSOR START LINE = 9 LINE = 1 LINE = 1

CURSOR END LlNE=9

CURSOR END LINE = 1

CURSOR END LINE =9

Figure 3. Cursor Display Scan Line Control Examples

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MPU WRITE TIMING CHARACTERISTICS

(V cc '" 5.0V ±5%. T A = 0 to 70oC. unless otherwise noted)

1 MHz 2MHz

ClwlCteriitic Symbol Min Max Min Max Unit

Cycle Time TCYC 1.0 - 0.5 - In

02 Pulse Width TC 440 - 200 - ns

Address Set-Up Time TACW 180 - 90 - ns

Address Hold Time TCAH 0 - 0 - ns

RtW Set-Up Time TWCW 180 - 90 - ns

Riiii Hold Time TCWH 0 - 0 - ns

Data Bus Set-Up Time TDCW 265 - 100 - ns

Data Bus Hold Time THW · 10 - 10 - ns

(tr and t f • 10 to 30 111)

WRITE CYCLE

~----------TCYC------------~

2.0V 2.0V

O.BV r-------J ... ----_I-T ACW

.,..,..,..,~

2.0V

Ci, RS

O.BV

____ ... ----.... -TWCW

O.BV

TOCW THW

DO-07

MPU READ TIMING CHARACTERISTICS ( (V cc = 5.0V ±5%. T A = 0 to 700 C. unless otherwise noted),

1 MHz 2 MHz

Characteristic Symbol Min Max Min Max Unit -

Cycle Time TCYC 1.0 - 0.5 - ",5

02 Pulse Width TC 440 - 200 - ns

Address Set-Up Time TACR 180 - 90 - ns

Address Hold Time TCAR 0 - 0 ~ ns

RtWSet-Up Time TWCR 180 - 90 - ns

Read Access Time TCDR - 340 - 150 ns

Read Hold Time THR 10 - 10 - ns

Data Bus Active'Time (Invalid Data) TCDA 40 - 40 - ns

Itr and tf = 10 to 30 ns)

---,-.. --~-------~-.

MEMORY AND VIDEO INTERFACE CHARACTERISTICS

(V cc '" 5.0V ±.5%, T A" 0 to 70De. unless otherwise noted)

1 MHz

Characterittics Symbol Min Mo.

Char .. Clock CVcle Time TCCY 0.' 40

Char. Clock Pulse Width TCCH 200 -MAO·MA 13 Propagation Delay TMAD - 300

RAO-RA4 Propagation Delav TRAD - 300

DISPLAY ENABLE Prop. Delay TDTD - 450

HVSNC Propagation Delay THSD - 450

VSYNC Propagation TVSD - 450

Cursor Propagation Delay TCDO - 450

LPEN Strobe Width T LPH ISO -

LPEN to CCLK Delay T LPI 20 -

CCLK to. LPEN Delay T LP2 0 -

fr. tf ., 20 ns (max)

SYSTEM TIMING DEFINITIONS

~------------TCCY--------------~

CCLK

SIGNAL­ISee Belowl

2.0V

* SIGNAL

MAO·MA13

RAO·RA4

DISPLAY ENABLE

HSYNC

VSYNC

CURSOR

LIGHT PEN STROBE TIMING DEFINITIONS

CCLK

SIGNAL SYMBOL IX)

TMAD

TRAD

TDTD

T HSD

TVSD

TCDD

2MHz

Min Mo. Units

0.' 40 .s

200 - ns

- 300 ns

- 300 ns

- 450 ns

- 450 ns

- 450 ns

- 450 ns

ISO - ns

20 - ns

0 - ns

\"----

O.BV 1------'

LPEN

SEE NOTE

MAO.MA13 _____ ~~\.. ___ n_+l ___ ___l~\.. ______ n+_2 ______ [

NOTE:

SLASH AREA DEFINES THE "WINDOW" IN WHICH AN LPEN POSITIVE EDGE WILL CAUSE ADDRESS N+2 TO LOAD INTO LIGHT PEN REGISTER. TRANSITIONS ON EITHER SIDE OF THIS "WINDOW" WILL RESULT IN UNPREDICTABLE VALUES BEING LOADED INTO THE LIGHT PEN REGISTER.

SPECIFICATIONS

Maximum Ratings

Rating Symbol Value Unit

Supply Voltage VCC -0.3 to +7.0 Vdc

Input Voltage VIN -0.3 to +7.0 Vdc

Operating Temperature Range TOp o to +70 °c Storage Temperature T STG ·55 to 150 °c

All inputs contain protection circuitry to prevent damage due to high static discharges., Care should be taken to prevent unnecessary applica­tion of voltages in excess of the allowable limits.

Electrical Characteristics

(V CC = 5.0V ±5%, T A = 0·70oC, unless otherwise noted)

Characteristic Symbol Min Max Unit\

Input High Voltage VIH 2.0 VCC Vdc

Input Low Voltage VIL 0.3 0.8 Vdc

Input Leakage (02, RfiiJ, RES,~, RS, LPEN, CCLK) liN - 2.5 "Adc

Three-State Input Leakage (00-07)

(V IN = 0.4 to 2.4V) ITSI - 10.0 "Adc

Output High Voltage

I LOAO = 205 "Adc (00-07) VOH 2.4 - Vdc

I LOAO = 100 "Adc (all others)

Output Low Voltage

ILOAO = 1.6 mAdc VOL - 0.4 Vdc

Power Oissipation Po - 1000 mW

Input Capacitance

02,RAN,RES,CS,RS, LPEN,CCLK CIN - 10.0 pF

00-07 - 12.5 pF

Output Capacitance COUT - 10.0 pF ..

TEST LOAD

2.4Kfl

R854S-1 PIN

130pF I R

R=11KO FOR 00-07 =24KO FOR ALL OTHER OUTPUTS

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PART NUMBER R6551

R6500 Microcomputer System

DATA SHEET

Asynchronous Communication Interface Adapter (ACIA) The R6551 Asynchronous Communication Interface Adapter

(ACIA) provides a program-controlled interface between 8-bit

microprocessor-based systems and serial communication data sets and modems.

With its on-chip baud rate generator, the R6551 is capable of

transmitting at 15 different program-selectable rates between

50 baud and 19,200 baud, and receiving at either the transmit rate or at 16 times an external clock rate. The R6551 has pro­

grammable word lengths of 5, 6, 7, or 8 bits; even, odd or no

parity; 1, 1-1/2 or 2 stop bits.

With the R6551, a crystal is the only required external support

component - eliminating the multiple-component support that is typically needed.

In addition, the R6551 is designed for maximum programmed

control from the CPU, to simplify hardware implementation. A

control register and a separate command register permit the CPU

to easily select the R6551 's operating modes and check data, parameters and status.

Ordering Information

Order Package Temperature Number Type Frequency Range

R6551 P Plastic 1 MHz OOC to +700 C

R6551AP Plastic 2 MHz OOC to +700 C

R6551C Ceramic 1 MHz OOC to +700 C

R6551AC Ceramic 2 MHz OOC to +700 C

VSS CSO CS1 IRQ

RES 07 RxC 06 XTLI 05

04 RTS 03

CTS 02 TxO 01

OTR 11 DO RxO 12 DSR

RSO 13 OCO

RS1 14 VCC

R6551 Pin Configuration

© Rockwell International Corporation 1981 All Rights Reserved Printed in U.S.A.

FEATURES

• Compatible with 8-bit microprocessors

• Full duplex or half duplex operation with buffered receiver and transmitter

• 15 programmable Baud Rates (50 to 19,200)

• Receiver data rate may be identical to baud rate or may be 16 times the external clock input

• Data set/modem control functions • Programmable word lengths, number of stop bits, and parity

bit generation and detection

• Programmable interrupt control

• Software reset • Program-selectable serial echo mode

• Two chip selects • 2 MHz or 1 MHz clock rate • Single +5V ±5% power supply • 28-pin plastic or ceramic DIP

• Full TTL compatibility

00-07<::8

IRQ

RtW

CSO

CS1

RSO

RS1

JJ2

RES

VCC

VSS

..

DATA BUS BUFFERS

I/O CONTROL

TIMING & CONTROL LOGIC

TRANSMIT DATA & SHIFT REGISTERS

BAUD RATE GENERATOR

RECEIVE DATA & SHIFT REGISTERS

~--CTS

'---I~TxD

..... -- DCD

141--I~ RxC

~--XTLI

I--"'XTLO

DTR

RTS

RxD

R6551 Interface Diagram

Specifications subject to change without notice

Document No_ 29000 053 Rev. 1, January 1981

» en -< :s (') :::T ... o :s o c:: en n o 3 3 c:: :s -. (') Q) r+ _. o :s -:s r+ CD :::.l. Q) (') CD

» 0. Q)

"0 r+ CD ... -» n -» -

INTERNAL ORGANIZATION

00-07 T.O

6CD IRQ

DsR

~tW R.C

CSO XTLI

CS; XTLQ

RSO OTR

RS, fiTS

.2 R.O

Rei

R6551 BI;)ck Diagram

Transmitter/Receiver

Bits 0-3 of the Control Register .select the divisor used to generate the baud rate for the Transmitter. If the Receiver clock is to use the same baud rate as the Tr·ansmitter, then RxC becomes an output pin and can be used to slave other circuits to the R6551.

..... -""""T-- RxD

.... ----------- RxC

XTLI

Transmitter/Receiver Clock Circuits

Transmit and. Receive Data Regist~rs

These registers are used as temporary data storage for the 6551 Trans­mit and Receive circuits. The Transmit Data Register is characterized as follows:

• Bit 0 is the leading bit to be transmitted.

• Unused data bits are the high-order bits and are "don't care" for transmission.

The Receive Data Register is characterized in a similar fashion:

• Bit 0 is the leading bit received.

• Unused data bits are the high-order bits and are "0" for the receiver.

• Parity bits are not contained in the Receive Data Register, but are stripped-off after being used for external parity checking. Parity and all unused high-order bits are "0".

Control Register

The Control Register selects the desired baud rate, frequency source, word· length, and the number of stop bits.

ISBN I WL I RCS , seR' I I WL' WLO I [SBR3ISBR2ISBR'ISBROI

Lc--I

,'----- SELECTED BAVO RATE ISBR)

~ ! !.~ o Q 00 00 0 , 00 1 0 00 1 1 o 1 00 o 1 0 1 o 1 1 0 o 1 ., 1 , 0 00 '001 10 10 10 1 1 1 1 00 11 01 1 1 1 0 1111

16x b .... M) Clock 50 a.\ld 75 '&.Iud 109.92 Baud 134.58 Baud 150 s.ud 300 Bo'" 600 Blud 12()O Blud 1800 Baud 2400 Baud 3600 Blud 4800 S.ud 7200 Baud 9600 s.ud 19.200 a.ud

'---------- RECEIVER. CLOCK SOURCE IRCS)

o .. E~t ... n.1 Receiver Ctock 1. - B.ud R •• e

'-------------- WORD LENGTH IWL)

n 00 8 Bits 0' 'Bits 10 SBits T 1 SSits

'----------------- SToP BIT NUMBER ISBN)

7 6 5 4 3 2 1 O.

10 10 10 I 0 10 10 10 10 I H"d ... ," R .... ,IiU) - - - - - - - - Prolr.mRese!

0-1 Stop Bit T =2StopBits

-l%StopBitl IFor WL - 6.nd No Parity)

zlStopBit . (For Wl" 8 and Paritvl

R6551 Control Register

Commllnd Register

The Command Register controls specific modes and functions.

~OATATERMINAL READY IOTR)

o • Deb T«miNlI Not R_cty (OTA High) , • Datil TermlNlI RNdy li5TlI' Low)

INTERRUPT REQUEST DISABLED (lRO)

O. IRQ E .. bltd , -IAQDilllblfd

TRANSMITTER INTERRUPT CONTRDLITlC)

~ ~ iffiI. Hloh, T ........ I ...... upt O_blod 0" RTI- Low, Tnn .... 1t Im.rupt E_1ed 10m· LoW, Transmit Int.rupt Enlbled 1 1 fITS .. Low. TrlMlnit Interrupt DI_11Id

Tr.n .... it Bruk on TxO

'---------- RECEIVER ECHO MODE IREM)

0" Recti .. Nor .... Mode . , .. ANI'_ Echo Mod.

L--____ --'-...;.. _____ PARITY MODE ENABLED IPME)

o .. PII,ity Mod. Di.b'-' . No Plirity Bit 0 __

Parity Check D_bled 1 .. Perity Mode El1Iblld

'---------------- PARITY MODE CONTROLIPMC)

Z Ii o 0 Odd ,.-Ity Tn .. wmlttedIRectiwd o 1 E .... PI,ity Tr.ftlmittedlA .. i .... 1 0 Mlrk "'rhy Bit Tr.lIIMiIted

PII,ity Check Otab ... 1 1 StMce ..... ity Bit T,..nsm'*tecl

... ,ityCheclcDillblMl

R6551 Command Register

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Status Register

The Status Register reports the status of various R6551 functions

1 0

I ~ ~;;;;::;;"'. Frammg Error·

a '" No Framing Error 1 ,. Framing Error Detected

Overrun-

D = No Ollerrun

1 = Overrun Hi'15 Occurred

L-______ Receiver Data Register Full

o ., Not Full 1 ,. Full

L-________ Transmitter Data Register Empty

o = Not Empty 1 = Empty

L-__ ~ _______ Data Carrier Detect lOCO)

o = OeD low (Detect) 1 = OeD high (Not Detectedl

L-____________ Data Set Ready (DSR)

o = DSA low (Ready) 1 '" DSA high (Not Ready)

L-______________ Interrupt (tRQ!

a '" No Interrupt , '" Interrupt Has Occurred

-No interrupt occurs for these conditions

R6551 Status Register

INTERFACE SIGNAL DESCRIPTION

RES (Reset)

During system initialization a low on the RES input will cause internal registers to be cleared.

02 (Input Clock)

The input clock is the system 02 clock and is used to synchronize all data transfers between the system microprocessor and the R6551.

R/W (Read/Write)

The R/W is generated by the microprocessor and is used to control the direction of data transfers. A high on the R/W pin allows the proc' essor to read the data supplied by the R6551. A low on the R!W pin allows a write to the R6551.

I RQ (Interrupt Request)

The iRCi pin is an interrupt output from the interrupt control logic. It is an open drain output, permitting several devices to be connected to the common IRQ microprocessor input. Normally a high level, iR5 goes low when an interrupt occurs.

00-07 (Data Bus)

The 00-07 pins are the eight data lines used to transfer data between the processor and the R6551. These lines are bi-directional and are normally high-impedance, except during Read cycles when the R6551

is selected.

cso, CS, (Chip Selects)

The two ch ip select inputs are normally connected to the processor address lines either directly or through decoders. The R6551 is selected when CSO is high and CS1 is low.

RSO, RS' (Register Selects)

The two register select lines are normally connected to the processor address lines to allow the processor to select the various R6551 internal registers. The following table indicates the internal register select coding:

RS' RSO Write Read

0 0 Transmit Data Receiver Data Register Register

0 1 Programmed Status Register Reset (Data is "Don't Care")

1 0 Command Register

1 1 Control Register

Note that only the Command and Control registers are read/write. The Programmed Reset operation does not cause any data transfer, but is used to clear Bits 0 through 4 in the Command Register and Bit 2 in the Status Register. The Programmed Reset is slightly different from the Hardware Reset (RES); these differences are described in the individual register definitions.

ACIA/Modem Interface Signal Description

XTLI, XTLO (Crystal Pins)

These pins are normally directly connected to the external crystal (1.8432 MHz) used to derive the various baud rates. Alternatively, an externally generated clock may be used to drive the XTLI pin, in which case the XTLO pin must float. XTLI is the input pin for the

transmit clock.

TxD (Transmit Data)

The TxD output line is used to transfer serial NRZ (non-return-to­zero) data to the modem. The LSB (least significant bit) of the Trans­mit Data Register is the first data bit transmitted and the rate of data transmission is determined by the baud rate selected, or under control of an external clock (as selected by the Control Register!.

RxD (Receive Data)

The RxD input line is used to transfer serial NRZ data into the ACIA from the modem, LSB first. The receiver data rate is either the pro­grammed baud rate or the rate of an externally generated receiver

clock (as selected by the Control Register!.

RxC (Receive Clock)

The RxC is a bi-directional pin which serves as either the receiver 16x clock input or the receiver 16x clock output. The latter mode results if the internal baud rate generator is selected for receiver data clocking.

(",- ',' , '

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RTS (Request to Send)

The RTS output pin is used to control the modem from the processor. The state of the RTS pin is determined by the contents of the Com­mand Register.

CTS (Clear to Send)

The CTS inp~t pin is used to control the transmitter operation. The enable state is with CTS low. The transmitter is automatically dis­abled if CTS is high.

DTR (Data Terminal Ready)

This output pin is used to indicate the status of the R6551 to the modem_ A Iowan DTR indicates the R6551 is enabled and a high indicates it is disabled. The processor controls this pin via bit 0 of the Command Register.

READ/WRITE CYCLE CHARACTERISTICS

(VCC = 5.0V ±5%, T A = 0 to 700 C, unless otherwise noted)

Characteristic Symbol Min

Cycle Time tCYC 1.0

02 Pulse Width tc 400

Address Set-Up Time tAC 120

Address Hold Time tCAH 0

R/W Set-Up Time twc 120

R/W Hold Time tCWH 0

Data Bus Set-Up Time tDCW 150

Data Bus Hold Time tHW 20

Read Access Time (Valid Data) tCDR -Read Hold Time tHR 20

Bus Active Time (Invalid Data) tCDA 40

(t r and tf = 10 to 30 ns)

CSO, CS1, RSO, RSl

DSR (Data Set Ready)

The DSR input pin is used to indicate to the R6551 the status of the modem. A low indicates the "ready" state and a high, "not-ready". DSR is a high-impedance input, and must be connected. If .unused, it should be driven high or lOiN, but not switched.

DCD (Data Carrier Detect)

The DCD input pin is used to indicate to the R6551 the status of the carrier-detec~ outpuf of the modem. A low indicates that the modem carrier signal is present and a high, that it is not. Like 5SR, DCD is a high-impedance input, and must be connected.

1 MHz 2MHz

Max Min Max Unit

40 0.5 40 J..Is

- 200 - ns

- 70 - ns

- 0 - ns

- 70 - ns

- 0 - ns

- 60 - ns

- 20 - ns

200 - 150 ns

- 20 - ns

- 40 - ns

===~VIH

~~~VIL

~------------------VIH

V 1L

Write Timing Characteristics

~---------------------------------------------------VIH RtW

Read Timing Characteristics

TRANSMIT/RECEIVE CHARACTERISTICS

1 MHz 2 MHz

Characteristic Symbol Min Max Min Max Unit

Transmit/Receive tCCY 400' - 400' - ns Clock Rate

Transmit/Receive tCH 175 - 175 - ns Clock High Time

Transmit/Receive tCl 175 - 175 - ns Clock low Time

XTLI to TxD too - 500 - 500 ns Propagation Delay

RTS Propagation t Dly - 500 - 500 ns Delay

I RQ Propagation tlRQ - 500 - 500 ns Delay (Clear)

(t r, t f = 10 to 30 ns)

1 'The baud rate with external clocking is: Baud Rate = -16--'---

x TCCY

PACKAGE OUTLINES

28 LEAD CERAMIC

1.115)

'" (1.420) • 1.080) (1.380) I +

j~~~A,,,,, : jt = I I "'" I---:::: ---I ,-, (.055) (.022) --l 1-1.090) (.010) (.015) 1.155) 1.065)

(.125) (.015)

I---------tccv--------~

XTll (TRANSMIT CLOCK INPUT) __ .....I

TxO

IRQ (CLEAR)

Rxe (INPUT)

NOTE: TxO rate is 1/16 TxC rate

Transmit Timing with External Clock

_ -----J

tIRQ!-Interrupt and Output Timing

I------tccv------~~I

NOTE: RxO rate is 1/16 RxC rate

Receive External Clock Timing

28 LEAD PLASTIC

I (.550) (.530)

a.,.;,..,.,..,1"'I"T"I"T"I ................................................... ~ ~_------_(1.470)----_-.

(1.440)

(.065) 1.065)

(

(

(.

Intel S04SH/S04SH-1 /S035H LlS035H L-1 HMOS SINGLE COMPONENT S-BIT MICROCOMPUTER

• S04SH/S048H-1 Mask Programmable ROM • S03SHL/803SHL-1 CPU Only with Power Down Mode

• 8-BIT CP.U, ROM, RAM, I/O in Single • 1K x 8 ROM Package 64 x 8 RAM

• High Performance HMOS 27 I/O Lines

• Interval Timer/Event Counter • Reduced, Power Consumption • Easily Expandable Memory and I/O

• 1.4 usec and 1.9 usec Cycle Versions • Compatible with 8080/8085 Series All Instructions 1 or 2 Cycles. Peripherals

• Over 90 Instructions: 70% Single Byte • Two Single Level Interrupts

The Intel@ B04BH/B04BH-1/B035HLlB035HL-1 are totally self-sufficient, B-bit parallel computers fabricated on single silicon chips using Intel's advanced N-channel silicon gate HMOS process,

The B04BH contains a 1 K X B program memory, a 64 X B RAM data memory, 27 I/O lines, and an B-bit timer/counter in addition to on-board oscillator and clock circuits, For systems that require extra capability the B048H can be expanded using standard memories and MCS-80Tl1/MCS-B5T11 peripherals, The B035HL is the equivalent of the 8048H without program memory and can be used with external ROM AND RAM,

To reduce development problems to a minimum and provide maximum flexibility, a logically and functionally pin compatible version of the B048H with UV-erasable user-programmable EPROM program memory is avail­able. The B74B will. emulate the B04BH up to 6 MHz clock frequency with minor differences.

The B04BH is fully compatible with the 8048 when operated at 6 MHz.

These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have extensive bit handling capability as well as facilities for' bo(h binary and BCD arithmetic. Efficient use of program memory results from an instruction set consisting mostly of single bit instructions and no in­structions over 2 bytes in length.

PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM

TO

XTAL 1 Tl PORT o 1

XTAL 2 P27 CLOCK 1024 WORDS 64 WORDS PROGRAM DATA

IiEsTt P26 MEMORY MEMORY

ss P2S PORT

INT P24 '. 2 , ;:. > EA P17

RD P16

PSEN PIS B048H WR P14 80:iSHL

ALE P13 B04BH-l 803SHL-l

B BIT CPU IY- r-

DBa P12

OB, Pll

DB2 PIa

DB3 VDD V V DB4 PROG

DBs P23

DBS P22 BUS

DB7 P21 PORT EXPANDER

B BIT 27

TIMER 1/0 LINES EVENT COUNTER

VSS P20 STROBE

Intel Corporation assumes no responsibility for the use of any circuit.ry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.

elntel Corporation 1980' AFN-01491A-01

APPENDIX A

8035/8048/8748/ and 8049 CPU SPECIFICATIONS

This appendix contains the specifications for the CPU chips that may

possibly be used with the system as its hardware design exists. Use

of the 8035 is expected to compose the bulk of the applications.

A-I

(

intel S04SH/S04SH-1 /S035HL/S035H L-1 [?)OO ~ OJfu(]O~~OOW

PIN DESCRIPTION

Designation Pin = Function Designation Pin = Function

VSS 20 Circuit GND potential testable with conditional

VDD 26 low power standby pin jump instruction.

VCC 40 Main power supply; +5V (Active low)

during operation. RD 8 Output strobe' activated during a BUS read. Can be

PROG 25 Output strobe for 8243 1/0 used to enable data onto the expander. bus from an external device.

P10-P17 27-34 8-bit quasi-bidirectional Used as a read strobe to Port 1 port. external data memory. P20-27 21-24 8-bit quasi-bidirectional (Active low) Port 2 port.

35-38 P20-P23 contain the four 'RESET 4 Input which is used to

high order program counter initialize the processor.

bits during an external pro- (Active low)

gram memory fetch and (Non TTL VI H)

serve as a 4-bit 1/0 expander WR 10 Output strobe during a bus bus for 8243. write. (Active low)

DBO-DB7 12-19 True bidirectional port Used as write strobe to BUS which can be written or read external data memory.

synchronously using the ALE 11 Address latch enable. This RD, WR strobes. The port signal occurs once during can also be statically each cycle and is useful as a latched. clock output. Contains the 8 low order The negative edge of ALE program counter bits during strobes address into ex-an external program ternal data and program memory fetch, and receives 'memory. the addressed instruction

PS'E'N 9 Program store enable. This under the control of PSEN. Also contains the address output occurs only during a

and data during an external fetch to external program

RAM data store instruction, memory. (Active low)

under control of ALE, RD, SS 5 Single step input can be and WR. used in conjunction with

TO Input pin testable using the ALE to "single step" the

conditional transfer in- processor through each

structions JTO and JNTO. TO instruction. (Active low)

can be designated as a clock EA 7 External access input which output using ENTO ClK forces all program memory instruction. fetches to reference external

T1 39 Input pin testable using the memory. Useful for emula-

JT1, and JNT1 instructions. tion and debug, and

Can be designated the essential for testing and

timer/counter input using program verification.

the STRT CNT instruction. (Active high)

INT 6 Interrupt input. Initiates an XTAl1 2 One side of c"rystal input for

interrupt if interrupt is internal oscillator. Also

enabled. Interrupt is dis- input for external source.

abled after a reset. Also (Non TTL VIH)

XTAl2 3 Other side of crystal input.

AFN-01491A-02

S04SH/S04SH-1/S035HL-1/S035HL-1

INSTRUCT~ON SET

Accumulalor

Mnemonic De,crlpllon ADD A, R Add register 10 A ADD A, @R Add data memory to A ADD A, /I data Add immediate to A ADDC A, R Add register with carry ADDC A,@R" Add dala memory with carry ADDC A, /I data Add immediale with carry ANL A, R And register to A ANL A,@R And dala memory to A ANL A, # data And immediale to A ORl A, R Or regisler 10 A ORL A@R Or data memory to A ORL A, /I data Or immediale to A XRL A, R Exclusive or register to A XRL A, @R Exclusive or data memory to A XRL, A, # data Exclusive or immediate to A INCA Increment A DECA Decrement A CLR A Clear A CPLA Complement A DAA Decimal adjust A SWAP A Swap nibbles 01 A RL A Rotate A left RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry

Input/Oulpul

Mnemonic Descrlpllon IN A, P Inpul port to A OUTL P, A Output A to port ANL p, /I data And immediate to port ORL P, /I data Or Immediate to pori INS A, BUS Inpul BUS to A OUTL BUS, A Output A to BUS ANl BUS, # data And immediate to BUS ORl BUS, /I data Or immediate to BUS MOVD A,P Input expander port to A MOVD P, A Oulput A to expander port ANLD P, A And A to expander port ORLO P, A Or A to expander port

Regiliers

Mnemonic Descrlpllon

INC R Increment register INC@R Increment data memory DEeR Decrement register

Branch

Mnemonic Descrlpllon JMP addr Jump unconditional JMPP@A Jump indirect DJNZ R, addr Decrement register and skip JC addr Jump on carry = 1 JNC addr Jump on carry = 0 JZ addr Jump on A zero JNZ addr Jump on A not zero JTO addr Jump on TO" I JNTO addr Jump on TO" 0 JTI addr Jump on Tl " 1 JNTI addr Jump on TI "0 JFO addr Jump on FO" I JFl addr Jump on Fl " I JTF addr Jump on timer flag JNI addr Jump on INT " 0 JBb addr Jump on accumulator bit

Byle, Cycle. 1 1 1 1 2 2

1 1 ;! 2

1 1 1 2 2

1 1 1 2 2

1 1 2 2

1 1

Bylel Cycle, 1 2 1 2 2 2 2 2

I 2 1 2

2 2 2 2 1 2 1 2 1 2

1 2

Byles Cyclel

1 I I 1 I I

Byles Cycles 2 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Subroullne

Mnemonic CALL addr RETR RETR

Flags

Mnemonic ClR C CPL C ClR FO CPL FO ClR FI CPL FI

Dala Moves

Mnemonic MOV A, R MOVA,@R MOV A, /I data MOV R, A MOV@R,A MOV R, /I data MOV @R, /ldata MOVA, PSW MOV PSW, A XCH A, R XCH A, @R XCHD A;@A

MOVXA,@R MOVX@R,A MOVPA,@A MOVP3A, @

Tlmer/Counler

Mnemonic MOVA, T MOV T, A STAT T STRT CNT STOP TCNT EN TCNTI DIS TCNTl

Control

Mnemonic EN I DIS I SEL RBO SEL RBI SEL MBO SEL MBI ENT 0 ClK

Mnemonic NOP

Delcrlpllon Jump to subroutine Return

Return and restore status

Description Clear carry Complement carry CLear flag 0 Complement flag 0 Clear flag I Complement flag 1

Delcrlpllon Move register to A Move data memory to A Move immediate to A Move A to register Move A to data memory Move immediate to register Move immediate to data memory Move PSW to A Move A toPSW Exchange A and register Exchange A and data memory Exchange nibble of A and register Move exlernal data memory to A Move A to external data memory Move to A from current page Move to A from page 3

Description Aead timer/counter Load timer/counier Start timer Start counter Stop timer/counter Enable>timer/counter interrupt Disable timer/counter interrupt

Descrlpllon Enable external interrupt Disable external interrupt Select register bank 0 Select register bank I Select memory bank 0 Select memory bank 1 Enable clock output on TO

Description

No operation

Bytes Cycles 2 2

2 2

Bylel Cycle. 1 1

1

Byle. Cycles 1 1 1 I 2 2

1 1 1 1 2 2 2 2 1 1 I 1 1 1 1 1

1

1 2

1 2

1 2 1 2

Byle, Cycles I I 1 1 1 1 I 1 1 1 I I I 1

Bytes Cycle. I I 1 I 1 1 1 1 1 I I 1 1 1

Byles Cycles I 1

AFN·01491 A·03

(

(

(

S04SH/S04SH-1 IS035H LlS035H L-1

A~C. CHARACTERISTICS (PORT 2 TIMING) TA = O°Cto 70°C, VCC = 5V±100f0, VSS = OV

8048H 8048H·1 8035HL 8035HL·1

Symbol Parameter 6 MHz

Min. Max.

tcp Port control Setup Before Falling 110 edge of PROG.

tpc Port Control Hold After Falling 100 Edge of PROG.

tpR PROG to Time P2 Input Must Be Valid 810

tpF Input Data Hold Tinie 0 150

tDP Output Data Setup Time 250

tpD Output Data Hold Time 65

tpp PROG Pulse Width 1200

tpL Port 2 1/0 Data Setup 350

tLP Port 2 I/O Data'Hold 150

PORT 2 TIMING

EXPANDER PORT

OUTPUT

EXPANDER PORT

INPUT

PROG

\'--___ ~V

PCH

PCH PORT 20 3 DATA

, BUS TIMING AS A FUNCTION OF TCY *

SYMBOL

TLL TAL TLA TCC (1) TCC (2) TDW TWD TDR

FUNCTION OF TCY

7/30 TCY MIN 1/10 TCY MIN 1/15 TCY MIN 1/2 TCY MIN 2/5 TCY MIN 2/15 TCY MIN 1/15 TCY MIN 0 MIN

TCC (1) : RDIWR T CC (2) : PSEN

• APPROXIMATE VALUES NOT INCLUDING GATE DELAYS.

SYMBOL

TRD (1) TRD (2) TAW TAD (1) TAD (~) TAFC TCA

8 MHz 11 MHz Unit

Min. Max. Min. Max.

105 ns

90 ns

700 650 ns

0 150 0 150 ns

210 200 ns

35 20 ns

970 700 ns

300 250 ns

65 20 ns

\'---__ ~I --1'CAr'

PORT CONTROL

,-I

PORT CONTROL

'PC--!

~. I

r'DPi'PDl

'PR

'PP

I OUTPUT DATA

.. V I

FUNCTION OF TCY

11/30 TCY 3/10 TCY 3/10 TCY 1/2 TCY 1/3 TCY 1/30 TCY 1/15 TCY

MAX MAX MIN MAX MAX MIN MIN

TRD (1) : RD TRD (2) : PSEN

TAD(1);RD TAD (2) : PSEN

AFN·OI491A·05

(

. (,

S04SH/S04SH-1/S035HL/S035HL-1

WAVEFORMS

f-oo~-__ -_-IL-L-_-I-- ICY ------·----i ALE J\ '-___ -----'I L ALEJ I L

I - i-ICC--j- ICA i--pst",

AD -------.\ I IAFC --; I-- -I i---IDR

: i FLOATING I i BUS FLOATING ~-F-LO-A-TI-NG---

I ___ IAD~~~ BUS

Instruction Fetch From External Program Memory Read From External Data Memory

ALE J L

WR

2.4V -------,.X ~:: ~ TEST POINTS -:::~:: X ..... ___ _ O.4SV ____ ....J. • - -

BUS FLOATING

Write to External Data Memory Input and Output for A.C.rests.

A.C. CHARACTERISTICS TA = O°C to 70°C VCC = VDD = 5V ± 10%, VSS = OV

Symbol Parameter

tLL ALE Pulse Width

tAL Address Setup to ALE

tLA Address Hold from ALE

tcc Control Pulse Width (PSEN, RD, WR)

tow Data Setup before WR

two Data Hold after WR

tCY Cycle Time

tOR Data Hold

tRD PSEN, RD to Data In

tAW Address Setup to WR

tAD Address Setup to Data In

tAFC Address Float to RD, PSEN

tCA Control Pulse to ALE

NOTE 1: Control outputs BUS outputs

CL = 80 pF CL = 150 pF

8048H 8048H-1 8035HL 8035HL-1

6 MHz 8 MHz 11 MHz Conditions

Min. Max. Min. Max. Min. Max. Unit (Note 1)

400 270 150 ns

75 75 70 ns

65 65 50 ns

700 490 300 ns

370 370 280 ns

80 80 40 ns CL = 20pF (NOTE 2)

2.5 1.875 1.36 f.1s

0 200 0 150 0 100 ns

500 340 200 ns

230 210 200 ns

950 650 400 ns

0 0 -1 ns

10 10 0 ns

NOTE 2: BUS High Impedance Load: 20 pF

AFN-01491A-06

(

(,

(

(

(

(

(

I REVISIONS

lIONEl LTRI DESCRIPTION DATE I APPRovED

[ 1811 E.C"-I 54 ~ I

AQ.RAM I'!.

AI~ 4 '7"~4'l,' .~ f"

5H 2-

'51-1 Z.

-=:::::.:.:...:.:.:....::..::. ________ .;.:13<-1c. .00'--

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I 6b'~I4_4_--------------------------------------------------------------------------------------------------------------, AD.RAM·lt ~H t- 14 8

~H eo. ac.. CoLI(. " I.t ~~~~------------------~O

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AD·RAM·IO

AO.RAM·e

AD. RAM.'

5H t.- AD. RAIJ.'5

AD·RAM·"

AD·RAM·'

AD·RAIJ·'l,

AD· RAM· I

~ ~ ~ At5

'2.114 .., 8 8

I... 13 It \I

, DB·' OB.e.

DB.5

!!1M I OB.~

DB·!

OB·Z

DB"

DB· I/>

OME~.E.~ '!IH 2- : R./W 5101 I

0$ ,.. c c < ~

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Vc.c: At8 '5 p:. ~ - ZII4 GMD~q ,-.0 VoL ... If' :t

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ell·AD·" . CH·AD·' ~ 'H'" eH.AD· Z-CH.AD·I CH·AD·q)

APkICA'''' _ITaq,' ... 001

KALIl

....-----i------t! ! ! ! .- CC)JTROL 80 :: qSO

'·"I:'..:!:~oOot -0011 i'

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RI" "IIC.

CL~

L I ZONE I LlRl

L i .'1 REVISIONS

DESCRIPTION I DATE [eN 54,', I

- 8 !tD sea , .... A" CH·AD·4 .. " SH 3 - -e~H . ..:,A:.::D,....-=-3------------------------------------:::,,-I4D 4Q Ii I A8

..:e~H~.~A~O,....1~------------------------------------,~+iSD 5Q '5 1 Al

AU. 04 l!a /I Atl. Z 33'1. . os ~,"------------~I-----..:.:,t' F 14LSIGoGo

" I4G

5H I J

510/ '1.

SH f.

~~~~----------------------------------__ ~~D ~ A. ClI·AD·' 11 lD At.4 1Q 1(, S A5 C.~H..:._A..:D....; .. ~~ _________________________________ ~'8 ~~~+8Qt-'-'~+_~~------_t__t_~~------~4~

- II 8D z.f! A4 CRTC.Kt5

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I,"

01t-t-,~1::::.:.:.:.~-, 08

-~CL/(. .r ~ ,&_N'" OE. ~ c c < +5V

, ";' 8'''5 Lt.' ·v H'3t.1 /I III 14 c.p

C.K OH ~ I .... H. LD

{

SCREt::Stl.. q CP AGo I ...;:D'-B.;.;.~=-="---,4-1 "74L!l114 15 ~~----~~~ Q5~------~ ~D~B~5 ______ ....;"~Dl. Qtt-l~ ____ ~,

15 I

10 ~D~B~~~ _____ 4~DI Qlr5~----~~

~D:.l:8wl __ -,-_ ..... !I<-f 0" alP 1. R 38 +'5V IJR lit. '<7

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SWIFT. eLK ., DC CARR't 10 \ AIS

s

q

ADO 14LSlct'

DO

01

Dt. 03

r-__ ~14L~~_OO ____ 1~,CLK

TC. .!1. ~ .!!. QO

~

Q/ t

Q'Z " Q~

1

vA> ~ rr 18 - '''' lot

U

~~ __________ ~~---------..:.:'5~5IR IQt-3~_+------~--_.~_+_+~------~----------_.----~ vsr..r I

~ .5\1 14 4 r--------,,~ 10 AlB 2.Q'1-:5=-+-------t---+-+-+-4-------------~t-----+----::-I

8 1 " 5

tc~~ All 01 AIO oz-., 03 A8 An ()4.

A1 233L·_ 05

Af. 0(.

,A .-I RI9 •• IIC.

S A ~---..f-~8

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5.11/-

4 ~-------------'---+--5~ C At.~ I-:-:-______________ ~I_~ 0 14L"lIf.w " 10

'0 E

:~ : 14 It

II

11

I" 15 If.

,A .::1+5\1

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RA3

.-----,t~ Z.D14L51133Qt-f.--+-...,.---~-.-+~-4--....;,..--..... --------t-----+----.:::..j t 11.14

1 4

A5 01 11

f,J 1

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DOT BIAL .Hr'3'--------------~------------____ ~~~~--

r----~3D 4at---~------t--t-~4---~--_+-----------~--_+----... ---2!. 40

1.1 .... Icn,o.

E5 IK

Eft

OEL·DI5P\...ENA I

11\ All " iSl~j5L.EN

"MLSOO

~~_+_+_+_+-----4' ~ .•

L-__ ~ ____ -+~5~~

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.A .j'-",u> ~ '4L.~ ,,.

+5V "17

RIB II(.

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..!.o Q 5 DEL CURSOR

14L50+ A11

SMIFT. CLI(.. 14L'71

3 ell. ~. I ~ ~~~~------~_+_+_+_+_+----------~_a ~~A~I~~--~

14L~4 q

CLR

TI 5_

~~ow.\O~ ~ 14L~

UIJDERLlt-lE REVERSE·YIlJEO

~-r __ ~~~_q ... ~A~~ 1___ ~_.~~I~~~ 1--1 . -, A10 3 ---.;. 14 IV.-.:4::-+-I----1....,:...---... --::14' 10 CI(. Q' ~t=_--~H~~_+---------------::~~.;;:;;.;..=-___

Z~ r-------------~~~~~"~ 1_ ~ 1 , I-f-+-+-+---~I'I A.. 3 141.S08 II l..A 2Vt-q::--t-t---i--"'-+~Go 1.D Q'lt-:,=------4~_+-+---------------=~::::::::.;.==-BL't.lK BLAt.JK.

O\SPL.EtJA 5 >'-"t---I~~~--"'--.:....j .. -----....;;...-..:---~3'A 3Yt-:::-++-+--.... f-f-:7-I30 QS~--------..... ..f-+-----------------.=:..:.:..;:.:..:....----A12'4 a.-____________________ ~14 4A 4V~I~t~_+--_+~_+_+~-~~1 4D Q.~I~O----------~-t---------------__ ~~~~-----

DEL.OI5PL·Et-l-

HALF·lt-lTEt-l5ITY 14LS.04 3 .... 20=-____________ --'--____ '':-1 I, A1.0 wD AZ' Q5 It

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11 ..... ---~4D 48 ~V 14L500 Il. At.' r"+ _____ qi>Q<.14\.$n4 STRI I' _I

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VSVt.lC ~) 14LSoa

ROW.' DISPL·EIJ-

_ICA'. ~o __ • DW.O.~_

.. ,_, _011 ~--. ""'0._ .. -.. '........... .-

311 "

511 ~

~SH w

5Hw 51014

COUTROL 80· "SO ........ -

'~..: a.-OO1 Ii

---~ -

D

c

B

A

8 7 6

'X"TALI

I" Y1tQ" u. _ ILl ~== ________ ~ ______________________________ ~~IRQ -=A=B~~~ ______ ~~ ____________________________ ~~I' R~~ ~A~B=I~ ______ ~~~ __________________________ ~I~'" R51 ~R~~ ______ ~4-~~ __________________ -+~t~~ R~

A8q .. ~~~~---+-+-r;----------------------r~C5~ ~r~o~.p~.S~E~L~ __ ~~~I-1~~----__ --______ --__ ---+~~ CSI A~

'"551

,

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.,. :

4

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ii:

3 2 REVISIONS

DESCRIPTION

ECIJ 5+

~D~B~~ ________ ~~~~~~--------__ ----~----~~le OB~ 5H I..... OBI ICJ OBI

C411

DBl. W DBl.

DB' ~ DB' DB4 Z"Z. 0 B4 DBS t3 OBS D~ « ~~ DB' 1..5 DB'

RlIO

TKO

It.

10

330 ,.. PF

(/7

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T '3rO-P~F~--------~ * Ct~.OI UF

<50=: .2. Z1 IU.

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14LS!('" q

GI.lO

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11---1 10

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I~ U. XLI

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~A~B~I~I ______ ~~HHH~~~H~_+_+_+_+_+--_+~t eso t-HH_+_+-+-+-+-+~--+....:3~ CSl

18 t-~H-4-+--+4--I-+---~~OB¢ ~r_r_r-r-~~~~~~14q OBI

W ZI OBl.

t-r-r-~~~~~~4 OB9 t-r-~~~~~~z~t DB4 t-~H_4---+-~~DB5 .-~~ __ ~~Z4~DB~

..... r-r-_r-Z5~DB' t1 02

t--I--4~RE,et

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R'30 510A 'fl,W -A

Of to +;' 115

14L50S DTR~I~I------+_----_, , 1m 1-8=--____ -+_..,

1'.0 MOO TXD~I~O------_+--_+--_r~r-----_1----~~~----~------~------~----------~ RlIC !-=-5 ____ _+--_+-_+H~---~--_~++----~----...:..J 1~3t 11--__ ....:.::12:.{, -1--""""" 1\ TltO

I, , " A48 rp..:..:--------..--------~~-:..:....::~4 OSR ~-----+~4_-~-' t AS8 ----./ 1488 1 . L-- C!il '

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OCO LI-"------~_+_+--_+--------H----++4_----~----------_+--~ L.....-j,-- 330 PF r 5 74L!I32 r--__ ~4..f

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,

1150 '"55"1

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11_. rl I--< C45

IzIA3q~~II~----------~J~ __ --+_-3-30--P-F----~R~.~D~" ....---~ 1"88 14LS'2

13 It 4 ~48 ASq 4Y~-----;-----r------------~--------------~~------------~~

..... ~~~~IO~4A 74LS157 5 A48

rl--< 1'188

C55 330 PF

OTR "

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