tpHL tpLH

t

t

Vin

Vout

50%

50%

tr

10%

90%

tf

7.3 Power Dissipation

= VDD is assumed a constant, so we look to IDD

Two currents: DC and Dynamic (switching) give two components to the power:

= +

Ideally PDC is zero (unless the inverter is switching), but in reality there are leakage currents, which we call the Quiescent Current IDDQ.

Dynamic Power Dissipation Pdyn:

How do we compute the switching current?

7.4 DC Characteristics: NAND and NOR Gates

7.4.1 – NAND Analysis

Three possible transitions -> Three distinct VTCs To understand this better, we will now calculate VM for the case of simultaneous switching

Now plugging in the and relationships from our equivalent inverter, we solve for VM as before, by equating the two saturation currents when = = :

7.4.2 NOR Gate

By the same arguments, the NOR series and parallel FETs can be combined, and again we can calculate the VM for the simultaneous switching case

7.5 NAND and NOR Transient Response

7.5.1 NAND2 Switching Times

Concentrate on the worst-case values for switching times and find the values

NAND2 Rise time: Worst case, only 1 pFET is conducting:

If both pFETs are conducting then the equivalent resistance is lowered to ( 2⁄ ) – which would be a “best case” scenario with the shortest charging time.

NAND2 Fall time: The situation is complicated by the presence of the inter-FET capacitance CX. The worst case is when CX also has a charge that will flow through the MnA nFET to GND.

Elmore Formula:

Picture an RC circuit as a tree where the voltage source is the roots and the leaves are the capacitances at the end of branches:

The Elmore delay model estimates the delay from a source switching to one of the “leaf” nodes as the sum over each node i of the capacitance Ci of the node multiplied by the effective resistance Ris of the shared path from the source to the node to the “leaf”:

= ∑

7.5.2 NOR2 Switching Times

NOR2 Fall Time:

NOR2 Rise Time:

7.5.3 Summary fan-in (FI): The number of inputs connected to a logic gate. Complementary pairs increase the switching time since CFET is increased. Switching delays increase with:

Fan-In External Loads

And the layout geometry (i.e. series vs. parallel) affect the transient response