9. datapath design - university of texas at austinjaa/vlsi/lectures/9-1.pdf · 2019-09-26 · 9....
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9. Datapath Design
Jacob Abraham
Department of Electrical and Computer EngineeringThe University of Texas at Austin
VLSI DesignFall 2019
September 26, 2019
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1s and 0s Detectors
1s detector: N-input AND gate
0s detector: Inversions + 1s detector (N-input NOR)
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Comparators
Equality Comparator
Check if each bit is equal(XNOR, or “equalitygate”)
1s detect on bitwiseequality
Magnitude Comparator
Compute B −A and lookat sign
B −A = B +A+ 1
For unsigned numbers,carry out is sign bit
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Signed Versus Unsigned Numbers
For signed numbers, comparison is harder
C: carry outZ: zero (all bits of A-B are 0)N: negative (MSB of result)V: overflow (inputs had different signs, output sign 6= B)
Magnitude Comparison
Relation Unsigned Comparison Signed Comparison
A = B Z Z
A 6= B Z Z
A < B C + Z (N ⊕ V ) + Z
A > B C (N ⊕ V )
A ≤ B C (N ⊕ V )
A ≥ B C + Z (N ⊕ V ) + Z
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Shifters
Logical Shift:Shifts number left or right and fills with 0s
1011 LSR 1 = 01011011 LSL 1 = 0110
Arithmetic Shift:Shifts number left or right; right shift – sign extend
1011 ASR 1 = 11011011 ASL 1 = 0110
Rotate:Shifts number left or right and fills with lost bits
1011 ROR 1 = 11011011 ROL 1 = 0111
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Funnel Shifter
A funnel shifter can do all six types of shifts
Selects N-bit field Y from 2N-bit input
Shift by k bits (0 ≤ k < N)
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Funnel Shifter Operation
Shift Type B C Offset
Logical Right 0 . . . 0 AN−1 . . . A0 k
Logical Left AN−1 . . . A0 0 . . . 0 N − kArithmetic Right AN−1 . . . AN−1
(sign extension)AN−1 . . . A0 k
Arithmetic Left AN−1 . . . A0 0 N − kRotate Right AN−1 . . . A0 AN−1 . . . A0 k
Rotate Left AN−1 . . . A0 AN−1 . . . A0 N − k
Computing N-k requires an adder
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Simplified Funnel Shifter
Optimize down to 2N-1 bit input
Shift Type Z Offset
Logical Right 0..0, AN−1 . . . A0 k
Logical Left AN−1 . . . A0, 0..0 k
Arithmetic Right AN−1 . . . AN−1, AN−1 . . . A0 k
Arithmetic Left AN−1 . . . A0, 0..0 k
Rotate Right AN−2 . . . A0, AN−1 . . . A0 k
Rotate Left AN−1 . . . A0, AN−1 . . . A1 k
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Funnel Shifter Design – 1
N N-input multiplexersUse 1-of-N hot select signals for shift amountnMOS pass transistor design (Note: Vt drops)
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Funnel Shifter Design – 2
Log N stages of2-input MUXes
No selectdecoding needed
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Multi-Input Adders
Suppose we want to add k N-bit wordsExample: 0001 + 0111 + 1101 + 0010 = 10111
Straightforward solution: k-1 N-input CPAsLarge and slow
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Carry Save Addition
Full adder sums 3 inputs, produces 2 outputsCarry output has twice the weight of sum output
N full adders in parallel: carry save adderProduce N sums and N carry outs
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CSA Application
Use k-2 stages of CSAsKeep result in carry-save redundant form
Final CPA computes actual result
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Parity Generators
Static XOR Tree
Dynamic XOR Circuit
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Pass Gate Comparator
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Multiplication
Example:
M x N-bit multiplication
Produce N M-bit partial productsSum these to produce M+N-bit product
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General Form for Multiplication
Multiplicand: Y = (yM−1, yM−2, . . . , y1, y0)Multiplier: X = (xN−1, xN−2, . . . , x1, x0)Product:
P =
M−1∑j=0
yj2j
(N−1∑i=0
xi2i
)=
N−1∑i=0
M−1∑j=0
xiyj2i+j
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Dot Diagram
Each dot represents a bit
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Array Multiplier
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Rectangular Array
Squash array to fit rectangular floorplan
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Fewer Partial Products – Booth Encoding
Array multiplier requires N partial products
If we looked at groups of r bits, we could form N/r partialproducts
Faster and smaller?Called radix-2r encoding
Example, for r = 2, look at pairs of bits
Form partial products of 0, Y, 2Y, 3YFirst three are easy, but 3Y requires adder
Is there a way to get 3Y without an addition step?
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Booth Encoding
Instead of 3Y, try -Y, then increment next partial product toadd 4Y
Similarly, for 2Y, try -2Y + 4Y in next partial product
Radix-4 modified Booth encoding value
Inputs Partial Product Booth Selects
x2i+1 x2i x2i−1 PPi Xi 2Xi Mi
0 0 0 0 0 0 0
0 0 1 Y 1 0 0
0 1 0 Y 1 0 0
0 1 1 2Y 0 1 0
1 0 0 -2Y 0 1 1
1 0 1 -Y 1 0 1
1 1 0 -Y 1 0 1
1 1 1 -0(=0) 0 0 1
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Advanced Multiplication
Signed vs. unsigned inputs
Higher radix Booth encoding
Array vs. tree CSA networks
Serial Multiplication
Lower area at expense of speed
Example, signal processing on bit streams
Delay for n× n multiply
2n bit product with 2n bit delayAdditional n-bit delay to shift n bitsTotal delay of 3n bits
Pipelined multiplier: possible to produce a new 2n bit productevery 2n bit times after initial n bit delay
Only interest in high-order bits: n bit latency for n bit productCan design for desired throughput
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Serial Multiplier Architecture
Area for structure increases linearly with number of bits, n
Pipeline multiplier accumulates partial product sums starting withthe least significant partial product (result is n-bit number which istruncated to n-1 bits before the next partial product)
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Division
To divide A by BShift P and A one bit leftSubtract B from P, put the result backIf result is negative, additional steps, set low order bits of A to0, otherwise to 1“restoring” or “non-restoring” division to fix negative result
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SRT Division
Divide A by B (n-bits)(view numbers as fractions between 1/2 and1)
1 If B has k leading 0s when expressed using n bits, shift allregisters by k bits
2 For i = 0 to (n-1)
1 If top 3 bits of P equal, set qi = 0, shift (P,A) one bit left2 If top 3 bits of P not all equal, and P negative, set qi = −1,
(written as 1, shift (P,A) one bit left and add B3 Otherwise, set qi = 1, shift (P,A) one bit left, subtract B
3 If the final remainder is negative, correct by adding B, correctquotient by subtracting 1; finally, shift remainder k bits right
Radix-4 SRT algorithm used in Pentium chip
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Floating Point (IEEE 754-1985)
Single precision:N = (−1)sign × 1.Significand× 2Exponent−127, 1 ≤ Exponent ≤ 254N = (−1)sign × 0.Significand× 2Exponent−126,Exponent = 0
“Hidden 1”, Bias, Special values NaN, ∞, −∞Rounds to nearest by default, but three other rounding modes
“Halfway” result rounded to nearest even FP number
“Denormal” numbers to represent results < 1.0× 2Emin
Sophisticated facilities for handling exceptionsECE Department, University of Texas at Austin Lecture 9. Datapath Design Jacob Abraham, September 26, 2019 26 / 27
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Iterative Division
Newtons iteration: finding the 0 of a function
Starting from a guess for the 0, approximate function by itstangent at the guess, form new guess based on where tangenthas a 0
Goldschmidt’s method
To compute a/b, iteratively, multiply both numerator anddenominator by r where r × b = 1
Find r iteratively
Scale the problem so b < 1
Set x0 = a, y0 = b and write b = 1− δ where |δ| < 1
If we pick r0 = 1 + δ, then y1 = r0y0 = 1− δ2
Next, pick r1 = 1 + δ2, etc., and yi → 1
Used in the TI 8847 chip and AMD Athlon CPUs
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