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A Novel Bidirectional DC-DC Converter with ZVSand Interleaving for Dual Voltage Systems in

AutomobilesPhilip Jose Ned Mohan

Department of Electrical Engineering

University of Minnesota

200 Union Street SE

Minneapolis, MN 55455, USA

philip@ece.umn.edu mohan@ece.umn.edu

Abstract—This paper presents a novel bidirectional dc-dc con-verter for 42V/14V dual voltage systems in automobiles. The con-verter uses Clamped Zero voltage Switching to minimize loses, andinterleaving for reduced current ripple. SABER simulations arepresented to verify the design. The simulation results are con-firmed by hardware implementation.

I. INTRODUCTION

The requirement of a higher electrical system voltage in au-tomobiles has now been widely acknowledged ([1]), and effortsare on to formulate standards for the same. The MIT/IndustryConsortium for Advanced Automotive Electrical/ElectronicComponents and Systems led by the Massachusetts Institute ofTechnology, Boston has chosen 42 volts as the preferred electri-cal system voltage for automobiles of the future. In the short runhowever, it is proposed for new automobiles to have two volt-age systems onboard till the components and technology for 42V systems are fully developed. Several architectures are stud-ied for managing two voltage systems in an automobile, manyof them requiring a bidirectional dc-dc converter which inter-faces the 42 V and the 14 V electrical subsystems. This paperexplores the possibility of using a simple buck converter featur-ing clamped Zero Voltage Switching [2] for reduced switchinglosses so that the converter can be run at high switching fre-quencies. To circumvent the problem of high current ripple inthe proposed ZVS scheme, a number of such converters can beinterleaved. Output current sharing for the converters is basedon the scheme proposed by [3].

Section II describes the design of the converter. Experimentalresults are presented in section III.

II. DESIGN

The converter outline is shown in Fig. 1. N converters con-nected in parallel transfer power between the 42 V bus and the14 V bus. The voltage error is amplified by the voltage con-troller, which generates a current reference. This current refer-ence is equally shared by the current controllers . That is, thecurrent reference divided by the number of converters is givento each current controller. Each converter then works in aver-age current control. The inner current control loop is designed

using average model analysis of power converters. H∞ control[4] is used to design a robust current controller which is insen-sitive to fluctuations in the input voltage. Further, input voltagefeed forward is used to improve the response of the converter soas to avoid high startup currents. The converters are interleavedso as to reduce the ripple in output current.

Fig. 1. Outline of Converter

A. Controller Design

The converter has an inner current loop to facilitate currentsharing across several parallel converters. The current con-troller has to be insensitive to fluctuations in the input and out-put voltages, and also the load, which is essentially the internalresistance of the 12 V battery. To achieve these goals, H∞control is used with appropriate weighting functions. First, theconverter is modeled in an average sense [5] with the duty ratiocommand as input, and the input and output voltages as dis-turbances (see Fig. 2). The effect of switching frequency ismodeled as a noise input which adds on to the current output.The weighting functions are chosen so as to give a high steadystate open loop gain, and also to make the controller insensitiveto switching frequency. Hence the weighting function Wn is acascade of two transfer functions, as given in eq. 1, one to in-crease sensitivity at low frequency, and the other to decrease the

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sensitivity at the switching frequency. A weighting function isalso added to the measured inductor current to model the band-width of measurement circuit. The chosen weighting functionsare:

Wn =1.5 × 10−11s2 + 0.00021s + 0.15

1 × 10−10s2 + 0.0028s + 1×

5.674 × 10−13s2 + 1.337 × 10−5s + 0.074.053× 10−13s2 + 1.91 × 10−6s + 1

Wi = 1Wo = 1

Wz =1

1.592 × 10−7s + 1(1)

Fig. 2. Current controller design

The controller is designed using MATLAB and the sub-optimal controller Kc is reduced in order to yield a third-ordercontroller.

In order to avoid transient high currents, hysteresis controlis added which kicks in when the inductor current goes aboveor below the operating region (see Fig. 3). Further, the inputvoltage is sensed to predict the duty cycle. For the converter,

Vo = DVin (2)

where Vo is the output voltage

Vin is the input voltage

and D is the duty cycle

Now, Vin can be expressed as a variation ∆Vin about a nom-inal Vin,nom. That is,

Vin = Vin,nom + ∆Vin (3)

(4)

Eq. 3 can then be rewritten as

D =Vo

Vin,nom + ∆Vin

=Vo

Vin,nom

11 + ∆Vin

Vin,nom

≈ Vo

Vin,nom(1 − ∆Vin

Vin,nom)

=2Vo

Vin,nom− VoVin

V 2in,nom

(5)

The expression for duty ratio obtained in Eq. 5 is used to pre-dict the nominal duty cycle about which the controller operates.

Fig. 3. Hysteresis control for current limiting

Fig. 4. Duty cycle feedforwarding

B. Zero Voltage Switching

In order to reduce switching losses and improve efficiencyof the converter,the converter uses Zero Voltage Switching withswitch voltage clamped to the input voltage as shown in Fig.5. As switch T1 is turned off, the inductor current charges ca-pacitor C1 to input voltage and discharges C2 to zero voltagewhen the antiparallel diode of T2 starts conducting. Switch T2can then be turned on. The value of the capacitances and thedead-time between the high and low side gate pulses are criti-cal to obtain proper ZVS operation. Another constraint is thatthe inductor current has to reverse in each cycle so that ZVSis effective when T2 is turned off and T1 is turned on. Thisthen means that the inductor peak-peak ripple has to be a littlemore than double the maximum average current expected. Thislarge ripple is indeed a problem, which however is alleviated byinterleaving.

Fig. 5. Clamped Zero Voltage Switching Power Circuit

The circuit was simulated using SABER to determine the val-ues of capacitors C1 and C2, and the deadtime which gave opti-mum performance. Zero Voltage Switching Waveforms for the

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lower MOSFET are given in Fig. 6.

Fig. 6. Simulation results of Clamped Zero Voltage Switching of Lower MOS-FET

C. Interleaving

As mentioned in the previous section, proper ZVS operationrequires that inductor current flows in either direction in eachcycle, which necessitates large inductor current ripple. How-ever, by paralleling several converters and phase shifting theirgate pulses appropriately, this ripple can be reduced to a greatextend. Hence a programmable delay circuit is incorporatedinto the gate drive of the converter.

D. Voltage controller

Once the design of the current controller was completed, theouter voltage loop can be designed. Since the current loop ismuch faster than the voltage loop, it could be assumed that theinductor current is exactly same as the current reference. Asimple integral converter suffices for voltage control so that thesteady state error was zero.

III. IMPLEMENTATION AND EXPERIMENTAL RESULTS

The converter was built in two parts: a voltage board, whichgenerated the current reference, and also the master clock, andseveral current controlled ZVS converter boards which wereconnected in parallel.

A. Zero Voltage Switching

The converter was first tested to see if Zero Voltage Switch-ing was functioning properly. Figures 7 and 8 shows the lowerMOSFET gate-source and drain source voltages, during no-load and full-load operation. The MOSFET drain-source risesonly after the gate-source voltage (i.e., drain current) fall to

zero, and the drain-source voltage falls to zero before the gate-source voltage starts to rise, indicating zero voltage turn on andzero current turn off.

Fig. 7. Clamped Zero Voltage Switching during no load

Fig. 8. Clamped Zero Voltage Switching during full load

B. Current Loop

The current controller was implemented using a linearOPAMP circuit. The step response of the current loop is shownin Fig. 9. Fig. 10 shows that the controlled inductor current isinsensitive to a disturbance in input voltage.

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Fig. 9. Step response of current loop

Fig. 10. Effect of input voltage fluctuation

C. Interleaving

Two converters were interleaved to observe the effect on out-put ripple current. Fig. 11 shows the results of the experiment,with the delay between the two boards set to half the switchingtime. There is significant reduction in ripple current. The ripplewould be even lower with more converters in parallel.

Fig. 11. Effect of interleaving on output current ripple

IV. CONCLUSION

A bidirectional converter for use in dual voltage systems inautomobiles is presented. Zero Voltage Switching and out-put current interleaving are implemented for reduced switchinglosses and current ripple. Interleaving also helps to modularizethe converter design for use in higher power applications. Thedesign was carried out using MATLAB and verified by SABERsimulations. Experiment observations confirm simulation re-sults.

REFERENCES

[1] Kassakian, J. G, ”Automotive Electrical Systems - The Power ElectronicMarket of the Future”, APEC 2000, vol. 1, pp 3-9.

[2] Henze, C. P, Martin, H. C and Parsley, D. W, ”Zero-Voltage Switchingin High Frequency Power Converters using Pulse Width Modulation”,APEC 1988, pp 33-40.

[3] Bhinge, A., Mohan N., Giri, R. and Ayyanar R., ”Series-Parallel Connec-tion of DC-DC Converter Modules with Active Sharing of Input Voltageand Load Current”, APEC 2002.

[4] Zhou, K., ”Essentials of Robust Control”, Prentice Hall, 1998[5] Nirgude, G., Tirumala, R., Mohan, N., ”A new, large-signal average

model for single-switch DC-DC converters operating in both CCM andDCM”, Power Electronics Specialists Conference, 2001. PESC. 2001IEEE 32nd Annual, Volume: 3 , 2001

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