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#

TL850 Preliminary Register Manual

Version 2.0

July, 1999

TERALOGIC CONFIDENTIAL - DO NOT COPY

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Copyright 1999, 1998, 1997 TeraLogic, Inc.

All rights reserved worldwide.

This register manual contains information that is confidential to TeraLogic, Inc. and is subject

to the terms and conditions, including confidentiality obligations, set forth in the applicable

Nondisclosure Agreement and/or License Agreement between Teralogic, Inc. and User.

Information herein is subject to change without notice. TeraLogic, Inc. assumes no

responsibility for any use of, or reliance on, the information contained herein.

THIS REGISTER MANUAL AND ALL INFORMATION CONTAINED HEREIN IS

PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS,

IMPLIED, STATUTORY, OR OTHERWISE. TERALOGIC, INC. AND ITS SUPPLIERS

SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY,

NONINFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE.

TeraLogic and the TeraLogic logo are trademarks of TeraLogic, Inc. All other trademarks arethe properties of their respective owners.

TeraLogic, Inc.

1240 Villa Street

Mountain View

CA 94041-1124

Tel. : (650) 526-2000

Fax. : (650) 526- 2006

Doc#PD-850-PM-001-02

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TERALOGIC CONFIDENTIAL - DO NOT COPYJuly 1999 Rev.2.0 Doc#PD-850-PM-001-02

This material is confidential and is provided under an existing NDA

TL850 Register Manual

The following document is the TL850 Register Manual which is provided as a reference for a pro-

grammer using the TL850 IC from Teralogic Inc. The interface through which the TL850 can beprogrammed is through the device drivers and Application Programmers Interface (API) pro-

vided by Teralogic Inc. It is recommended that a programmer gets familiarized with the devicedrivers and the API before attempting to modify the TL850 software. Developing device driversusing only the Register Manual is not recommended. Some features of the TL850 are only

accessible through the device driver and API, since this provides the only framework in which

Teralogic Inc. can ensure compliance of end-product to digital TV standards. If an application,which requires non-standard driver functionality, needs to be developed, contact Teralogic Inc.before attempting the change.

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TERALOGIC CONFIDENTIAL - DO NOT COPY July 1999 Rev.2.02


1.0 PCI CONFIGURATION REGISTERS

PCI configuration registers within the TL850 are implemented according to the PCI Specification

2.2 They are accessed by the Host bridge PCI master. The PCI Specification (Revision 2.2)describes the Configuration Space used by the system to identify and configure each device

attached to the bus. The Configuration Space contains a 256-byte address space for each deviceand has sufficient information for the system to identify the capabilities of the device. The soft-

ware executes a special configuration cycle to allow access to these registers.

Certain values in the configuration register must be loaded by an external NVRAM. On power-up, some default settings might be reprogrammable. The following chart shows whether the reg-

ister value must be loaded by NVRAM (NV), or have a hard coded (HC) value, or is reprogram-mable (REP) during system operation. Values loaded by NVRAM must be available prior to

system BIOS boot-up.

Table 1.1: PCI Configuration Registers - HIF

Register Location

Volatility HEXBits R/W Description

Default

(HEX)

HC 0x00000

0x00001

0x00002

0x00003

15:0

31:16

R

R

Vendor ID

Device ID

035f544C

REP 0x00004

0x00005

0x00006

0x00007

15:0

31:16

R/W

R/W

Status

Initialize to 0000 0010 0011 0000b.

Set bit 4 to 1, thus indicating that New Capabilities

are supported.

Bits 10, 9, 7:0 are RO. Write a 1 to clear. See PCI

2.1 Specification for details.

Command

2300000

HC 0x00008 7:0 R Revision ID 4800001

NV 0x00009 7:0 R Class Code

NV 0x0000A 7:0 R Sub Class

NV 0x0000B 7:0 R Base Class

REP 0x0000C 7:0 R Cache Line Size

Initialize to 0 after Reset

0

NV 0x0000D 7:0 R/W Latency Timer

NV 0x0000E 7:0 R Header Type

HC 0x0000F 7:0 R BIST (not Implemented)

REP 0x000100x00013

31:0 R/W Base Address for MIF (Memory Interface)Bits [31:26] programmable

80000000

NV 0x00014

0x0001B

31:0 Reserved

Additional Base Address Registers

0

NV 0x0001C

0x0001F

31:0 R/W Base Address for HIF (Host Interface)

Bits [31:20] programmable

40000000

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TERALOGIC CONFIDENTIAL - DO NOT COPYJuly 1999 Rev.2.0 3


NV 0x00020

0x00023

31:0 R/W Base Address for TSD (Transport Stream

Demultiplexer)

Bits [31:16] programmable

10000000

NV 0x00024

0x00027

31:0 Reserved

Additional Base Address Registers

0

NA 0x00028

0x0002B

Reserved 0

NV 0x0002C

0x0002D

15:0 R Subsystem Vendor ID

This value is initialized to 0. Optionally it can be set

from NVRAM prior to any read from the system

BIOS accessing PCI Configuration Space. If there

is no NVRAM available the value remains set to 0.

0

NV 0x0002E

0x0002F

31:16 R Subsystem ID (Same as Subsystem Vendor ID

above)

HC 0x00030

0x00033

31:0 R NOT USED (Expansion ROM Address) 0

HC 0x00034 7:0 R Capabilities Pointer 48

HC 0x00035

0x00037

31:08 R Reserved

HC 0x00038

0x0003B

31:0 R Reserved 0

REP 0x0003C 7:0 R/W Interrupt Line 4040100

REP 0x0003D 15:8 R Interrupt Pin

A alue of 1 indicates INTA#.

NV 0x0003E 23:16 R Min_Gnt

Thiz is used for specifying how long of a burstperiod the device needs assuming a clock rate of

33 MHz.

NV 0x0003F 31:17 R Max Lat

This is used for specifying how often the device

needs to gain access to the PCI bus.

REP 0x00040 7:0 TRDY Timeout Value 8080

REP 0x00041 15:8 Retry Timeout Value

0x00042

0x00043

31:16 R Reserved

0x000440x00047

31:0 R Reserved 0

Table 1.1: PCI Configuration Registers - HIF (cont.)

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HC 0x00048 7:0 R Capabilities ID 220001

HC 0x00049 15:8 R Next Item Pointer

Only power management function is supported

HC 0x0004A

0x0004B

31:16 R PMCPower Management Capabilities

Set to 0000 0000 0010 0010b

Bits 15:11 with 00000b

PME# is not supported

Bit 10 to a 0

D2 Power State is not supported

Bit 09 to a 0

D1 Power State is not supported

Bits 08:06 to a 000b (these bits are reserved)

Bit 05 to a 1

Device Specific. Device must be initialized after

entering D0.

Bit 04 to a 0 (ignore this bit)

External Strap is specific to supporting PME#. Bit

03 to a 0

Related to a PME Clock. Ignore this bit.

Bit 02:00 to a 010b

The TL850 is compliant to Rev 1.1 of the PCI

Power Management Interface Specification.

REP 0x0004C

0x0004D

15:0 R/W PMCSRPower Management Control/Status1

Set to 00000000000000xxb

Bit 15 to a 0; PME_status is irrelevant.

Bits 14:13 to a 00b

The Data Register is not required.

Bits 12:09 to a 0000b

The Data Register is not required.

Bit 08 to a 0

PME is not supported.

Bits 7:2 to 000000b (these bits are reserved)

Bits 01:00 depend on current state of the TL850.

If AWAKE (D0) set bits 01:00 to 00b

If Sleeping (D3) set bits 01:00 to 11b

D1 and D2 are not supported.

0

HC 0x0004E 23:16 R PMCSR PCI to PCI Bridge Support Extension

indicates PCI to PCI bridge is not supported

00

HC 0x0004F 31:24 R Data Register is not supported. 00

REP 0x00050

0x00053

31:0 Software Reset

If bit 1 =1, assert chip reset; if = 0, no reset

(default). When asserted, the TL850 is reset identi-

cally to the effect of RSTn pin, with the exception ofPLLs, DLL, PCI infc.

0

REP 0x00054

0x00057

31:0 NVRAM Programming Enable

If bit 1 = 1, NVRAM programming enabled; if = 0,

not enabled (default). When enabled, the NVRAM

can be programmed through the NVRAM register.

0

1. This value is initialized to the value indicated in the chart; but it is re-initialized to the value stored in the

External NVRAM prior to normal operation.

Table 1.1: PCI Configuration Registers - HIF (cont.)

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1.1 HOST BUS REGISTER MAP

The TL850 has eight address spaces selected by separate internal bank selects. There are sep-

arate address space for main memory through MIF, internal RAM testing and for the configura-tion registers. The first 40 Kword location are reserved for TL850 Registers and internal RAM

space.

.

1. Access to these registers is through device drivers and API provided by Teralogic Inc.

Table 1.2: Host Bus Register Map

PCI ADDR[19:0]Target

ModuleSize (32-Bit Word) Decode

0x000000x00FFF HIF 1024 0000 0000 XXXX XXXX XXXX

0x010000x01FFF VSC 1024 0000 0001 XXXX XXXX XXXX

0x020000X02FFF Note1 1024 0000 0010 XXXX XXXX XXXX

0x030000x03FFF APU 1024 0000 0011 XXXX XXXX XXXX

0x040000x04FFF BLT 1024 0000 0100 XXXX XXXX XXXX

0x050000x05FFF PLL/DLL 1024 0000 0101 XXXX XXXX XXXX

0x060000x06FFF Note1 1024 0000 0110 XXXX XXXX XXXX

0x070000x07FFF Note1 1024 0000 0111 XXXX XXXX XXXX

0x080000x0FFFF Note1 8192 0000 1XXX XXXX XXXX XXXX

0x100000x17FFF DPC 8192 0001 0XXX XXXX XXXX XXXX

0x180000x1FFFF Note1 8192 0001 1XXX XXXX XXXX XXXX

0x200000X27FFF TSD 8192 0010 0XXX XXXX XXXX XXXX

0x280000X28FFF MIF 8192 0010 1XXX XXXX XXXX XXXX

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2.0 REGISTER MAP

The following table is a summary of all the registers in the TL850 IC. The addresses mentioned in

the Base + Offset Address column are absolute byte addresses. The Base Address in the Reg-ister Name column are provided for completeness. Reserved registers are not mentioned in the

table. Hence, consecutive registers in the table may not have consecutive addresses.

Register Name Base + Offset Address Page #

HIF Registers (Base Address : 0x00000)

HIF Interrupt Status Register (HIF_INT0_STAT_REG) 0x00000 page 13

HIF Interrupt Mask Register (HIF_INT0_MASK_REG) 0x00004 page 14

HIF RAM Test Register (HIF_RAM_TEST_REG) 0x00010 page 15

HIF Hinted Address Register (HIF_HINTED_ADDR_REG) 0x00014 page 16

HIF Hinted Address Register (HIF_HINTED_ADDR_REG) 0x0001C page 16

HIF DMA Source Address Register (HIF_DMA_SRCADDR_REG) 0x00020 page 18

HIF DMA Destination Address Register (HIF_DMA_DSTADDR_REG) 0x00024 page 19

HIF DMA Count Register (HIF_DMA_COUNT_REG) 0x00028 page 20

HIF DMA Control Register (HIF_DMA_CTRL_REG) 0x0002C page 21

HIF Reserved Registers 0x000300x000FF page 22

VSC Registers (Base Address : 0x01000)

Video Channel Control Register (VSC_CTRL_REG) 0x01000 page 24

Video Channel Status Register (VSC_STAT_REG) 0x01004 page 25

VSC Interrupt Enable Register (VSC_INT_EN_REG) 0x01008 page 26

VSC Interrupt Status Register (VSC_INT_STAT_REG) 0x0100C page 27

VSC Memory Interface Control Register (VSC_MIF_REG) 0x01010 page 28

VSC Horizontal DDA Control Register (VSC_DDA_REG) 0x01014 page 29

VSC Horizontal Scaler Control Register (VSC_HS_REG) 0x01018 page 30

VSC Field 0 VBI Data Capture Control Register (VSC_VBI0_REG) 0x0101C page 31

VSC Field 1 VBI Data Capture Control Register (VSC_VBI1_REG) 0x01020 page 32

VSC VBI Data Buffer Start Address (VSC_VBUF_SADR_REG) 0x01024 page 33

VSC VBI Data Buffer Write Address (VSC_VBUF_WADR_REG) 0x01030 page 34

VSC Software Reset Register (VSC_SW_RESET_REG) 0x01030 page 35

APU Registers (Base Address : 0x03000)

Input, Output and Clock Configuration Register

(APU_IOC_CONFIG_REG)

0x03000 page 37

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Capture and Playback Configuration Register

(APU_CPB_CONFIG_REG)

0x03004 page 38

IEC-958 Configuration Register (APU_IEC_CONFIG_REG) 0x03008 page 39

IEC958 Channel Status Buffer 1 Registers (APU_IEC_CSB1_REG) 0x0300C page 40

IEC958 Channel Status Buffer 2 Registers (APU_IEC_CSB2_REG) 0x03010 page 41

Interrupt Configuration Register (APU_INT_CONFIG_REG) 0x03014 page 42

Interrupt Status Register (APU_INT_STATUS_REG) 0x03018 page 43

Capture/Playback Begin Address Register (APU_CPB_CBA_REG) 0x03020 page 44

Capture/Playback End Address Register (APU_CPB_CEA_REG) 0x03024 page 45

Capture/Playback Write Address Register (APU_CPB_CWA_REG) 0x03028 page 46

Capture/Playback Read Address Register (APU_CPB_CRA_REG) 0x0302C page 47

Capture/Playback Match Address Register (APU_CPB_CMA_REG) 0x03030 page 48

Internal Audio 0 Begin Address Registers (APU_IAU_IBA0_REG) 0x03034 page 49

Internal Audio 0 Read Address Registers (APU_IAU_IRA0_REG) 0x03038 page 50

Internal Audio 0 End Address Registers (APU_IAU_IEA0_REG) 0x0303C page 51



Internal Audio 1 End Address Registers (APU_IAU_IEA1_REG) 0x03048 page 54

Internal Audio 2 Begin Address Registers (APU_IAU_IBA2_REG) 0x0304C page 55



Mix Configuration Register (APU_MIX_CONFIG_REG) 0x03058 page 58

Cross-fade Coefficient Registers (APU_MIX_XFCn_REG; n=0 to 8) 0x0305C0x0307C page 59

BLT Registers (Base Address : 0x04000)

Channel S0 Configuration Register (BLT_CHAN_S0_REG) 0x04000 page 61

S1 Channel Configuration Register (BLT_CHAN_S1_REG) 0x04004 page 62

Destination Channel Configuration Register (BLT_CHAN_D_REG) 0x04008 page 63

BitBlt Command Register (BLT_CMD_REG) 0x0400C page 64

Mode Register (BLT_MODE_REG) 0x04010 page 65

Interrupt Status Register (BLT_INTR_STAT_REG) 0x04014 page 66

Channel S0, Left Address Register of First Line Address Processed

(BLT_LEFT_ADDRESS_S0_REG)

0x04018 page 67

Channel S0, Right Address Register of First Line Address Processed

(BLT_RIGHT_ADDRESS_S0_REG)

0x0401C page 68


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Channel S1 Left Address Register of First Line Processed


0x04020 page 69

Channel S1 Right Address Register of First Line Processed


0x04024 page 70

Channel D Left Address Register of First Line Processed

(BLT_LEFT_ADDRESS_D_REG)

0x04028 page 71

Channel D Right Address Register of First Line Processed

(BLT_RIGHT_ADDRESS_D_REG)

0x0402C page 72

Pitch Size for Channel S0 (BLT_S0_PITCH_SIZ_REG) 0x04030 page 73


Pitch Size For Channel D (BLT_D_PITCH_SIZ_REG) 0x04038 page 75

Bitmap Size (BLT_H_W_REG) 0x0403C page 76

Link List Address (BLT_LINK_ADDR_REG) 0x04040 page 77

Foreground Register S0 (BLT_S0_FG_COLOR_REG) 0x04044 page 78

Background Register S0 (BLT_S0_BG_REG) 0x04048 page 79

Foreground Register S1 (BLT_S1_FG_COLOR_REG) 0x0404C page 80


Alpha Parameters (BLT_ALPHA_REG) 0x04054 page 82

BLT Programmable Register (BLT_PROG_REG) 0x04058 page 83

BLT Pace Line Register (BLT_PACE_LINE_REG) 0x0405C page 84

PLL Registers (Base Address : 0x05000)

System Clock PLL Register (PLL_SYSCLK_REG) 0x05000 page 86

Memory Clock PLL Register (PLL_MIFCLK_REG) 0x05400 page 87

Display Processor Clock PLL Register (PLL_DPCCLK_REG) 0x05800 page 88

DLL Registers (Base Address : 0x05000)

DLL Instruction RAM (DLL_IRAM_REG) 0x05C00 page 91

DLL Fine Offset Delay Registers (DLL_FN_OFST_REG ) 0x05D00 page 92

DLL Fine Delay Registers (DLL_FN_REG) 0x05D04 page 93

DLL Gross Delay Registers (DLL_GR_REG) 0x05D08 page 94

DLL Offset Delay Registers (DLL_OFST_REG) 0x05D0C page 95

DLL Reset Registers (DLL_RST_REG) 0x05D10 page 96

DLL PCLK Delay Registers (DLL_PCLK_DLY_REG) 0x05D18 page 97

DLL SCLK Offset Registers (DLL_SCLK_OFST_REG) 0x05D18 page 98

DPC Registers (Base Address : 0x10000)


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DPC Configuration Register (DPC_CONFIG_REG) 0x10000 page 102

DPC Status (DPC_STATUS_REG) 0x10004 page 104

DPC Interrupt Enable (DPC_INT_EN_REG) 0x10008 page 105

DPC Interrupt Status Register (DPC_INT_STAT_REG) 0x1000C page 106

DPC Display Count (DPC_DISP_COUNT_REG) 0x10010 page 107

DPC Sync Parameter 1 (DPC_SYNC_PARAM1_REG) 0x10014 page 108


DPC Sync Parameter 3 (DPC_SYNC_PARAM3_REG) 0x1001C page 110


DPC Sync Delay 1 (DPC_SYNC_DELAY1_REG) 0x10024 page 112

DPC Sync Delay 2 (DPC_SYNC_DELAY2_REG) 0x10028 page 113

DPC Background Accumulated Luma Register

(DPC_BG_CUMLUMA_REG)

0x1002C page 114

DPC Overlay Accumulate Luma Register

(DPC_OVL_CUMLUMA_REG)

0x10030 page 115

DPC Background Configuration Register (DPC_BG_CONFIG_REG) 0x10040 page 116

DPC Background Color Register (DPC_BG_COLOR_REG) 0x10044 page 118

DPC Background Video Source Configuration Register

(DPC_BVDOSRC_CFG1_REG)

0x10048 page 119

DPC Background Video Source Configuration Register

(DPC_BVDOSRC_CFG2_REG)

0x1004C page 120

DPC Background Video Window Configuration 1 Register

(DPC_BVDOWIN_CFG1_REG)

0x10050 page 121

DPC Background Video Window Configuration 2 Register

(DPC_BVDOWIN_CFG2_REG)

0x10054 page 122

DPC Background Video SC Configuration 1 Register

(DPC_BVDO_SC_CFG1_REG)

0x10058 page 123

DPC Background Video SC Configuration 2 Register

(DPC_BVDO_SC_CFG2_REG)

0x1005C page 124

DPC Background Video HS Control 1 Register

(DPC_BVDO_HS_CTL1_REG)

0x10060 page 125

DPC Background Video HS Control 2 Register

(DPC_BVDO_HS_CTL2_REG)

0x10064 page 126

DPC Background Video VS Control 1 Register

(DPC_BVDO_VS_CTL1_REG)

0x10068 page 127

DPC Background Video VS Control 2 Register

(DPC_BVDO_VS_CTL2_REG)

0x1006C page 128


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DPC Background Video Initial V Phase Register

(DPC_BVDO_IVPH_REG)

0x10070 page 129

DPC Overlay Configuration Register (DPC_OVL_CONFIG_REG) 0x10080 page 130

DPC Overlay Display List Start Address Register(DPC_OVL_DLIST_SA_REG)

0x10084 page 132

DPC Overlay Plane Start Address Register (DPC_OVL_SA_REG) 0x10088 page 133

DPC Overlay Size Register (DPC_OVL_SIZE_REG) 0x1008C page 134

DPC Overlay Position Register (DPC_OVL_POS_REG) 0x10090 page 135

DPC Global Alpha Register (DPC_GALPHA_IBASE_REG) 0x10094 page 136

DPC Overlay Maximum Color Key Register

(DPC_OVL_MAX_KEY_REG)

0x10098 page 137

DPC Overlay Minimum Color Key Register

(DPC_OVL_MIN_KEY_REG)

0x1009C page 138

DPC Overlay Filter Co-efficients Register

(DPC_OVL_FLTR_COEF_REG)

0x100A0 page 139

DPC Overlay Display List 1 Register (DPC_OVL_DLIST1_REG) 0x100A4 page 140

DPC Overlay Display List 2 Register (DPC_OVL_DLIST2_REG) 0x100A8 page 142

DPC Auxiliary Display Configuration Register

(DPC_AUX_CONFIG_REG)

0x100C0 page 143

DPC Auxiliary Display Position Register (DPC_AUX_POS_REG) 0x100C4 page 144

DPC Auxiliary Display Horizontal Size Control Register

(DPC_AUX_HS_CTL_REG)

0x100C8 page 145

DPC Auxiliary Display Vertical Size Control Register

(DPC_AUX_VS_CTL_REG)

0x100CC page 146

DPC Auxiliary Display Programmable 1 Timing Register

(DPC_AUX_PROG1_REG)

0x100D0 page 147


(DPC_AUX_PROG2_REG)

0x100D4 page 148


(DPC_AUX_PROG3_REG)

0x100D8 page 149

DPC Cursor Start Address Register (DPC_CURS_SA_REG) 0x10100 page 150

DPC Cursor Position Register (DPC_CURS_POS_REG) 0x10104 page 151

DPC CUrsor Offset Register (DPC_CURS_OFFSET_REG) 0x10108 page 152

DPC Cursor Color Look UP Table (DPC_CURSCLUTn_REG; n = 0 to

15)

0x101400x1017C page 153

DPC Memory Address Register (DPC_MEM_ADDR_REG) 0x10180 page 154

DPC Memory Data Register (DPC_MEM_DATA_REG) 0x10184 page 155


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DPC GPIO Enable Register (DPC_GPIO_EN_REG) 0x10190 page 158

DPC GPIO Output Enable Register (DPC_GPIO_OUT_EN_REG) 0x10194 page 159

DPC GPIO Output Data Register (DPC_GPIO_OUTDATA_REG) 0x10198 page 160

DPC GPIO Input Data Register (DPC_GPIO_INDATA_REG) 0x1019C page 161

DPC Sync Pulse Generator Configuration 1 Register

(DPC_SPG_CONFIG1_REG)

0x101A0 page 162

DPC Sync Pulse Generator Configuration 2Register


0x101A4 page 163

DPC Sync Pulse Generator Configuration 3 Register


0x101A8 page 164

DPC_SPG_PCONFIG_REG 0x101AC page 165

TSD Registers (Base Address : 0x20000)

TSD DMA Read and TSD DMA Configuration Register(TSD_DMA_RD_CONFIG_REG)

0x27000 page 167

TSD DMA Write Address High/Low Register

(TSD_DMA_WR_ADD_REG)

0x27004 page 168

TSD Byte Stop and Byte Limit Register

(TSD_IO_BYTELIM_CNT_REG)

0x27800 page 169

STC Counter Low and Middle Register (TSD_STC_CNT_LM_REG) 0x27804 page 170

STC Counter High Register (TSD_STC_CNT_H_REG) 0x27808 page 171

TSD IO Configuration and VCXO Register (TSD_CON_VCXO_REG) 0x27810 page 172

TSD Interrupt Status Register (TSD_INT_STATUS_REG) 0x27814 page 173

TSD IO Status Register (TSD_IO_STATUS_REG) 0x27820 page 174

TSD MPEG and Byte Count Register (TSD_MPEG_BYTECNT_REG) 0x27824 page 175

MIF Registers (Base Address : 0x28000)

MIF Configuration Register (MIF_CONFIG_REG) 0x28000 page 177

Macroscheduler Internal State Select (MIF_MAC_STATE_REG) 0x2803C page 179

MIF Field Buffer #n (MIF_FLD_DSCR_n_REG; n = 0 to 15) 0x280400x2807C page 181

MIF Status for Client #n (MIF_STATUS_REG) 0x280800x280DC page 183


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3.0 HIF REGISTERS

HIF internal registers can be accessed by external PCI master.

Table 3.3: HIF Register Map


HIF Registers (Base Address : 0x00000)

HIF Interrupt Status Register (HIF_INT0_STAT_REG) 0x00000 page 13

HIF Interrupt Mask Register (HIF_INT0_MASK_REG) 0x00004 page 14

HIF RAM Test Register (HIF_RAM_TEST_REG) 0x00010 page 15

HIF Hinted Address Register (HIF_HINTED_ADDR_REG) 0x00014 page 16

HIF EEPROM Access Register (HIF_EEPROM_REG) 0x0001C page 17

HIF DMA Source Address Register (HIF_DMA_SRCADDR_REG) 0x00020 page 18

HIF DMA Destination Address Register (HIF_DMA_DSTADDR_REG) 0x00024 page 19

HIF DMA Count Register (HIF_DMA_COUNT_REG) 0x00028 page 20

HIF DMA Control Register (HIF_DMA_CTRL_REG) 0x0002C page 21

HIF Reserved Registers 0x000300x000FF page 22

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HIF Interrupt Status Register (HIF_INT0_STAT_REG)

Address: 0x00000

31 16

Reserved

15 10 9 8 7 6 5 4 3 2 1 0

Reservedhif_mcu_intr

hif_hpip_intr

hif_vpip_intr

hif_mce_intr

hif_hif_intr

hif_vsc_intr

hif_dpc_intr

hif_mif_intr

hif_blt_intr

hif_apu_intr

Bits Mode Field Name Description Default

0 R/W hif_apu_intr APU Interrupt Pending. 0

1 R/W hif_blt_intr BLT Interrupt Pending. 0

2 R/W hif_mif_intr MIF Interrupt Pending. 0

3 R/W hif_dpc_intr DPC Interrupt Pending. 0

4 R/W hif_vsc_intr VSC Interrupt Pending. 0

5 R/W hif_hif_intr HIF Interrupt Pending. 0

6 R/W hif_mce_intr MCE interrupt Pending 0

7 R/W hif_vpip_intr VPIP interrupt Pending 0

8 R/W hif_hpip_intr HPIP interrupt Pending 0

9 R/W hif_mcu_intr MCU interrupt Pending 0

31:10 - - Reserved 0

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HIF Interrupt Mask Register (HIF_INT0_MASK_REG)

Address: 0x00004

31 16

Reserved

15 10 9 8 7 6 5 4 3 2 1 0

Reservedhif_mask

_mcu_intr

hif_mask_hpip_

intr

hif_mask_vpip_

intr

hif_mask_mce_

intr

hif_mask_hif_intr

hif_mask_vsc_intr

hif_mask_dpc_intr

hif_mask_mif_

intr

hif_mask_blt_

intr

hif_mask_apu_

intr

Bits Mode Name Description Default

0 R/W hif_mask_apu_intr 1 = Enable apu interrupts. 0 = disable. 1

1 R/W hif_mask_blt_intr 1 = Enable blt interrupts. 0 = disable. 1

2 R/W hif_mask_MIF_intr 1 = Enable MIF interrupts. 0 = disable. 1

3 R/W hif_mask_dpc_intr 1 = Enable dpc interrupts. 0 = disable. 1

4 R/W hif_mask_vsc_intr 1 = Enable vsc interrupts. 0 = disable. 1

5 R/W hif_mask_hif_intr 1 = Enable hif interrupts. 0 = disable. 1

6 R/W hif_mask_mce_intr 1 = Enable mce interrupts. 0 = disable. 1

7 R/W hif_mask_vpip_intr 1 = Enable vpip interrupts. 0 = disable. 1

8 RW hif_mask_hpip_intr 1 = Enable hpip interrupts. 0 = disable. 1

9 R/W hif_mask_mcu_intr 1 = Enable mcu interrupts. 0 = disable. 1

31:10 Reserved 0

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HIF RAM Test Register (HIF_RAM_TEST_REG)

Address: 0x00010

31 16

Reserved

15 10 9 8 7 6 5 4 3 2 1 0

Reserved hif_mem_test_reg


2:0 R/W hif_mem_test_reg 000 - Normal mode. 001-111 Internal RAM test. 0

31:3 Reserved 0

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HIF Hinted Address Register (HIF_HINTED_ADDR_REG)

Address: 0x00014

31 16

HintAddr

15 10 9 8 7 6 5 4 3 2 1 0

HintAddr Reservedr


1:0 R Reserved Reserved. 0

31:2 RW HintAddr A write to this register will cause a prefetch operation of

the cache line into the memory read buffer.

0

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HIF EEPROM Access Register (HIF_EEPROM_REG)

Address: 0x0001C

31 16

Reserved

15 10 9 8 7 6 4 3 2 1 0

Reservedhif_

eeprom_ow

Reservedhif_

eeprom_do

hif_eeprom_

di

hif_eeprom_

sk

hif_eeprom_

cs


0 R/W hif_eeprom_cs EEPROM CS pin, chip output. 0

1 R/W hif_eeprom_sk EEPROM SK, chip output. 0

2 R hif_eeprom_di EEPROM DIN, chip output. 0

3 R/W hif_eeprom_do EEPROM DOUT, chip input 0

6:4 R Reserved Reserved. 0

7 R/W hif_eeprom_ow When set, the bitfields [3:0] go directly to pin outputs

eeprom_cs/sk/di/do.

0

31:8 Reserved Reserved 0

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HIF DMA Source Address Register (HIF_DMA_SRCADDR_REG)

Address: 0x00020

31 16

SrcAddr

15 10 9 8 7 6 5 4 3 2 1 0

SrcAddr Reservedr


1:0 R Reserved Reserved. All bits set to 0. Write has no effect. 0

31:2 RW SrcAddr The address that the DMA controller reads data from. 0

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HIF DMA Destination Address Register (HIF_DMA_DSTADDR_REG)

Address: 0x00024

31 16

DstAddr

15 10 9 8 7 6 5 4 3 2 1 0

DstAddr Reservedr



31:2 RW DstAddr The address that the DMA controller writes data to. 0

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HIF DMA Count Register (HIF_DMA_COUNT_REG)

Address: 0x00028

31 16

Reserved

15 10 9 8 7 6 5 4 3 2 1 0

Count Reserved



15:2 RW Count The number of words that are left in DMA transfers. Note

that in video DMA mode, this number must be a multiple of

8; if it is not, the TL850 transfers 16 32-bit words back to

the external destination address.

0


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HIF DMA Control Register (HIF_DMA_CTRL_REG)

Address: 0x0002C

31 16

Reserved

15 12 11 8 7 6 5 4 3 2 1 0

End_Byte_En Start_Byte_EnDMA_VDO_

RESET

DMA_ENDIAN

_EN

DMA_FAKE_VDO_DMA

DMA_VIDEO

DMAActSt

DMA_EN

DMA_ERR

DMA_DIR


0 DMA_DIR DMA transfer direction. 1: PCI to TL850; 0: TL850 to PCI. 0

1 DMA_ERR DMA transfer error indication. 1: an error has occured. 0

2 DMA_EN DMA enable. 0: DMA disabled; 1: DMA enabled. 0

3 DMAActSt DMA activity status (read only). 0: Channel is not active; 1:

Channel is currently active.

0

4 DMA_VIDEO DMA video channel enable. 0: MIF DMA channel; 1: AUX

video DMA channel.

0

5 DMA_FAKE_VDO_DMA 0: Normal DMA; 1: Fake video DMA operation (only read

from AUX FIFO and no PCI transaction takes place).

0

6 DMA_ENDIAN_EN Endian Switch enable. 0: disable Endian switch; 1: enable

Endian switch (byte 0 to byte 3, byte 1 to byte 2, byte 2 to

byte 1, byte 3 to byte 0).

0

7 DMA_VDO_RESET 0: no action; 1: reset DPC AUX FIFO and clear the previ-ous video DMA operation even if it is unfinished.

0

11:8 Start_Byte_En Byte enables for the first DMA word. This is not applicable

in video DMA mode.

F

15:12 End_Byte_En Byte enables for the last DMA word. This is not applicable

in video DMA mode.

F

31:16 Reserved Reserved. 0

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HIF Reserved Registers

Address: 0x000300x000FF

31 0

Reserved


31:0 Reserved Reserved. 0

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4.0 VSC REGISTERS

Table 4.4: VSC Register Map


VSC Registers (Base Address : 0x01000)

Video Channel Control Register (VSC_CTRL_REG) 0x01000 page 24

Video Channel Status Register (VSC_STAT_REG) 0x01004 page 25

VSC Interrupt Enable Register (VSC_INT_EN_REG) 0x01008 page 26

VSC Interrupt Status Register (VSC_INT_STAT_REG) 0x0100C page 27

VSC Memory Interface Control Register (VSC_MIF_REG) 0x01010 page 28

VSC Horizontal DDA Control Register (VSC_DDA_REG) 0x01014 page 29

VSC Horizontal Scaler Control Register (VSC_HS_REG) 0x01018 page 30

VSC Field 0 VBI Data Capture Control Register (VSC_VBI0_REG) 0x0101C page 31

VSC Field 1 VBI Data Capture Control Register (VSC_VBI1_REG) 0x01020 page 32

VSC VBI Data Buffer Start Address (VSC_VBUF_SADR_REG) 0x01024 page 33

VSC VBI Data Buffer Write Address (VSC_VBUF_WADR_REG) 0x01030 page 34

VSC Software Reset Register (VSC_SW_RESET_REG) 0x01030 page 35

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Video Channel Control Register (VSC_CTRL_REG)

Address: 0x01000

This register specifies the operation of Video Port.

31 16

reserved

15 6 5 4 3 2 1 0

vsc_vline_icntvsc_ctype

vsc_vact_polarity

vsc_vbi_vact_on

vsc_vbi_en1

vsc_vbi_en0

vsc_en


0 RW vsc_en VSC enable. This bit enables or disable the VSC. The

VSC and its output turns on and off only on the frame

boundaries.

0: VSC off; 1: VSC on

0

1 RW vsc_vbi_en0 VSC VBI data capture enable. This bit enables or disablethe VSC VBI data capture feature during F==0. The VBI

data capture function turns on and off only on the frame

boundaries.

0: VSC VBI data capture off; 1: VSC VBI data capture on

0

2 RW vsc_vbi_en1 VSC VBI data capture enable. This bit enables or disable

the VSC VBI data capture feature during F==1. The VBI

data capture function turns on and off only on the frame

boundaries.

0: VSC VBI data capture off ; 1: VSC VBI data capture on

0

3 RW vsc_vbi_vact_on VSC VBI VACT on. This bit indicates whether VACT signal

is used for VBI data capture. Note: VACT is always used

for active video region.

0: VSC VBI VACT off; 1: VSC VBI VACT on

0

4 RW vsc_vact_polarity VSC VACT polarity. This bit indicates whether VACT

signal is active high or active low. This applies to both

active video and VBI region.

0: VSC VACT active low; 1: VSC VACT active high

0

5 RW vsc_ctype VSC chroma type. This bit indicates whether the chroma

is signed or unsigned.

0: chroma is unsigned; 1: chroma is signed

1

15:6 RW vsc_vline_icnt Vertical Line interrupt count. This field contains the num-

ber of the vertical line for generating an interrupt if

vsc_A_VLINE_IE register is set. Valid ranges for this field

are 1 to 525 for NTSC and 1 to 625 for PAL.

0xFF

31:16 RW Reserved Reserved. 0

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Video Channel Status Register (VSC_STAT_REG)

Address: 0x01004

This register provides status information on the Video port.

31 16

res

15 2 1 0

res vsc_f_flagvsc_

v_flag


0 RO vsc_v_flag CCIR656 V Flag. This bit gives the CCIR656 V status on

video channel.

0: active video line

1: vertical blanking

1 RO vsc_f_flag CCIR656 F Flag. This bit gives the CCIR656 F status onvideo channel.

0: Field 1 (odd)

1: Field 2 (even)

31:2 RO res Reserved. These bits are reserved and must be written as

zeros.

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VSC Interrupt Enable Register (VSC_INT_EN_REG)

Address: 0x01008

This register provides the interrupt enables for the VSC.

31 16

res

15 7 6 5 4 3 2 1 0

Reservedvsc_vbi_

ievsc_f1_

ievsc_f0_

ievsc_vblank1_

ievsc_vblank0_

ievsc_vline_

ievsc_ibuf_ov_ie


0 RW vsc_ibuf_ov_ie Internal Scaler FIFO Overflow Interrupt Enable. This bit

enables/disables interrupts on internal Scaler FIFO over-

flows. 0: interrupts disabled. 1: interrupts enabled

0

1 RW vsc_vline_ie Video Channel B Vertical Line Interrupt Enable. This bit

enables/disables interrupts at the beginning of line n of

Channel B, where n is specified by the register

vsc_B_VLINE_ICNT.

0: interrupts disabled. 1: interrupts enabled

0

2 RW vsc_vblank0_ie Video Channel Vertical Blanking Interrupt Enable for field.

This field enables/disables interrupt when the video is

entering the vertical blanking interval (V->1) preceding the

transition to field 0.

0: interrupts disable

1: enable interrupt

0

3 RW vsc_vblank1_ie Video Channel Vertical Blanking Interrupt Enable for field.

This field enables/disables interrupt when the video is

entering the vertical blanking interval (V->1) preceding the

transition to field 1.0: interrupt disable

1: enable interrupt

0

4 RW vsc_f0_ie Video Channel Field 0 Interrupt Enable. This field enables/

disables interrupt on field transition from 1 to 0.

0: interrupt disabled

1: enable interrupt

0

5 RW vsc_f1_ie Video Channel Field 1 Interrupt Enable. This field enables/

disables interrupt on field transition from 0 to 1.

0: interrupt disabled

1: enable interrupt

0

6 RW vsc_vbi_ie VBI capture done interrupt enable. This field enables/dis-

ables when VBI capture is finished0: interrupt disabled

1: interrupt enabled.

0

31:7 RW reserved These bits are reserved and must be written as zeros.

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VSC Interrupt Status Register (VSC_INT_STAT_REG)

Address: 0x0100C

The status register is cleared when read. However, a pending interrupt occurring during the samecycle has priority and will set the corresponding status bit. All interrupts are activated only on the

leading edge of the interrupt conditions. The status bits are set when their corresponding condi-tions occur even if the interrupt enable bits are not set.

31 16

res

15 7 6 5 4 3 2 1 0

resvsc_vbi_

intvsc_f1_

intvsc_f0_

int

vsc_vblank1

_int

vsc_vblank0

_int

vsc_vline_int

vsc_ibuf_ov_int


0 RO vsc_ibuf_ov_int Internal DRAM Interface scaler FIFO Overflow Status. This

bit is set to one when an overflow in the internal DRAMInterface scaler FIFO occurs.

0

1 RO vsc_vline_int Video Channel vertical line interrupt status. This bit is set

to one when the VSC detects the begin of video line

number X, where X is defined in the vsc_ctrl_reg.

0

2 RO vsc_vblank0_int Video Channel Vertical Blanking interrupt Status. This bit

is set to one when the video is entering the vertical blank-

ing interval (V->1) during field 0.

0

3 RO vsc_vblank1_int Video Channel Vertical Blanking interrupt Status. This bit

is set to one when the video is entering the vertical blank-

ing interval (V->1) during field 1.

0

4 RO vsc_f0_int Video Channel Field 0 interrupt Status. This bit is set toone when the video enters field 0.

0

5 RO vsc_f1_int Video Channel Field 1 interrupt Status. This bit is set to

one when the video enters field 1.

0

6 RO vsc_vbi_int VBI Capture Done interrupt Status. This bit is set to one

when the VBI data is written into SDRAM.

0

31:7 RO reserved This field is reserved and must be written as zeros.

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VSC Memory Interface Control Register (VSC_MIF_REG)

Address: 0x01010

31 16

res

15 12 11 8 7 4 3 0res vsc_base1 res vsc_base0


3:0 RW vsc_base0 This is the MIF descriptor base that VSC uses when post-

ing a buffer request for field 0 to MIF

0

7:4 RW reserved These bits are reserved and must be written as zeros. 0

11:8 RW vsc_base1 This is the MIF descriptor base that VSC will use when

posting a buffer request for field 1 to MIF

1


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VSC Horizontal DDA Control Register (VSC_DDA_REG)

Address: 0x01014

This register specifies the horizontal scaling factors

31 24 23 20 19 16

vsc_lphase res vsc_hstep_reg

15 0

vsc_hstep_reg


19:0 RW vsc_hstep_reg Horizontal Step. This field contains the 20-bit step value

needed for the horizontal DDA. This value avoids a

divide in the implementation. The vsc_sv_hsize is the

desired horizontal line width of the scaled output video.

0x80000

23:20 RW res These bits are reserved and must be written as zeros.

31:24 RW vsc_lphase Initial Luma phase. This field contains the eight-bit initial

phase offset for the Luma DDA.

0

VSC_HSTEP VSC_SV_HSIZE VSC_HSIZE( ) 219

=

vsc_hsize

vsc_hstep

vsc_sv_hsize

zoom

vsc_hphase

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VSC Horizontal Scaler Control Register (VSC_HS_REG)

Address: 0x01018

31 26 25 16

res vsc_sv_hsize

15 10 9 0

res vsc_line_width


9:0 RW vsc_line_width This is the number of active pixels per video line. 720


25:16 RW vsc_sv_hsize This is the expected number of pixel output from the

horizontal scaler.

720


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VSC Field 0 VBI Data Capture Control Register (VSC_VBI0_REG)

Address: 0x0101C

This register defines the field 0 VBI data capture operation..

31 25 24 16

res vsc_vbi0_vsize

15 10 9 0

reserved vsc_vbi0_voffset


9:0 RW vsc_vbi0_voffset Field 0 VBI Vertical Offset. This field contains a 10-bit

signed offset -(voffset) indicating where the VBI data cap-

ture begins. The offset is referenced to the rising edge of

the CCIR-656 timing reference V.

0x3F0

(16)


24:16 RW vsc_vbi0_vsize Field 0 VBI Vertical Size. This field defines the number of

VBI lines to be captured. The maximum VBI size is 262 for

NTSC and 288 for PAL.

3


* vsc_vbi_voffset = -(voffset-1) where voffset is >= 0

CCIR V

CCIR H

voffset lines vsc_vbi_vsize lines

Digital Field 1

line 4

Blanking 2

Blanking 1

Field 1Active Video

Field 2Active Video

line 266

Digital Field 2

line 3

line 1 (V=1)

line 20 (V=0)

line 283 (V=0)

line 264 (V=1)

line 525 (V=0)

NTSC (CCIR656 line numbering)

VBI Data Field 1

VBI Data Field 2

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VSC Field 1 VBI Data Capture Control Register (VSC_VBI1_REG)

Address: 0x01020

This register defines the field 1 VBI data capture operation..

31 25 24 16

res vsc_vbi1_vsize

15 10 9 0

reserved vsc_vbi1_voffset


9:0 RW vsc_vbi1_voffset Field 1 VBI Vertical Offset. This field contains a 10-bit

signed offset -(voffset) indicating where the VBI data

capture begins. The offset is referenced to the rising edge

of the CCIR-656 timing reference V.

0x3f0

(16)


24:16 RW vsc_vbi1_vsize Field 1 VBI Vertical Size. This field defines the number of

VBI line to be captured. The maximum VBI size is 262 for

NTSC and 288 for PAL.

3


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VSC VBI Data Buffer Start Address (VSC_VBUF_SADR_REG)

Address: 0x01024

This register specifies the start address of the VBI field buffer in external memory...

31 27 26 16

Reserved vsc_vbuf_sadr

15 5 4 0

vsc_vbuf_sadr 0


4:0 RO ZERO Reserved. Writes are ignored reads return 0. 0

26:5 RW vsc_vbuf_sadr Start address of external VBI data field buffer. The address

is in 32 bytes.

0x0000

31:22 RW Reserved Reserved. These bits are reserved and must be written as

zeros.

vsc_vbuf_wadr

vsc_vbuf_sadr

VBI

Data

Capture

field

Buffer

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VSC VBI Data Buffer Write Address (VSC_VBUF_WADR_REG)

Address: 0x01028

This register contains the current write address of the VBI field buffer in external memory...

31 27 26 16

Reserved vsc_vbuf_wadr

15 5 4 0

vsc_vbuf_wadr 0


4:0 RO ZERO Reserved. Writes are ignored reads return 0. 0

26:5 RO vsc_vbuf_wadr Write address of external VBI data field buffer. The

address is in 32 bytes.

0x0000

31:22 RO Reserved Reserved. These bits are reserved and must be written as

zeros.

vsc_vbuf_wadr

vsc_vbuf_sadr

VBI

Data

Capture

field

Buffer

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VSC Software Reset Register (VSC_SW_RESET_REG)

Address: 0x01030

This register contains the bit to reset the VSC module via software...

31 16

res

15 2 1 0

res res vsc_rst


0 RW vsc_rst VSC Module Reset. When set to 1, resets the VSC mod-

ule. The module stays reset till a 0 is written back to come

out of reset. When set to 0 the module is out of reset.

0

31:1 RO Reserved Reserved. 0

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5.0 APU REGISTERS

The following sections contain details about APU registers.

Table 5.5: APU Register Map


APU Registers (Base Address : 0x03000)

Input, Output and Clock Configuration Register

(APU_IOC_CONFIG_REG)

0x03000 page 37

Capture and Playback Configuration Register

(APU_CPB_CONFIG_REG)

0x03004 page 38

IEC-958 Configuration Register (APU_IEC_CONFIG_REG) 0x03008 page 39

IEC958 Channel Status Buffer 1 Registers (APU_IEC_CSB1_REG) 0x0300C page 40

IEC958 Channel Status Buffer 2 Registers (APU_IEC_CSB2_REG) 0x03010 page 41

Interrupt Configuration Register (APU_INT_CONFIG_REG) 0x03014 page 42

Interrupt Status Register (APU_INT_STATUS_REG) 0x03018 page 43

Capture/Playback Begin Address Register (APU_CPB_CBA_REG) 0x03020 page 44

Capture/Playback End Address Register (APU_CPB_CEA_REG) 0x03024 page 45

Capture/Playback Write Address Register (APU_CPB_CWA_REG) 0x03028 page 46

Capture/Playback Read Address Register (APU_CPB_CRA_REG) 0x0302C page 47

Capture/Playback Match Address Register (APU_CPB_CMA_REG) 0x03030 page 48



Internal Audio 0 End Address Registers (APU_IAU_IEA0_REG) 0x0303C page 51




Internal Audio 2 Begin Address Registers (APU_IAU_IBA2_REG) 0x0304C page 55



Mix Configuration Register (APU_MIX_CONFIG_REG) 0x03058 page 58

Cross-fade Coefficient Registers (APU_MIX_XFCn_REG; n=0 to 8) 0x0305C0x0307C page 59

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Input, Output and Clock Configuration Register (APU_IOC_CONFIG_REG)

Address: 0x03000

31 26 25 24 23 22 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 3 2 1 0

acr acx acm bcx ocm icm byp 0 owl iwl2 iwl1 iwl0 idly ace ijfy


0 ijfy Input audio sample justify mode. 0 = left justified; 1 = right

justified

0

1 ace BCLK active edge.

0 = rising edge, 1 = falling edge.

0

2 idly Delay from lrclk transition to first bit cell of input audio

sample.

0 = no delay, 1 = one bclk cycle delay.

0

4:3 iwl0 Audio input port-0 bits/sample.

03 = 16b, 18b, 20b, 24b.

0 (16b)

6:5 iwl1 Audio input port-1 bits/sample.

03 = 16b, 18b, 20b, 24b.

0 (16b)

8:7 iwl2 Audio Input port-2 bits/sample. 03 = 16b, 18b, 20b, 24b. 0 (16b)

10:9 owl Audio output bits/sample (ports 0,1,2). 03 = 16b, 18b,

20b, 24b.

0 (16b)

13:11 reserved Must be written as zero. 0

14 adatao Tristate buffer enable for adatao.

0 = enable

1 = disable

1

15 byp Bypass serial streams from input ports to output ports.


19:18 ocm Output clock (bclko/lrclko) source mode.

0 = slave

1 = aclk

2, 3 = reserved

0

21:20 bcx BCLK multiplier. 03 = 32x, 48x, 64x, 128x. 0

23:22 acm ACLK source mode. 03=Reserved; must be written as

zero.

25:24 acx ACLK multiplier. 03 = 128x, 256x, 384x, 512x. 0

31:26 reserved These bits are Reserved and must be set to zeroes.

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Capture and Playback Configuration Register (APU_CPB_CONFIG_REG)

Address: 0x03004

31 22 21:20 19:18 17:16 15 14:13 12:11 10:9 8 7 6 1 0

0 iam2 iam1 iam0 0 pbm2 pbm1 pbm0 pen cen cmsk cfr


0 cfr Capture FIFO reset. 0 = reset, 1 = normal 0

6:1 cmsk Capture mask. when set, enables audio capture to

memory.

0 = disable, 1 = enable.

bit-1: port-0 left-channel

bit-2: port-0 right-channel

...

bit-6: port-3 right channel.

0

7 cen Capture enable. when set, enables audio capture based

on cmsk.0 = disable, 1 = enable.

0

8 pen Playback enable. when set enables audio playback from

memory.


0

10:9 pbm0 Playback mode, stream-0.

00 = mute,

01 = memory playback,

10 = bypass (samples come from corresponding I2S input

port),

11 = reserved.

00

12:11 pbm1 Playback mode, stream-1.0011 = same as pbm0.

14:13 pbm2 Playback mode, stream-2.

0011 = same as pbm0.

15 reserved Must be written as zero.

17:16 iam0 Internal audio mode, stream-0.

00 = stereo, auto repeat disabled,

01 = stereo, auto repeat enabled,

10 = mono, auto repeat disabled,

11 = mono, auto repeat enabled.


0011:same as iam0.


0011:same as iam0.

31:22 reserved Must be written as zero.

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IEC-958 Configuration Register (APU_IEC_CONFIG_REG)

Address: 0x03008

31 24 23 22 21 20 19 16 15 14 12 11 10 8 7 6:5 4:3 2:1 0

fmc 0 p v u aux 0 sel1 0 sel0 csm mod1 mod0 owl enb


0 enb IEC enable. enable iec-958 encoding.


0

2:1 owl IEC output word length. audio samples are padded with

zero on the least significant bits, as appropriate.

03 = 16b, 18b, 20b, 24b.

0

4:3 mod0 IEC mode, channel-0.

0 = mute,

1 = mixer output,

2 = capture audio bypass (samples come from

corresponding input port)3 = internal audio bypass (samples come from IAU buffer

2).

0

6:5 mod1 IEC mode, channel-1.

03 = same as mod0.

7 csm Channel status buffer mode.

0 = 32b, 1 = 192b.

0

10:8 sel0 IEC data select, channel-0

05 = select audio stream 05,

67 = reserved.

0


14:12 sel1 IEC data select, channel-1

07 = same as sel0.

15 reserved Must be written as zero. 0

19:16 iecaux IEC auxiliary data. provides iec auxiliary data for iec sub-

frames.

20 u IEC user bit. provides iec user bit for iec subframes.

21 v IEC user bit. provides iec valid bit for iec subframes.

22 p IEC parity.

0 = normal parity (even) over bits 31:4,

1 = inverted parity.

0


31:24 fmc IEC frame counter. counts frames within a block

automatically. should not be modified by host except

during initialization. this field is cleared by chip reset.

0191 = frame number within iec 958 block,

192255 = reserved.

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IEC958 Channel Status Buffer 1 Registers (APU_IEC_CSB1_REG)

Address: 0x0300C

31 0

csb1

Bits Mode Field Name DescriptionDefa

ult

31:0 csb1 IEC channel status buffer. This register provides the

source for the channel status bits of iec958 channel-1sub-

frame words. Bits are serialized, lsb first, one bit per

iec958 frame, from each register. If csm=0, channel status

bits are set to 0 for fmc > 31. If csm=1, channel status bits

are repeated every 32 frames. An interrupt is available to

alert the CPU every 32 frames. This allows the loading of

new channel status information. Note that 32b are suffi-

cient for the entire iec958 block in case of Consumer use

applications. The host must reload this register every 32frames.

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IEC958 Channel Status Buffer 2 Registers (APU_IEC_CSB2_REG)

Address: 0x03010

31 0

csb2

Bits Mode Field Name DescriptionDefa

ult

31:0 csb2 IEC channel status buffer. This register provides the

source for the channel status bits of iec958 channel-2 sub-

frame words. Bits are serialized, lsb first, one bit per

iec958 frame, from each register. If csm=0, channel status

bits are set to 0 for fmc > 31. If csm=1, channel status bits

are repeated every 32 frames. An interrupt is available to

alert the CPU every 32 frames. This allows the loading of

new channel status information. Note that 32b are suffi-

cient for the entire iec958 block in case of Consumer use

applications. The host must reload this register every 32frames.

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Interrupt Configuration Register (APU_INT_CONFIG_REG)

Address: 0x03014

31 13 12:11 10 8 7 6 5 4:3 2 0

Reserved iecfrm iauwrp Res capunf capovf 0 matint


2:0 matint Interrupt on reference address match.

000 = disabled,

001 = match playback pointer,

010 = match capture pointer,

011 = match playback or capture pointers,

100 = match internal audio pointer (stream-0),



000


5 capovf Interrupt on capture buffer overflow.0 = disable,

1 = enable.

0

6 capunf Interrupt on capture buffer underflow.

0 = disable,

1 = enable.

0


10:8 iauwrp[2:0] Interrupt on internal audio buffer wrap-around.

0 = disable The three iau channels can be enabled/dis-

abled independently (default 000 all disabled)

1 = enable.

000

12:11 iecfrm Interrupt on iec-958 frame sequence end.00 = disable,

01 = one frame,

10 = 32 frames,

11 = 192 frames (block).

00


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Interrupt Status Register (APU_INT_STATUS_REG)

Address: 0x03018

All bits are cleared upon read by the Host.

31 12: 11 10 8 7 6 5 4: 1 0

Reserved iecfrm iauwrp R capunf capovf 0 matint


0 matint Set if reference address match occurred.

4:1 reserved 0 0

5 capovf Set if capture buffer overflow occurred.

6 capunf Set if capture buffer underflow occurred.

7 reserved 0 0

10:8 iauwrp Set if internal audio buffer wrap-around occurred.

11 iecfrm Set if iec-958 frame sequence end occurred.

31:12 reserved 0 0

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Capture/Playback Begin Address Register (APU_CPB_CBA_REG)

Address: 0x03020

31 25 24 5 4 0

Reserved cba Reserved



24:5 cba Capture/playback begin address, in 32-byte units. the

actual DRAM word address is given by 8*cba.


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Capture/Playback End Address Register (APU_CPB_CEA_REG)

Address: 0x03024

31 25 24 5 4 0

Reserved cea Reserved



24:5 cea Capture/playback end address, in 32-byte units. the actual

DRAM word address is given by 8*cea + 7.


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Capture/Playback Write Address Register (APU_CPB_CWA_REG)

Address: 0x03028

31 25 24 5 4 0

Reserved cwa Reserved



24:5 cwa Capture/playback write address, in 32-byte units. the

actual DRAM word address is given by 8*cwa.


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Capture/Playback Read Address Register (APU_CPB_CRA_REG)

Address: 0x0302C

31 25 24 5 4 0

Reserved cra Reserved



24:5 cra Capture/playback read address, in 32-byte units. the

actual DRAM word address is given by 8*cra.


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Capture/Playback Match Address Register (APU_CPB_CMA_REG)

Address: 0x03030

This register is used to generate interrupts when another capture/playback register matches thecontents of this register. See APU_INT_CONFIG register.

31 25 24 5 4 0

Reserved cma Reserved



24:5 cma Capture/playback match address, in 32-byte units. the

actual DRAM word address is given by 8*cma.


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Internal Audio 0 Begin Address Registers (APU_IAU_IBA0_REG)

Address: 0x03034

31 25 24 5 4 0

Reserved iba Reserved



24:5 iba Internal audio begin address, in 32-byte units. the actual

DRAM word address is given by 8*iba.


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Internal Audio 0 Read Address Registers (APU_IAU_IRA0_REG)

Address: 0x03038

31 25 24 5 4 0

Reserved ira Reserved



24:5 ira Internal audio read address, in 32-byte units. the actual

DRAM word address is given by 8*ira.


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Internal Audio 0 End Address Registers (APU_IAU_IEA0_REG)

Address: 0x0303C

31 25 24 2 1 0

Reserved iea Res



24:2 iea Internal audio end address, in words (4 bytes).


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Address: 0x03040

31 25 24 5 4 0







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Address: 0x03044

31 25 24 5 4 0







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Address: 0x03048

31 25 24 2 1 0

Reserved iea Res





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Address: 0x0304C

31 25 24 5 4 0







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Address: 0x03050

31 25 24 5 4 0







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Address: 0x03054

31 25 24 2 1 0

Reserved iea Res





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Mix Configuration Register (APU_MIX_CONFIG_REG)

Address: 0x03058

Mixing coefficients determine the weighting of internal audio and playback audio. The sum ofweights is always 1. Each mixing coefficient applies to both left and right channels of the corre-

sponding audio stream. A value of 0 corresponds to 100% ( dB) attenuation of the corre-

sponding internal audio stream. Values between 1 and 195 represent attenuations of 97 to 0 dB,respectively, in 0.5 dB increments. Values above 195 are treated as 195 (0 dB).

31 24 23 16 15 8 7 6 5 4 3:2 1 0

mixc2 mixc1 mixc0 Res mixm2 mixm1 mixm0


1:0 mixm0 Mix mode, stream-0.

00 = pause,

01 = play,

10 = mute,

11 = reserved.


0011 = same as mixm0.


0011 = same as mixm0.


15:8 mixc0 Mix coefficient, stream-0.

0x00 = attenuation of internal audio stream-0

0x010xC3 = 97 to 0 dB attenuation.


0x00 = attenuation of internal audio stream-10x010xC3 = 97 to 0 dB attenuation.


0x00 = attenuation of internal audio stream-2

0x010xC3 = 97 to 0 dB attenuation.

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6.0 BLT REGISTERS

The following is the description of the BLT registers.

Table 6.6: BLT Register Map

Register NameBase + Offset Address Page #

BLT Registers (Base Address : 0x04000)

Channel S0 Configuration Register (BLT_CHAN_S0_REG) 0x04000 page 61

S1 Channel Configuration Register (BLT_CHAN_S1_REG) 0x04004 page 62

Destination Channel Configuration Register (BLT_CHAN_D_REG) 0x04008 page 63

BitBlt Command Register (BLT_CMD_REG) 0x0400C page 64

Mode Register (BLT_MODE_REG) 0x04010 page 65

Interrupt Status Register (BLT_INTR_STAT_REG) 0x04014 page 66

Channel S0, Left Address Register of First Line Address Processed(BLT_LEFT_ADDRESS_S0_REG) 0x04018 page 67

Channel S0, Right Address Register of First Line Address Processed


0x0401C page 68

Channel S1 Left Address Register of First Line Processed


0x04020 page 69

Channel S1 Right Address Register of First Line Processed


0x04024 page 70

Channel D Left Address Register of First Line Processed

(BLT_LEFT_ADDRESS_D_REG)

0x04028 page 71

Channel D Right Address Register of First Line Processed

(BLT_RIGHT_ADDRESS_D_REG)

0x0402C page 72



Pitch Size For Channel D (BLT_D_PITCH_SIZ_REG) 0x04038 page 75

Bitmap Size (BLT_H_W_REG) 0x0403C page 76

Link List Address (BLT_LINK_ADDR_REG) 0x04040 page 77

Foreground Register S0 (BLT_S0_FG_COLOR_REG) 0x04044 page 78


Foreground Register S1 (BLT_S1_FG_COLOR_REG) 0x0404C page 80


Alpha Parameters (BLT_ALPHA_REG) 0x04054 page 82

BLT Programmable Register (BLT_PROG_REG) 0x04058 page 83

BLT Pace Line Register (BLT_PACE_LINE_REG) 0x0405C page 84

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Channel S0 Configuration Register (BLT_CHAN_S0_REG)

Address: 0x04000

31 16

Reserved

15 11 10 9 8 7 6 5 2 1 0

Reserved Mask Reduce_PixBlockPaint

Pix Format Y_DIR X_Dir


0 R/W X_Dir When at 1, scan line from left to right, increments in X

direction.

1

1 R/W Y_Dir When at 1, increments line number. 1

5:2 R/W Pix Format Source S0 format:

B: 1 bit of index

C: 4 bits of index7: 8 bits of index

3: alpha[8],index[8]

9: alpha[4]

6: color rgb[8]

D: alpha[4]rgb[12]

5: color rgb[16]

4: color rgb[24]

0: alpha[8] rgb[24]

A: CbYCr[24]

E: Color RGB 15

0

6 R/W Block Paint Source S0 uses a global color register.

8:7 R/W Reduce_Pix Method used to reduce format when

Source format > Destination format:

0: Truncate

1: Round off

2: Dither

Default: 0

0

9 R/W Mask 1: Keep destination untouched when S0(i1) = 0. Write

result to destination when S0(i1) =1.

0: Use Foreground color or Background color as a source

S0 when respectively S0(i1) = 1 or S0(i1) = 0.

0

31:10 Reserved Reserved.

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S1 Channel Configuration Register (BLT_CHAN_S1_REG)

Address: 0x04004

31 16

Reserved

15 9 8 7 6 5 2 1 0

Reserved Reduce_PixBlockPaint

Pix Format Y_DIR X_Dir



direction.

1

1 R/W Y_Dir When at 1, increments number of lines. 1

5:2 R/W Pix Format Source S1 format:

B: 1 bit of index

C: 4 bits of index

7: 8 bits of index

3: alpha[8],index[8]

9: alpha[4]

6: color rgb[8]

D: alpha[4]rgb[12]

5: color rgb[16]

4: color rgb[24]

0: alpha[8] rgb[24]

E: Color RGB 15

0

6 R/W Block Paint Source S1 uses a global color register.

8:7 R/W Reduce_

Pix

Method used to reduce format when

Source format > Destination format:

0: Truncate

1: Round off

2: Dither

0


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Destination Channel Configuration Register (BLT_CHAN_D_REG)

Address: 0x04008

31 16

Reserved

15 11 10 9 8 7 6 5 2 1 0

Reserved XY_Dither Pix Format Y_DIR X_Dir



direction.

1

1 R/W Y_Dir When at 1, increments number of lines. 1

5:2 R/W Pix Format Destination format:

7: 8 bits of index

3: alpha[8],index[8]6: color rgb[8]

D: alpha[4]rgb[12]

5: color rgb[16]

4: color rgb[24]

0: alpha[8] rgb[24]

E: Color RGB 15

0

7:6 R/W XY_Dither Initial Matrix coefficient addresses to be applied to destina-

tion:

00: from upper left

01: from upper right

10: from lower left

11: from lower right

0


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Mode Register (BLT_MODE_REG)

Address: 0x04010

31 16

Reserved

15 8 7 6 5 4 3 2 1 0

Reserved End_BLTBLT_Busy

Mask_Field

Suspend_BLT

Pace_BLT


1:0 R/W Pace_BLT Start BitBlt after Comman register programmed and

according to the following:

case (Pace_BLT):

0: No constrains

1: Upon VSYNC

2: Upon HSYNC

3: Upon specific display line number

0

2 R/W Suspend_BLT Takes effect only after current BLT is over. Any Bitblt

operation is suspended as long as this bit is set.

0

3 R/W Mask_Field When set, the compare of the Line Pace register (address

17hex) is compared on bits 9 to 0. The msb (bit 10) is

ignored.

4 R BLT_Busy Set internally when BitBlt operation is effectively

started.Cleared when current BitBlt operation completes.

When in link list mode, this bit covers the time for updating

register and the BitBlt operation.

0

5 R End_BLT BitBlt operation is over. 1


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Interrupt Status Register (BLT_INTR_STAT_REG)

Address: 0x04014

31 18 17 16

Reserved Bool_Sel_Alpha

15 8 7 6 5 4 3 2 1 0

ReservedMask_

BLT_Late

Mask_End_

Chain_BLT

Mask_BLT_End

BLT_Late

BLT_End_of_

Chain_Status

BLT_End_Status


0 R BLT_End_Status When not masked an interrupt is generated when a BitBlt

operation completes.

1 R BLT_End_of_Chain_

Status

When not masked, an interrupt is generated when the

chain of BitBlt completes.

2 R BLT_Late Generates an interrupt to inform the CPU that the BLIT

does not get enough memory bandwidth when in pace

mode.

3 R/W Mask_BLT_End Dynamically mask End BLT interrupt. 1

4 R/W Mask_End_Chain_BLT Dynamically masks End BLT chained Interrupt 1

5 R/W Mask_BLT_Late This bit mask the interrupt due to BLT late when BLIT

operation are paced based upon display line match.

1


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Channel S0 , Lef t Address Register of F i rs t L ine Address Processed


Address: 0x04018

31 28 27 16

Reserved Word Address

15 8 7 6 5 4 3 2 1 0

Word AddressByte address within

workLeft Address


2:0 R/W Left Address Left address of the first line processed of the source

region. It is a bit address:

Bit 2 to 0: Bit address within Byte

Note that because the left address is Byte aligned bits 2 to

0 are always 0.

4:3 R/W Bit 4 to 3: Byte address within word

27:5 R/W Bit 27 to 5: Word address


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Channel S0 , Right Address Register of F i rs t L ine Address Processed


Address: 0x0401C

31 28 27 16


15 8 7 6 5 4 3 2 1 0


workRight Address


2:0 R/W Right Address Right address of the first line processed of the source



Right = Left + (PixSiz * Width + 7) / 8 1

4:3 R/W Bit 4 to 3: Byte address within word



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Channel S1 Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_S1_REG)

Address: 0x04020

31 28 27 16


15 8 7 6 5 4 3 2 1 0


workLeft Address


2:0 RW Left Address Left address of the first line processed of the source



Note that because the left address is Byte aligned the bit 2

to 0 are always 0.

4:3 RW Byte address within word



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Channel S1 Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_S1_REG)

Address: 0x04024

31 28 27 16


15 8 7 6 5 4 3 2 1 0


workRight Address


2:0 RW Right Address Right address of the first line processed of the source




4:3 RW Byte address within word



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Channel D Left Address Register of First Line Processed (BLT_LEFT_ADDRESS_D_REG)

Address: 0x04028

31 28 27 16


15 8 7 6 5 4 3 2 1 0


workLeft Address


2:0 R/W Left Address Left address of the first line processed of the source



Note that because the left address is Byte aligned the bit 2

to 0 are always 0.

4:3 Bit 4 to 3: Byte address within word



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Channel D Right Address Register of First Line Processed (BLT_RIGHT_ADDRESS_D_REG)

Address: 0x0402C

31 28 27 16


15 8 7 6 5 4 3 2 1 0


workRight Address


2:0 R/W Right Address Right address of the first line processed of the source




4:3 Bit 4 to 3: Byte address within word



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Pitch Size for Channel S0 (BLT_S0_PITCH_SIZ_REG)

Address: 0x04030

31 16

Reserved

15 0

Pitch


15:0 R/W Pitch Number of words for jumping from one line to the next

(beginning to beginning).

Used when Channel S0 is enabled.


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Pitch Size for Channel S1 (BLT_S1_PITCH_SIZ_REG)

Address: 0x04034

31 16

Reserved

15 0

Pitch


15:0 R/W Pitch Number of words for jumping from one line to the next

(beginning to beginning).

850pm2.0

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