8086-microprocessor-architecture-120207111857-phpapp01 (1).pptx

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    6 Biticroprocessor

    Nit

    12

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    Need of Microprocessor in Instrumentation

    • Intelligent Instrumentation

    • Facilitates communication and control

    •  Automation

     

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    Features of 8086

    16-Bit Processor

    ALU, Registers work with 16 Bit binary word

    It has a 16 bit data bus

    Can read or write data to a memory/port either 16bits or 8 bit at a tim

    Has a 20bit address bus meaning it can address up to 220 = 1MB memo

    Fourteen , 16-Bit Registers

    Frequency range of 8086 is 6-10 MHz

    Address ranges from 00000H to FFFFFH

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    Architecture of 8086

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    Functional Blocks

    • !o "locks #I$ and %$.• he #I$ handles all transactions o& data and addresses on the "uses &or %$.

    • he #I$ 'er&orms all "us o'erations such as(Instruction &etching  ()eading and !riting o'erands &or memor*  (+alculating the addresses o& the memor* o'erands

    • %$ e,ecutes instructions &rom the instruction s*stem "*te -ueue

    • #oth units o'erate as*nchronousl* to gie the /0/6 an oerla''ing instruction &etch and e,ecution mechanism !hich is called as Pipelining  his results in e&&icient use o& the s*stem "us and s*stem 'er&ormance.

     

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    Bus Interface Unit

    • emor*• 6("*te Instruction ueue

    • he 4egment )egisters +4 D4 %4 44• he Instruction ointer I.• he Address 4umming "lock 7

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    Memory

    The memory in an 8086 based system is organized as segmented memory.

    The CPU 8086 is able to address 1Mbyte of memory.

    The Complete physically available memory may be divided into a number of log

    The size of each segment is 64 KB

    A segment is an area that begins at any location which is divisible by 16.

    The 4 segments are Code, Data, Extra and Stack segments.

    Each of these segments can be used for a specific function.

    • Code segment is used for storing the instructions.• The stack segment is used as a stack and it is used to store the return address.• The data and extra segments are used for storing data byte.

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    Queue

    The BIU uses a mechanism known as an instruction stream queue to implemearchitecture.

    This queue permits pre-fetch of up to 6 bytes of instruction code.

    These pre-fetching instructions are held in its FIFO queue. With its 16 bit datafetches two instruction bytes in a single memory cycle.

    After a byte is loaded at the input end of the queue, it automatically shifts up FIFO to the empty location nearest the output

    The EU accesses the queue from the output end. It reads one instruction byte from the output of the queue.

    The intervals of no bus activity, which may occur between bus cycles are know

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    Segment Registers

    • 8 4egment registers

    •  All are 16 "it registers.

    • %ach o& the 4egment registers store the u''er 16 "itaddress o& the starting address o& the corres'ondingsegments.

    Data Segmregister

    StackSegmentregister

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    •Containing address of 64 KB segment with proc•Used to access instructions referenced by instruregister.

    Code segment

    •Containing address of 64KB segment with prog•Data referenced by the stack pointer (SP) and baregisters is located in the stack segment.

    Stack segment

    •Containing address of 64KB segment with prog•Assumes all data referenced by general registersand index register (SI, DI) is located in the data Data segment

    •Containing address of 64KB segment, usually w•Assumes that the DI register references the ES smanipulation instructions.

    Extra segment

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    Instruction Pointer and Summing Block

    • he instruction 'ointer register contains a 16("ito&&set address o& instruction that is to "e e,ecutedne,t.

    • he I al!a*s re&erences the +ode segment register +4.

    • he alue o& the instruction 'ointer is incremented a&ter e,ecuting eer* i nstruction.

    • o& orm a 20"it address o& the ne,t instruction the 16 "it address o& the I is added "* the address summing "lock to the address contained in the +4 !hich has "een shi&ted &our "its to the le&t.

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    Execution Unit

    • Decodes instructions &etched "* the #I$• 9enerate control signals

    • %,ecutes instructions.

    he main 'arts are:

    • +ontrol +ircuitr*• Instruction decoder 

    •  A;$• )egisters

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     A< A;

    #< #;

    +< +;

    D< D;

    4

    #

    4I

    DI

      / "its   / "its

      16 "its

    Accumu

    Base

    Count

    Data

    Stack Po

    Base Po

    Source I

    Destinat

    AX

    BX

    CX

    DX

    Pointer 

    Index

      / "its   / "its

      16 "its

    Accumu

    Base

    Count

    Data

    Stack Po

    Base Po

    Source I

    Destinat

    General Purpose Registers

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    Register Purpose

    AX I/O operations and String manipulation

    !X Store address in"ormation

    #X Counter in string manipulation and shift/rotate instructions

    DX $sed as a port num%er in I/O operations In integer 3multipl' and di(ide instru)tion t*e +X register )ontaorder ,ord o" t*e initial or resulting num%er

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    •SP: Stack pointer•Used with SS to access the stack segment

    •BP: Base Pointer•Primarily used to access data on the stack

    Pointer

    •SI: Source Index register• Required for some string manipulation operations•SI is associated with the DS in string operations

    •DI: Destination Index register• Is also required for some string operations.•DI is associated with the ES in string operations

    Index Register

    •A flag is a flip flop which indicates some conditions produced by theinstruction or controls certain operations of the EU .Flag Register

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    Flag Purpose

    ra' F

     A control &lag.

    %na"les the tra''ing through an on(chi' de"ugging

    &eature.

    Interru't IF A control &lag.+ontrols the o'eration o& the IN) interru't re-uest

    I=0> IN) 'in disa"led. I=1> IN) 'in ena"led.

    Direction DF

     A control &lag.

    It selects either the increment or decrement mode &or D

    and Bor 4I registers during the string instructions.

    Cer&lo! CF

    Cer&lo! occurs !hen signed num"ers are added or

    su"tracted. An oer&lo! indicates the result has e,ceede

    the ca'acit* o& the achine

    I

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    • Is a maskable hardware interrupt.• When an interrupt occurs, the processor stores FLAGstack, disables further interrupts, fetches from the bus

    representing interrupt type, and jumps to interrupt p

    INTR

    • Is a non-maskable interrupt.• Interrupt is processed in the same way as the INTR inhigher priority then the maskable interrupt.NMI

    • Software interrupt processing is the same as for the hinterrupts.

    Softwareinterrupts

    Interrupts

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    Applications of 8086

    • Patient Monitoring in Intensive Care Unit.• Pathological Analysis• Measurement of heart activity.• MRI scanning and CT scanning etc.

    Instrumentation

    • In home appliances, such as microwave oven, washinmachine etc.

    • In controlling various parameters like speed, pressurtemperature etc.

    Automation andControl

    • In digital telephone sets.• Telephone exchanges and modem etc.• In television, satellite communication teleconferencin

    Communication

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     -*an.