INTRODUCTION TO 8086 MICROPROCESSOR

Introduction

The Intel 8086 is a 16-bit microprocessor that is intended to be used as the CPU in a microcomputer. 16-bit indicates that the word length of the microprocessor. The 8086 microprocessor has a 16-bit data bus and hence it’s ALU and internal registers are able to process 16 bits of information at a time. To speed up the processing, 8086 divides the work to be done into two functional units namely Execution Unit (EU) and Bus Interface Unit (BIU). The BIU is responsible for the transfer of data and addresses on the buses for the EU. The EU instructs the BIU to fetch the instructions or data from the memory, decodes the instructions and executes instructions. The 8086 microprocessor produces the physical address by adding the effective address to the contents of any one of the four segment registers and this way of addressing the memory is called segment:offset notation. The effective address of the operands can be calculated in different ways and hence effective address calculation leads to different addressing modes. To program 8086 and to develop 8086 based systems it is necessary to study about the instruction set of 8086. Overall, this unit makes you to learn the architecture, memory addressing and instruction set of 8086 microprocessor.

8086 Architecture

The architecture of 8086 includes Arithmetic Logic Unit (ALU), flags, general registers, instruction byte queue and segment registers. The 8086 CPU logic has been partitioned into two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU) as shown in figure 2.1. The major reason for this separation is to increase the processing speed of the processor. You please observe that this separation and the increase in the word length improve the performance of 8086 in comparison with that of 8085. These two units cooperate asynchronously. The BIU has to interact with memory and input and output devices in fetching the instructions and data required by the EU and in sending the results produced by EU to the memory or the output device. As the name implies, the EU is responsible for executing the instructions of the programs and to carry out the required processing. EU gives the instructions to the BIU to decide where to fetch instructions or data from and where to send the result. In addition to giving the instructions to the BIU, EU decodes instructions and executes instructions.

Figure 2.1 Functional Components of 8086 Architecture

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Detailed view of 8086 architecture is shown in figure 2.2.

Figure 2.2 Detailed Architecture of 8086 Microprocessor

The Execution Unit (EU)

The Execution Unit (EU) of 8086 microprocessor has control unit, instruction decoder, Arithmetic and Logical Unit (ALU), general registers, flag register, pointers and index registers.

Control unit is responsible for the co-ordination of all other units of the processor. It generates timing and control signals which are necessary for the execution of instructions. It controls the data flow between CPU and peripherals (including memory). It provides status, control and timing signals which are required for the operation of memory and I/O devices. It directs the internal operations of the processor. In short, we can say that it controls the entire operations of the microprocessor and peripherals connected to the microprocessor. Hence you can understand that control unit is like the brain of an 8086 based microcomputer system.

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The EU of 8086 has a 16-bit ALU. ALU performs various arithmetic and logical operations over the data. It takes care of all manipulations required over the data to produce the required output. Some frequently performed operations are addition, subtraction, logical AND, logical OR, logical XOR, complement, left shift, right shift etc.

The instruction decoder translates the instructions fetched from the memory into a series of actions that are carried out by the EU. Instruction decoding is the process of segregating the instruction into opcode and operands.

Registers

Various registers present in the EU can be divided into three categories namely general registers, flag register and pointers and index register.

General Registers

General registers are used for temporary storage and manipulation of data and instructions. Data remain in the registers till they are sent to the memory or I/O devices. The various general registers are shown in figure 2.3.

Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the

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low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions.

Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

Figure 2.3 General Registers of 8086

Flag Register

This register is a 16-bit register containing a collection of 9 flags (each flag is a flip flop) as shown in figure 2.4. Each of these flip flops holds 1-bit flag that indicates certain conditions which arises during arithmetic and logic operations.

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Figure 2.4 Flag Register of 8086

The meanings of each flag are shown below.

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand.

Direction Flag (DF) - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero.

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Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.

Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation.

Since flag register reflects the happenings inside the 8086 microprocessor, it is called the Program Status Word (PSW). The contents of PSW, accumulator and other registers are saved in the stack during the handling of interrupt. Flag registers can be summarized as follows.

Pointers and Index registers

Pointer registers are used to point to a particular location either in memory or stack from which the data is to be read or to which the data is to be written. Index registers are

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useful in implementing sophisticated addressing modes (identifying the location of the operands). The EU of 8086 has the set of pointers and index registers as shown in figure 2.5. The functions of pointers and index registers are explained as follows.

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data addresses in string manipulation instructions.

Figure 2.5 Pointers and Index registers of 8086

The Bus Interface Unit (BIU)

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The BIU has an instruction stream byte queue, a set of segment registers and instruction pointer.

Instruction Byte Queue

8086 instructions vary from 1 to 6 bytes. Therefore fetch and execution are taking place concurrently in order to improve the performance of the microprocessor. The BIU feeds the instruction stream to the execution unit through a 6 byte prefetch queue. This prefetch queue can be considered as a form of loosely coupled pipelining. Execution and decoding of certain instructions do not require the use of buses. While such instructions are executed, the BIU fetches up to six instruction bytes for the following instructions (the subsequent instructions). The BIU store these prefetched bytes in a first-in-first out register by name instruction byte queue. When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in BIU. This process is much faster since it forms a pipeline.

Segment Registers

In 8086, program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory.

Memory can be thought of as a vast collection of bytes. These bytes need to be organized in some efficient manner in order to be of any use. A simple scheme would be to order the bytes in a serial fashion and number them from 0 (or 1) to the end of memory. The numbers thus given to the individual positions in memory are called ADDRESSES. The problem with this approach is that towards the end of memory, the addresses become very large. For example, if a computer has 1 Megabyte of RAM, the highest address would be 1048575 (=1024*1024-1). This definitely would not fit in a 16-bit register and therefore addresses need to be stored in two registers. The scheme used in the 8086 is called segmentation. Every address has two parts, a SEGMENT and an OFFSET. The segment indicates the starting of a 64 kilobyte portion of memory, in multiples of 16. The offset indicates the position within the 64k portion.

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Absolute address = (segment * 16) + offset

The memory of 8086 is divided into 4 segments namely code segment (program memory), data segment (data memory), stack memory (stack segment) and extra memory (extra segment). The various segments of the memory and the corresponding segment registers are shown in figure 2.6 and they are explained as follows.

Program memory – Program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction.

Data memory – The processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks).

Stack memory – A stack is a section of the memory set aside to store addresses and data while a subprogram executes. The stack segment register is used to hold the upper 16 bits of the starting address for the program stack.

Extra segment – This segment is also similar to data memory where additional data may be stored and maintained. This area is very often used for string related operations.

Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons.

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Code Segment (CS) register is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.

Stack Segment (SS) register is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.

Data Segment (DS) register is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.

Extra Segment (ES) register is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions.

Figure 2.6 Memory Segments and Segment Register

Instruction Pointer

The instruction pointer contains a 16-bit offset which tells where in that 64-Kbyte code segment the next instruction byte is to be fetched from. The actual physical address sent to memory is produced by adding the offset contained in the IP register to the segment base represented by the upper 16 bits in the CS register.

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Segment: Offset Notation

Segment: Offset addressing was introduced at a time when the largest register in a CPU was only 16-bits (or two bytes) which meant that it could address only 65,536 bytes (64kb) of memory directly. But everyone was hungry for a way to run programs that were much larger than 64kb. Rather than creating a CPU with larger register sizes (of at least 24-bits just to add another byte), the CPU designers at Intel decided to stick with only 16-bit registers for their 8086 CPU and change the way it would use them: They expanded the instruction set so it could group two 16-bit registers together whenever the program needed to tell the CPU to use an Absolute memory location that was too far off for a single two byte register to contain the reference.

Unfortunately, they didn't simply combine two registers into a high and low order (which would have given us a way to access up to 4 Gigabytes of memory. Instead, they came up with the Segment: Offset scheme which allowed a CPU to effectively address only about 1 Megabyte of memory. Keep in mind, however, that this was at a time when no one could dream of a PC with more than 640kb of memory

The scheme works like this: The value in any register considered being a Segment register is multiplied by 16 (or shifted one hexadecimal byte to the left; add an extra 0 to the end of the hex number) and then the value in an Offset register is added to it. So, the Absolute address for any combination of Segment and Offset pairs is found by using the formula

Physical Memory Location = (Segment value * 16) + Offset Value

This will become a lot easier once you've seen a few examples. The Absolute or Linear address for the Segment: Offset pair, F000: FFFD can be computed quite easily in your mind by simply inserting a zero at the end of the Segment value ( which is the same as multiplying by 16 ) and then adding the Offset value:

F0000

+ FFFD

------

FFFFD or 1,048,573(decimal)

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Here's another example: 923F:E2FF ->

923F0

+ E2FF

------

A06EF or 657,135(decimal)

Now let's compute the Absolute Memory location for the largest value that can be expressed using a Segment: Offset reference

FFFF0

+ FFFF

-------

10FFEF or 1,114,095 (decimal)

In reality, it wasn't until quite some time after the 8086, that such a large value actually corresponded to a real Memory location. Once it became common for PCs to have over 1MB of memory, programmers developed ways to use it to their advantage and this last byte became part of what's now called the HMA (High Memory Area). But until that time, if a program tried to use a Segment: Offset pair that exceeded a 20-bit Absolute address (1MB), the CPU would truncate the higher bits, effectively mapping any value over FFFFFh (1,048,575) to an address within the first Segment. Thus, 10FFEFh was mapped to FFFEh.

One of the downsides in using Segment: Offset pairs (and likely what confuses most of you) is the fact that a large number of these pairs refer to the same exact memory locations. For example, every Segment: Offset pair below, refers to exactly the same location in memory:

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0007:7B90 0008:7B80 0009:7B70 000A:7B60 000B:7B50 000C:7B40

0047:7790 0048:7780 0049:7770 004A:7760 004B:7750 004C:7740

0077:7490 0078:7480 0079:7470 007A:7460 007B:7450 007C:7440

01FF:5C10 0200:5C00 0201:5BF0 0202:5BE0 0203:5BD0 0204:5BC0

07BB:0050 07BC:0040 07BD:0030 07BE:0020 07BF:0010 07C0:0000

All the above Segment: Offset pairs are only some of the many ways to refer to the single absolute memory location of 7C00h.

As a matter of fact there may be up to 4096 different Segment: Offset pairs for addressing a single byte in Memory; depending upon its particular location. For absolute addresses 0h through FFEFh (o through 65,519), the number of different pairs can be computed as follows:

Divide the absolute address by 16 (which shifts all the hex digits one place to the right)

Throw away any fractional remainder and add 1

This is the same thing as saying: Add 1 to the segment number if the offset is 000Fh (15) or less. For example, the byte in memory referenced by the Segment: Offset pair 0040:0000 has a total of 41h (or 65) different pairs that might be used. For the Absolute address 7C00h, which was mentioned above, there's a total of: 7C00 / 10h --> 7C0 + 1 = 7C1 (or 1,985) relative ways to address this same memory location using Segment: Offset pairs. For the absolute addresses from FFF0h (65,520) all the way through FFFFFh (1,048,575), there will always be 4,096 Segment: Offset pairs one could use to refer to these addresses. That's a little over 88% of the memory that can be accessed using Segment: Offsets. The last 65,520 bytes that can be accessed by this method are collectively called the High Memory Area (HMA). For each 16 bytes higher in the HMA that we point to, there is one less Segment: Offset pair available to reference that paragraph.

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Since BIU takes care of the interaction with memory and other peripherals EU is able to concentrate in the processing of data. Moreover the maintenance of the instruction queue enables the 8086 microprocessor unit (MPU) to achieve pipelining. Overall, the performance of 8086 is improved considerably.

Have you understood?

1. What are the two functional units of 8086 processor?

2. What is the function of the BIU?

3. What is the function of the EU?

4. What is the purpose of the Instruction Queue of BIU?

5. How does the physical memory location is computed in segment:offset notation?

6. What is the function of the base pointer?

7. What are the functions of SI and DI registers?

8. State the purpose of the four segment registers.

Properties and Pin Description

Intel 8086 is a 16-bit HMOS microprocessor. It is a 40 pin IC. It uses a 5V d.c. supply for its operation. The 8086 uses 20-line addresses bus. It can directly address up to 1MB (220=1MB) of memory address. It uses 16-line data bus. 16-bit data word is sub divided into a low-order byte and a high-order byte. The 20 lines of the address bus operate in multiplexed mode. The 16-low order address bus lines are multiplexed with data and 4 high-order address bus lines are multiplexed with status signals. The schematic diagram of Intel 8086 is shown in figure 2.7.

AD0-AD15 (Bidirectional) – Address/Data bus. These are low order address bus. They are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.

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A16-A19 (Output) – High order address bus. These are multiplexed with status signals.

A16/S3, A17/S4, A18/S5, A19/S6 – The specified address lines are multiplexed with corresponding status signals.

BHE (Active Low)/S7 (Output) – Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.

RD (Read) (Active Low) – The signal is used for read operation. It is an output signal. It is active when low.

READY (Input) – The addressed I/O or memory sends acknowledgement through this pin. When HIGH it indicates that the peripheral is ready to transfer data.

RESET (Input) – System reset. The signal is active high.

CLK (Input) – Clock. 5, 8 or 10 MHz.

INTR – Interrupt Request

NMI (Input) – Non-maskable Interrupt Request

TEST (Active Low) (Input) – Wait for test control. When it is low the microprocessor continues execution otherwise waits.

Vcc – Power Supply ( +5V D.C.)

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GND – Ground

Figure 2.7 Pin diagram of 8086

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