8086 and memory interfacing
TRANSCRIPT
8086 Processor Pin Details (Hardware)
8086 and Memory Interfacing
Bore Gowda S BECE Department Manipal Institute of TechnologyManipal-576104
In the design of all computers, semiconductor memories are used as primary storage for data and codeThey are connected directly to the CPU and they are the memory the CPU asks for information (code or data) Among the most widely used are RAM and ROMThe physical address space, or memory map, of a microprocessor refers to the range of addresses of memory location that can accessed by the microprocessor. The size of the address space depends on the number of address lines of the microprocessor.At least two memory devices are required in a microprocessor system: one for the ROM and one for the RAM.In an 8086 the high addresses in the memory map should always be occupied by a ROM, while the low addresses in the memory map should always be occupied by a RAM.
Memory CapacityThe number of bits/bytes that a semiconductor memory chip can store is called its chip capacity
Memory organization
A memory device or memory chip must have three types of lines or connections: Address, Data, Enable and Control.Address Lines: The input lines that select a memory location within the memory device.Decoders are used, inside the memory chip, to select a specific locationThe number of address pins on a memory chip specifies the number of memory locations.If n specifies the number of address lines, thenNumber of memory location = 2n
Memory organization
Data Lines:
The data pins are typically bi-directional in read-write memories. The number of data pins is related to the size of the memory location . For example, an 8-bit wide (byte-wide) memory device has 8 data pinsThe number of data lines (m-bits) determines the size of each location in the memory.
Memory Capacity = 2n x m
Memory organization
Memory organization
5
2n wordsm-bits per word
Chip select
Read/Write
n-address linesA0 - An
m-data linesD0 - Dm
RAM Memory Chip
2n wordsm-bits per word
Chip select
Write
n-address linesA0 - An
m-data linesD0 - Dm
RAM Memory Chip
Read
Memory organization
6
2n wordsm-bits per word
Chip select
Read
n-address linesA0 - An
m-data linesD0 - Dm
ROM Memory Chip
Memory organization
Memory Interfacing
Memory Decoding
In general, all the memory locations are not implemented.All the address are not used by the memory devices to select particular memory locations.The unused lines are used to decode to generate chip select signals.Basically, two techniques are used to decode the addressAbsolute or Full decodingLinear or Partial decodingFull DecodingAll of the higher address lines are decoded to select memory chip, and the chip is selected only for the specified logic levels on these high order address lines.Each memory location has unique addressDisadvantages: it needs more hardware for decoding
Partial Decoding
All the address lines are not used to generate chip select, basically used in small systemsIndividual high order address lines are used to decode the chip select for the memory chips using less hardwareDisadvantages: Each memory location has more than one address called roll-over addresses (fold back or shading).
Decoding circuits
NAND gatesDecodersProgrammable Logic Devices(PLAs, PAL, GAL)Comparators
Memory Decoding
Interface two 4Kx8 EPROM (8Kx8) chips to 8086. Select suitable address maps
Note: The address of RAM may be selected anywhere in the 1MB address space.The address of EPROM/ROM may be selected such that the address FFFF0H must lie in this space.
To address 8K=23 x 210 = 213 , the processor needs 13 address linesSo address lines A0 A12 used to address 8K locations A13 A19 are used to generate chip select signal
Address Map/ Address decoding Table
CHIPS
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADDRESS
EPROM(Oand E)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FFFFFH
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
FE000H
To decoder
To 4K Memory IC