8085 arch_interfacing io

8/4/2019 8085 Arch_Interfacing IO

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Microprocessors & Interfacing 1

The 8085 Microprocessor Architecture


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The 8085 and Its Busses

The 8085 is an 8-bit general purposemicroprocessor that can address 64K Byte ofmemory.

It has 40 pins and uses +5V for power. It can runat a maximum frequency of 3 MHz.

The pins on the chip can be grouped into 6 groups:

Address Bus.

Data Bus.

Control and Status Signals.

Power supply and frequency.

Externally Initiated Signals.

Serial I/O ports.


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Pinout Diagram of 8085U7

8085

36

1

2

5

6

9

8

7

10

11

29

33

39

35

12

13

14

15

16

17

1819

21

2223

24

25

26

27

28

30

31

32

34

3

374

38

40

20

RST-IN

X1

X2

SID

TRAP

RST 5.5

RST 6.5

RST 7.5

INTR

INTA

S0

S1

HOLD

READY

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A8

A9

A10

A11

A12

A13

A14

A15

ALE

WRRD

IO/M

RST-OT

CLKOSOD

HLDA

VCC

VSS


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Logic Pinout of 8085

DataBu

s

A

ddressBus

8085

36

1

2

5

6

9

8

7

10

11

29

33

39

35

12

13

1415

16

17

18

19

21

22

23

24

25

26

27

28

30

31

3234

3

37

4

38

40

20

RST-IN

X1

X2

SID

TRAP

RST 5.5RST 6.5

RST 7.5

INTR

INTA

S0

S1

HOLD

READY

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A8

A9

A10A11

A12

A13

A14

A15

ALE

WR

RD

IO/M

RST-OT

CLKO

SOD

HLDA

VCC

VSS

Control &Status

Control &

Status

Externally

initiated

signals

Serial I/O

ports

Power Supply &frequency


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Intel 8085 CPU Block Diagram


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Registers hold temporary data. Instruction register (IR) holds the currently executinginstruction.

Instruction Decoder (ID)- decodes the instruction.

Once decoded, the instruction controls the remainderof the MPU, memory and IO through the timing andcontrol block.

The 8085 Block Diagram


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Temporary register- holds information from thememory or register array. An input of the ALU.

Increment/Decrement address latch It adds orsubtracts one from any of other registers in registerarray.

The 8085 Block Diagram

Why are the PC and SP registers are 16-bit ?


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Registers

The 8085 includes six registers, one accumulator, and oneflag register.

In addition, it has two 16-bit registers: the stack pointer

and the program counter.

They are described briefly as follows.The 8085 has six general-purpose registers to store 8-bit

data; these are identified as B,C,D,E,H, and L .

They can be combined as register pairs - BC, DE, and HL -

to perform some 16-bit operations.The programmer can use these registers to store or copy

data into the registers by using data copy instructions.


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Accumulator

The accumulator is an 8-bit register that is a part of

arithmetic/logic unit (ALU).

This register is used to store 8-bit data and to perform

arithmetic and logical operations.

The result of an operation is stored in the accumulator. Theaccumulator is also identified as register A.


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Flags

The ALU includes five flip-flops, which are set or reset after an

operation according to data conditions of the result in theaccumulator and other registers.

They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and

Auxiliary Carry (AC) flags. The most commonly used flags are

Zero, Carry, and Sign.The microprocessor uses these flags to test data conditions.

For example, after an addition of two numbers, if the sum in

the accumulator is larger than eight bits, the flip-flop used to

indicate a carry -- called the Carry flag (CY) -- isset to one.


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Five bit positions out of eight are used to store the outputs of

the five flip-flops. The flags are stored in the 8-bit register sothat the programmer can examine these flags (data conditions)

by accessing the register through an instruction.

These flags have critical importance in the decision-makingprocess of the microprocessor.

The conditions (set or reset) of the flags are tested through the

software instructions. For example, the instruction JC (Jump on

Carry) is implemented to change the sequence of a program

when CY flag is set. The thorough understanding of flag is

essential in writing assembly language programs.


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Program Counter (PC)

This 16-bit register deals with sequencing the execution of

instructions. This registeris a memory pointer. Memory locations have 16-bit addresses,

and that is why this is a

16-bit register.

The microprocessor uses this register to sequence the executionof the instructions.

The function of the program counter is to point to the memory

address from which the

next byte is to be fetched. When a byte (machine code) is beingfetched, the program

counter is incremented by one to point to the next memory

location.


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Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory

pointer. It points to a memory location in R/W memory,

called the stack.

The beginning of the stack is defined by loading 16-bit

address in the stack pointer.


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Control Unit

Generates signals within microprocessor to carry out the

instruction, which has been decoded. In reality causes certainconnections between blocks of the microprocessor to be

opened or closed, so that data goes where it is required, and

ALU operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation

such as add, subtract, AND, OR, etc. Uses data frommemory and from Accumulator to perform arithmetic. Always

stores result of operation in Accumulator.


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Instruction Register/Decoder

Temporary store for the current instruction of a program.

Latest instruction is sent here from memory prior to

execution. Decoder then takes instruction and decodes or

interprets the instruction. Decoded instruction is then

passed to next stage.


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8085 MPU has 3 pins

that control or presentthe clock signal.

X1 and X2 pinsdetermine theclock frequency.

CLK OUT is a TTLsquare-waveoutput clock.

The CLOCK OUT is

one-half the crystalfrequency.

Clock Pins

8085A

X1 CLKOUT

X2

6 MHz


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8085 p consists of 16 signal pins used as address bus.

Divided into 2 part: A15 A8 (upper) andAD7 AD0 (lower). A15A8 : Unidirectional, known as high order

address. AD7 AD0 : bidirectional and dual purpose (address

and data placed once at a time). AD7AD0 also known as low order address. To execute an instruction, at early stage AD7 AD0

uses as address bus and alternately as data bus forthe next cycle.

The method to change from address bus to data busknown as bus multiplexing.

8085 Pinout


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Group of signals consists of : Two control signals (RD read; and WR - write).

Three status signals (IO/M, S1, and S0) to recognizenature of operation.

ALE (Address Latch Enable) signal : active high signal - generated to show the start of 8085

operation.

When transition 1-to-0: indicate that lines AD7-AD0 (AD7-AD0 = A7-A0) act as address lines.

8085 Pinout


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ALE used to demultiplex address/data bus


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The Address and Data Busses

The address bus has 8 signal lines A8 A15which are unidirectional.

The other 8 address bits are multiplexed (timeshared) with the 8 data bits.

So, the bits AD0 AD7 are bi-directional andserve as A0 A7 and D0 D7 at the same time.

During the execution of the instruction, these lines carrythe address bits during the early part, then during the lateparts of the execution, they carry the 8 data bits.

In order to separate the address from the data, wecan use a latch to save the value before thefunction of the bits changes.


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The Control and Status Signals

There are 4 main control and status signals.These are:

ALE: Address Latch Enable. This signal is a pulse thatbecome 1 when the AD0 AD7 lines have an addresson them. It becomes 0 after that. This signal can be usedto enable a latch to save the address bits from the AD

lines.

RD: Read. Active low.

WR: Write. Active low.

IO/M: This signal specifies whether the operation is a

memory operation (IO/M=0) or an I/O operation(IO/M=1).

S1 and S0 : Status signals to specify the kind ofoperation being performed .Usually un-used in smallsystems.


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Frequency Control Signals

There are 3 important pins in the frequencycontrol group. X0 and X1 are the inputs from the crystal or clock

generating circuit.

The frequency is internally divided by 2.

So, to run the microprocessor at 3 MHz, a clock running at6 MHz should be connected to the X0 and X1 pins.

CLK (OUT): An output clock pin to drive the clockof the rest of the system.

We will discuss the rest of the control signals aswe get to them.


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Control and Status Signals.


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Microprocessor Communication and Bus Timing

To understand how the microprocessor operatesand uses these different signals, we should studythe process of communication between themicroprocessor and memory during a memoryread or write operation.

Lets look at timing and the data flow of aninstruction fetch operation. (Example 3.1)


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Steps For Fetching an Instruction

Lets assume that we are trying to fetch theinstruction at memory location 2005. That meansthat the program counter is now set to that value.

The following is the sequence of operations:

The program counter places the address value on the

address bus and the controller issues a RD signal. The memorys address decoder gets the value and

determines which memory location is being accessed.

The value in the memory location is placed on the databus.

The value on the data bus is read into the instructiondecoder inside the microprocessor.

After decoding the instruction, the control unit issues theproper control signals to perform the operation.


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Timing Signals For Fetching an Instruction

Now, lets look at the exact timing of thissequence of events as that is extremelyimportant. (figure 3.3) At T1 , the high order 8 address bits (20H) are placed on the

address lines A8 A15 and the low order bits are placed on AD7AD0. The ALE signal goes high to indicate that AD0 AD8 are

carrying an address. At exactly the same time, the IO/M signal goeslow to indicate a memory operation.

At the beginning of the T2 cycle, the low order 8 address bits areremoved from AD7 AD0 and the controller sends the Read (RD)signal to the memory. The signal remains low (active) for two clock

periods to allow for slow devices. During T2 , memory places thedata from the memory location on the lines AD7 AD0 .

During T3 the RD signal is Disabled (goes high). This turns off theoutput Tri-state buffers in the memory. That makes the AD7 AD0lines go to high impedence mode.


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Demultiplexing AD7-AD0

From the above description, it becomes obvious that

the AD7 AD0 lines are serving a dual purpose andthat they need to be demultiplexed to get all theinformation.

The high order bits of the address remain on the busfor three clock periods. However, the low order bits

remain for only one clock period and they would be lostif they are not saved externally. Also, notice that thelow order bits of the address disappear when they areneeded most.

To make sure we have the entire address for the fullthree clock cycles, we will use an external latch to savethe value of AD7 AD0 when it is carrying the addressbits. We use the ALE signal to enable this latch.


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Demultiplexing AD7-AD0

Given that ALE operates as a pulse during T1, wewill be able to latch the address. Then when ALE

goes low, the address is saved and the AD7 AD0lines can be used for their purpose as the bi-directional data lines.

A15-A8

LatchAD7-AD0

D7- D

0

A7- A

0

8085

ALE


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Cycles and States

From the above discussion, we can define termsthat will become handy later on: T- State: One subdivision of an operation. A T-state

lasts for one clock period.

An instructions execution length is usually measured in a

number of T-states. (clock cycles). Machine Cycle: The time required to complete one

operation of accessing memory, I/O, or acknowledgingan external request.

This cycle may consist of 3 to 6 T-states.

Instruction Cycle: The time required to complete theexecution of an instruction.

In the 8085, an instruction cycle may consist of 1 to 6machine cycles.


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Generating Control Signals

The 8085 generates a single RD signal.However, the signal needs to be used with bothmemory and I/O. So, it must be combined withthe IO/M signal to generate different controlsignals for the memory and I/O.

Keeping in mind the operation of the IO/M signalwe can use the following circuitry to generate theright set of signals:


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A closer look at the 8085 Architecture

Previously we discussed the 8085 from aprogrammers perspective.

Now, lets look at some of its features with moredetail.


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The ALU

In addition to the arithmetic & logic circuits, theALU includes the accumulator, which is part ofevery arithmetic & logic operation.

Also, the ALU includes a temporary register usedfor holding data temporarily during the executionof the operation. This temporary register is notaccessible by the programmer.


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The Flags register

There is also the flags register whose bits are

affected by the arithmetic & logic operations. S-sign flag

The sign flag is set if bit D7 of the accumulator is set after an arithmetic orlogic operation.

Z-zero flag Set if the result of the ALU operation is 0. Otherwise is reset. This flag is

affected by operations on the accumulator as well as other registers. (DCRB).

AC-Auxiliary Carry This flag is set when a carry is generated from bit D3 and passed to D4 .

This flag is used only internally for BCD operations. (Section 10.5 describesBCD addition including the DAA instruction).

P-Parity flag After an ALU operation if the result has an even # of 1s the p-flag is set.

Otherwise it is cleared. So, the flag can be used to indicate even parity.

CY-carry flag Discussed earlier


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More on the 8085 machine cycles

The 8085 executes several types of instructionswith each requiring a different number ofoperations of different types. However, theoperations can be grouped into a small set.

The three main types are: Memory Read and Write.

I/O Read and Write.

Request Acknowledge.

These can be further divided into variousoperations (machine cycles).


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Opcode Fetch Machine Cycle

The first step of executing any instruction is theOpcode fetch cycle. In this cycle, the microprocessor brings in the

instructions Opcode from memory.

To differentiate this machine cycle from the very similar

memory read cycle, the control & status signals are setas follows:

IO/M=0, s0 and s1 are both 1.

This machine cycle has four T-states.

The 8085 uses the first 3 T-states to fetch the opcode.

T4 is used to decode and execute it.

It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle.


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Memory Read Machine Cycle

The memory read machine cycle is exactly thesame as the opcode fetch except: It only has 3 T-states

The s0 signal is set to 0 instead.


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The Memory Read Machine Cycle

To understand the memory read machine cycle,

lets study the execution of the followinginstruction:

MVI A, 32

In memory, this instruction looks like:

The first byte 3EH represents the opcode for loading abyte into the accumulator (MVI A), the second byte is thedata to be loaded.

The 8085 needs to read these two bytes frommemory before it can execute the instruction.

Therefore, it will need at least two machine cycles. The first machine cycle is the opcode fetch discussed earlier.

The second machine cycle is the Memory Read Cycle.

Figure 3.10 page 83.

2000H

2001H

3E

32


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Machine Cycles vs. Number of bytes in the instruction

Machine cycles and instruction length, do nothave a direct relationship. To illustrate lets look at the machine cycles

needed to execute the following instruction.

STA 2065H

This is a 3-byte instruction requiring 4 machine cycles and 13 T-states.

The machine code will be storedin memory as shown to the right

This instruction requires the following 4 machine cycles: Opcode fetch to fetch the opcode (32H) from location 2010H, decode it and

determine that 2 more bytes are needed (4 T-states).

Memory read to read the low order byte of the address (65H) (3 T-states).

Memory read to read the high order byte of the address (20H) (3 T-states).

A memory write to write the contents of the accumulator into the memorylocation.

2010H

2011H

2012H

32H

65H

20H


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The Memory Write Operation

In a memory write operation: The 8085 places the address (2065H) on the

address bus

Identifies the operation as a memory write(IO/M=0, s1=0, s0=1).

Places the contents of the accumulator on thedata bus and asserts the signal WR.

During the last T-state, the contents of the databus are saved into the memory location.


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Memory interfacing

There needs to be a lot of interaction betweenthe microprocessor and the memory for theexchange of information during programexecution.

Memory has its requirements on control signals

and their timing. The microprocessor has its requirements as well.

The interfacing operation is simply the matchingof these requirements.


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Memory structure & its requirements

The process of interfacing the above two chips isthe same.

However, the ROM does not have a WR signal.

AddressLines

DateLines

CS

RDOutput Buffer

ROM

AddressLines

Data Lines

CS

RDOutput Buffer

RAMWRInput Buffer

Data Lines


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Interfacing Memory

Accessing memory can be summarized into the

following three steps: Select the chip.

Identify the memory register.

Enable the appropriate buffer.

Translating this to microprocessor domain: The microprocessor places a 16-bit address on the

address bus.

Part of the address bus will select the chip and the otherpart will go through the address decoder to select the

register. The signals IO/M and RD combined indicate that a

memory read operation is in progress. The MEMR signalcan be used to enable the RD line on the memory chip.


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Microprocessors & Interfacing43

Address decoding

The result of address decoding is theidentification of a register for a given address. A large part of the address bus is usually

connected directly to the address inputs of thememory chip.

This portion is decoded internally within the chip. What concerns us is the other part that must be

decoded externally to select the chip.

This can be done either using logic gates or a

decoder.


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The Overall Picture

Putting all of the concepts together, we get:

A15-A8

LatchAD7-AD0

D7- D

0

A7- A

0

8085

ALE

IO/MRDWR

1K ByteMemory

Chip

WRRD

CS

A9- A

0

A15

- A10

Chip Selection

Circuit


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8085 Operations

Microprocessor Initiated Operations Internal Operations Peripheral/Externally Initiated Operations


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Microprocessor Initiated Operations

Memory Read Memory Write I/O Read

I/O Write


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Internal Operations

Store 8-bit data Perform Arithmetic and Logic Operations Test for conditions

Sequence the execution of instructions Store/Retrieve data from stack during execution

P i h l/E t ll I iti t d O ti


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Peripheral/Externally Initiated Operations

Reset Interrupt Ready

Hold


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Interfacing I/O Devices


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Interfacing I/O Devices

Using I/O devices data can be transferred

between the microprocessor and the outsideworld.

This can be done in groups of 8 bits using theentire data bus. This is called parallel I/O.

The other method is serial I/O where one bit istransferred at a time using the SI and SO pins onthe Microprocessor.


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Dealing with I/O Devices

There are two ways to deal with I/O devices. Consider them like any other memory location.

They are assigned a 16-bit address within the addressrange of the 8085.

The exchange of data with these devices follows thetransfer of data with memory. The user uses the same

instructions used for memory. This is called memory-mapped I/O.

Treat them separately from memory: I/O devices are assigned a port number within the 8-bit

address range of 00H to FFH.

The user in this case would access these devices usingthe IN and OUT instructions only.

This is called I/O-mapped I/O or Peripheral-mapped I/O.


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Basic interfacing concepts

The first step in interfacing an I/O device would

be to determine which instructions will be used toaccess it.

If you want the user to use the IN/OUTinstructions, then it should be interfaced as a

peripheral-mapped I/O device. If the user should use regular data transfer

instructions (LDA, STA, etc.) then it should beinterfaced as a memory-mapped I/O device.


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Peripheral I/O instructions

There are two instructions: IN brings data (8-bits) from an input device to the

accumulator

OUT brings data (8-bits) from the accumulator toan output device.

They are both 2 byte instructions with the secondbyte holding the 8-bit address of the device.

Note: Given that there are separate instructionsfor input and output, the 8085 can actuallycommunicate with 256 different input devicesAND an additional 256 different output devices.


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The execution of the OUT instruction

The OUT instruction requires 3 machine cycles

and 10 T-states. The first cycle is an opcode fetch cycle to fetch the

1st byte of the instruction from memory (OUT).

The second cycle is a memory read cycle to bring

the 8-bit port number from the next location. The third cycle is an I/O write cycle.

In this cycle, the 8085 places the port number on AD0-AD7 AND A8-A15 and the signal WR is set low (active).

Since the device address is placed on both AD0-AD7 aswell as A8-A15, there is no need for de-multiplexing AD0-AD7. A8-A15 can be used directly to identify the device.


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The execution of the IN instruction

The execution of the IN instruction is almost

identical to that of the OUT instruction. 3 machinecycles, 10 T-states.

The first machine cycle is the opcode fetch.

The second cycle is the memory read to get the

port number.

The third is an I/O Read cycle.

Again, in T1 the port address (8-bits) is placed on bothAD0- AD7, and A8-A15. The IO/M signal is set high to

indicate an I/O operation. At the beginning of T2, the RDsignal is set low (active) and the I/O device responds byplacing the 8-bit data on the data bus.


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The interfacing of output devices

Output devices are usually slow.

Also, the output is usually expected to continueappearing on the output device for a long period oftime.

Given that the data will only be present on the

data lines for a very short period (microseconds),it has to be latched externally.

To do this the external latch should be enabled when theports address is present on the address bus, the IO/M

signal is set high and WR is set low.

The resulting signal would be active when the outputdevice is being accessed by the microprocessor.

Decoding the address bus (for memory-mapped devices)follows the same techniques discussed in interfacingmemory.


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Interfacing of input devices

The basic concepts are similar to interfacing of

output devices. The address lines are decoded to generate a signal that

is active when the particular port is being accessed.

An IOR signal is generated by combining the IO/M andthe RD signals from the microprocessor.

A tri-state buffer is used to connect the inputdevice to the data bus. The control (Enable) forthese buffers is connected to the result ofcombining the address signal and the signalIORD.


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Examples of Interfacing I/O Devices

To illustrate the techniques of interfacing I/O

devices we will design the circuits needed tointerface 8 LEDs to display the contents of theaccumulator as well as 8 switches to set thecontents of the accumulator.


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Interfacing the LEDs

Lets first design the external circuit.

The data on the data bus from the microprocessorstays for an extremely short amount of time. So, inorder to keep it long enough for displaying, we willneed an external latch.

We will use an 8-bit latch to hold the data we need toconnect the 8 LED to the latches outputs.

However, the latch will not be able to source

enough current. So, we will use the invertedoutputs and make it sink the current instead.


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When should the latch be enabled?

It needs to be enabled when the data is on the

data bus. That happens when the ALE signal is low.

However, we only want to display the data that isbeing sent to the I/O, we dont want to display the

data being saved in memory. So, the latch needs to be enabled only during I/O

operations. That happens when IO/M=1

Finally we only want to display data intended for

our port. We must decide on a port number. Lets say FFH.

Now, we can design the control circuit.

I f i h LED (C l Ci i )


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Interfacing the LEDs (Control Circuit)

The Latch will be enabled when:

WR = 0 IO/M = 1

The address on A8 A15 = FFH

Latch Enable

A15

A8

IO/M

WR

I f i h LED (L h & LED )


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Interfacing the LEDs (Latch & LEDs)

I f i h LED ( h )


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Interfacing the LEDs (the program)

When a bit on the AD bus is 1, the corresponding

Q will be zero and the LED will have 5 volts onthe anode and 0 on the cathode. Therefore, it willbe on.

Finally, to write the program:MVI A, Data ;load the data to be displayed

OUT FF ;send the data to output port FF

HLT ;End

I t f i th it h


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Interfacing the switches

The binary value from the switches will have to

be carried by the data bus. However, the databus is a shared bus. So, the switches must beconnected to the data bus using Tri-state buffers.

Similar to the latch, the buffers must be enabledonly on I/O Read operation from this I/O port.

Lets choose I/O port 0FH for the switches. So,the buffers must be enabled when:

RD = 0

IO/M = 1

A8-A15 = 0FH

I t f i th S it h (C t l Ci it)


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IO/M

RD

Buffer Enable

A8

Interfacing the Switches (Control Circuit)

A15

I t f i th S it h (L t h & S it h )


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Interfacing the Switches (Latch & Switches)

I t f i th S it h (th )


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Interfacing the Switches (the program)

Finally, the program:

IN 0FH ;input data from port 0F into AHLT ;END

If we combine both circuits, then we can write thefollowing program:

INPUT: IN 0FH

OUT FFH

JMP INPUT

I t f i M M d I/O d i


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Interfacing a Memory-Mapped I/O device

Instead of using 8-bit address, the full 16-bits of

the address bus must be used. Instead of using IOR and IOW, use MEMR and

MEMW.

8085 arch_interfacing io

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