74138

Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 71 Publication Order Number:

MC74HC138A/D

��

�� High–Performance Silicon–Gate CMOS

The MC74HC138A is identical in pinout to the LS138. The deviceinputs are compatible with standard CMOS outputs; with pullupresistors, they are compatible with LSTTL outputs.

The HC138A decodes a three–bit Address to one–of–eightactive–low outputs. This device features three Chip Select inputs, twoactive–low and one active–high to facilitate the demultiplexing,cascading, and chip–selecting functions. The demultiplexing functionis accomplished by using the Address inputs to select the desireddevice output; one of the Chip Selects is used as a data input while theother Chip Selects are held in their active states.• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC StandardNo. 7A

• Chip Complexity: 100 FETs or 29 Equivalent Gates

LOGIC DIAGRAM

7Y6

Y5

Y4

Y3Y2Y1

Y0

Y7

9

1011

121314

15

3

2

1

CS1

CS2

A0

A1

A2 ACTIVE–LOWOUTPUTS

ADDRESSINPUTS

CS3

CHIP–SELECTINPUTS 5

4

6PIN 16 = VCCPIN 8 = GND

Inputs Outputs

CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X X H X X X H H H H H H H HX H X X X X H H H H H H H HL X X X X X H H H H H H H H

H L L L L L L H H H H H H HH L L L L H H L H H H H H HH L L L H L H H L H H H H HH L L L H H H H H L H H H H

H L L H L L H H H H L H H HH L L H L H H H H H H L H HH L L H H L H H H H H H L HH L L H H H H H H H H H H L

FUNCTION TABLE

H = high level (steady state); L = low level (steady state); X = don’t care

SO–16D SUFFIX

CASE 751B

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TSSOP–16DT SUFFIXCASE 948F

1

16

PDIP–16N SUFFIXCASE 648

1

16

1

16

MARKINGDIAGRAMS

1

16

MC74HC138ANAWLYYWW

1

16

HC138AAWLYWW

A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week

HC138AALYW

1

16

Device Package Shipping

ORDERING INFORMATION

MC74HC138AN PDIP–16 2000 / Box

MC74HC138AD SOIC–16 48 / Rail

MC74HC138ADR2 SOIC–16 2500 / Reel

MC74HC138ADT TSSOP–16 96 / Rail

MC74HC138ADTR2 TSSOP–16 2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A0

CS2

A2

A1

Y7

CS1

CS3

GND

Y3

Y2

Y1

Y0

VCC

Y5

Y4

Y6

MC74HC138A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter ÎÎÎÎÎÎÎÎÎÎ

Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ

– 0.5 to + 7.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ

– 0.5 to VCC + 0.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND) ÎÎÎÎÎÎÎÎÎÎ

– 0.5 to VCC + 0.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin ÎÎÎÎÎÎÎÎÎÎ

± 20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

Iout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin ÎÎÎÎÎÎÎÎÎÎ

± 25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

ICC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins ÎÎÎÎÎÎÎÎÎÎ

± 50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎ

PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

750500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ

Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature ÎÎÎÎÎÎÎÎÎÎ

– 65 to + 150ÎÎÎÎÎÎ

�C


TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

260

ÎÎÎÎÎÎÎÎÎ

�C

*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/�C from 65� to 125�CSOIC Package: – 7 mW/�C from 65� to 125�C TSSOP Package: – 6.1 .W/�C from 65� to 125�C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONSÎÎÎÎÎÎÎÎSymbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParameter

ÎÎÎÎÎÎMinÎÎÎÎMaxÎÎÎÎÎÎUnitÎÎÎÎ

ÎÎÎÎVCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ2.0ÎÎÎÎ6.0ÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎVin, VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ0ÎÎÎÎVCCÎÎÎÎÎÎVÎÎÎÎ

ÎÎÎÎTAÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOperating Temperature, All Package Types

ÎÎÎÎÎÎ– 55ÎÎÎÎ+ 125ÎÎÎÎÎÎ�CÎÎÎÎ


tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V(Figure 2) VCC = 4.5 V

VCC = 6.0 V


000

ÎÎÎÎÎÎÎÎ

1000500400


ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ


ÎÎÎÎÎÎÎÎ


Guaranteed LimitÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter


Test Conditions


VCCV


–55�C to25�C

ÎÎÎÎÎÎÎÎÎ� 85�C


� 125�C

ÎÎÎÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum High–Level InputVoltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V|Iout| � 20 µA


2.03.04.56.0


1.52.13.154.2


1.52.13.154.2


1.52.13.154.2


V


VILÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–Level InputVoltage


Vout = 0.1 V or VCC – 0.1 V|Iout| � 20 µA


2.03.04.56.0


0.50.91.351.8


0.50.91.351.8


0.50.91.351.8


V


VOH


Minimum High–Level OutputVoltage


Vin = VIH or VIL|Iout| � 20 µA


2.04.56.0


1.94.45.9


1.94.45.9


1.94.45.9


V




Vin = VIH or VIL |Iout| � 2.4 mA|Iout| � 4.0 mA|Iout| � 5.2 mA


3.04.56.0


2.483.985.48

ÎÎÎÎÎÎÎÎÎ

2.343.845.34


2.203.705.20

ÎÎÎÎÎÎÎÎÎ

This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high–impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND � (Vin or Vout) � VCC.

Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.

MC74HC138A

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎÎÎ

Unit


Guaranteed LimitÎÎÎÎÎÎÎÎVCC

V


Test Conditions


Parameter

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎ

� 125�CÎÎÎÎÎÎ� 85�C

ÎÎÎÎÎÎÎÎ

–55�C to25�C

ÎÎÎÎÎÎÎÎ

VCCV


Test ConditionsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VOLÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Low–Level OutputVoltage


Vin = VIH or VIL|Iout| � 20 µA


2.04.56.0


0.10.10.1


0.10.10.1


0.10.10.1


V




Vin = VIH or VIL |Iout| � 2.4 mA|Iout| � 4.0 mA|Iout| � 5.2 mA


3.04.56.0


0.260.260.26

ÎÎÎÎÎÎÎÎÎ

0.330.330.33


0.400.400.40

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎIin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input LeakageCurrent


Vin = VCC or GND ÎÎÎÎÎÎÎÎ

6.0 ÎÎÎÎÎÎÎÎ

± 0.1 ÎÎÎÎÎÎ

± 1.0ÎÎÎÎÎÎÎÎ

± 1.0ÎÎÎÎÎÎ

µA


ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Quiescent SupplyCurrent (per Package)


Vin = VCC or GNDIout = 0 µA


6.0ÎÎÎÎÎÎÎÎÎÎÎÎ

4ÎÎÎÎÎÎÎÎÎ

40ÎÎÎÎÎÎÎÎÎÎÎÎ

160ÎÎÎÎÎÎÎÎÎ

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book(DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ


Guaranteed Limit ÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter


VCCV


–55�C to25�C

ÎÎÎÎÎÎÎÎÎ� 85�C


� 125�C

ÎÎÎÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

tPLH,tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input A to Output Y(Figures 1 and 4)


2.03.04.56.0


135902723


1701253429


2051654135


ns


tPLH,tPHL


Maximum Propagation Delay, CS1 to Output Y(Figures 2 and 4)


2.03.04.56.0


110852219


1401002824


1651253328


ns


tPLH,tPHL


Maximum Propagation Delay, CS2 or CS3 to Output Y(Figures 3 and 4)


2.03.04.56.0


120902420


1501203026


1801503631


ns


tTLH,tTHL


Maximum Output Transition Time, Any Output(Figures 2 and 4)


2.03.04.56.0


75301513


95401916


110552219


ns

ÎÎÎÎÎÎÎÎÎÎ

Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance ÎÎÎÎÎÎÎÎ

— ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

10 ÎÎÎÎÎÎÎÎ

10 ÎÎÎÎÎÎ

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25 °C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 55 pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High–Speed CMOS Data Book (DL129/D).

MC74HC138A

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Figure 1.

50%

tPHLtPLH

VCC

GND

Figure 2.

VALID VALID

OUTPUT Y 50%

tftrVCC

GNDtPLH

tTLH

90%50%

10%OUTPUT Y

INPUT CS1

tPHL

90%50%

10%

tTHL

INPUT A

SWITCHING WAVEFORMS

tTHL tTLH

VCC

GND

tr

tPHL tPLH

OUTPUT Y

INPUTCS2, CS3

90%50%

10%

90%50%

10%

Figure 3.

tf

*Includes all probe and jig capacitance

Figure 4. Test Circuit

CL*

TEST POINT

DEVICEUNDERTEST

OUTPUT

PIN DESCRIPTIONS

ADDRESS INPUTSA0, A1, A2 (Pins 1, 2, 3)

Address inputs. These inputs, when the chip is selected,determine which of the eight outputs is active–low.

CONTROL INPUTSCS1, CS2, CS3 (Pins 6, 4, 5)

Chip select inputs. For CS1 at a high level and CS2, CS3at a low level, the chip is selected and the outputs follow the

Address inputs. For any other combination of CS1, CS2, andCS3, the outputs are at a logic high.

OUTPUTSY0 – Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)

Active–low Decoded outputs. These outputs assume alow level when addressed and the chip is selected. Theseoutputs remain high when not addressed or the chip is notselected.

MC74HC138A

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A0

A1

A2

CS3

CS2

CS1

1

2

3

4

5

6

15

14

13

12

11

10

9

7

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y0

EXPANDED LOGIC DIAGRAM

MC74HC138A

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PACKAGE DIMENSIONS

PDIP–16N SUFFIX

CASE 648–08ISSUE R

MIN MINMAX MAXINCHES MILLIMETERS

DIMABCDFGHJKLMS

18.806.353.690.391.02

0.212.807.50

0°0.51

19.556.854.440.531.77

0.383.307.7410°1.01

0.7400.2500.1450.0150.040

0.0080.1100.295

0°0.020

0.7700.2700.1750.0210.070

0.0150.1300.305

10°0.040

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

2.54 BSC1.27 BSC

0.100 BSC0.050 BSC

–A–

B1 8

916

F

HG

D 16 PL

S

C

–T–

SEATINGPLANE

K JM

L

T A0.25 (0.010) M M

0.25 (0.010) T B AM S S

MIN MINMAX MAXMILLIMETERS INCHES

DIMABCDFGJKMPR

9.803.801.350.350.40

0.190.10

0°5.800.25

10.004.001.750.491.25

0.250.25

7° 6.200.50

0.3860.1500.0540.0140.016

0.0080.004

0° 0.2290.010

0.3930.1570.0680.0190.049

0.0090.009

7° 0.2440.019

1.27 BSC 0.050 BSC


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

1 8

916

–A–

–B–

D 16 PL

K

C

G

–T–SEATING

PLANE

R X 45°

M J

F

P 8 PL

0.25 (0.010) BM M

SOIC–16D SUFFIX

CASE 751B–05ISSUE J

MC74HC138A

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PACKAGE DIMENSIONS

TSSOP–16DT SUFFIX

CASE 948F–01ISSUE O

ÇÇÇÇÇÇ

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C ––– 1.20 ––– 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.18 0.28 0.007 0.011J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8


Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.PROTRUSIONS OR GATE BURRS. MOLD FLASH ORGATE BURRS SHALL NOT EXCEED 0.15 (0.006) PERSIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED ATDATUM PLANE –W–.

� � � �

SECTION N–N

SEATINGPLANE

IDENT.PIN 1

1 8

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

HG

ÉÉÉÉÉÉ

DETAIL E

F

M

L

2X L/2

–U–

SU0.15 (0.006) T

SU0.15 (0.006) T

SUM0.10 (0.004) V ST

0.10 (0.004)–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

MC74HC138A

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changeswithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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Email : ONlit–[email protected]

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Toll Free from Hong Kong & Singapore:001–800–4422–3781

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For additional information, please contact your localSales Representative.

MC74HC138A/D

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74138

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