7-segment displays vhdl tutorial r. e. haskell and d. m. hanna t4: xilinx logiblox
Post on 22-Dec-2015
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TRANSCRIPT
library IEEE;use IEEE.std_logic_1164.all; entity seg7dec is port (q: in STD_LOGIC_VECTOR(3 downto 0);
AtoG: out STD_LOGIC_VECTOR(6 downto 0));end seg7dec;
7-Segment Decoder
architecture seg7dec_arch of seg7dec isbegin process(q) begin case q is when "0000" => AtoG <= "0000001"; when "0001" => AtoG <= "1001111"; when "0010" => AtoG <= "0010010"; when "0011" => AtoG <= "0000110"; when "0100" => AtoG <= "1001100"; when "0101" => AtoG <= "0100100"; when "0110" => AtoG <= "0100000"; when "0111" => AtoG <= "0001101"; when "1000" => AtoG <= "0000000"; when "1001" => AtoG <= "0000100"; when "1010" => AtoG <= "0001000"; when "1011" => AtoG <= "1100000"; when "1100" => AtoG <= "0110001"; when "1101" => AtoG <= "1000010"; when "1110" => AtoG <= "0110000"; when others => AtoG <= "0111000"; end case; end process;end seg7dec_arch;
mux4
ctr2bit
Acode
seg7dec
dig7segdig1(3:0)
dig2(3:0)
dig3(3:0)
dig4(3:0)
clk
anode(3:0)
AtoG(6:0)
A(4:1)
Multiplex displays
Asel(1:0)
Aen(3:0)
y1(3:0)
dig7seg
entity dig7seg is
port (
anode: in STD_LOGIC_VECTOR (3 downto 0);
dig1: in STD_LOGIC_VECTOR (3 downto 0);
dig2: in STD_LOGIC_VECTOR (3 downto 0);
dig3: in STD_LOGIC_VECTOR (3 downto 0);
dig4: in STD_LOGIC_VECTOR (3 downto 0);
clk: in STD_LOGIC;
AtoG: out STD_LOGIC_VECTOR (6 downto 0);
A: out STD_LOGIC_VECTOR (4 downto 1)
);
end dig7seg;
dig7seg
architecture dig7seg_arch of dig7seg issignal y1: STD_LOGIC_VECTOR (3 downto 0);signal sel2: STD_LOGIC_VECTOR (1 downto 0);begin u0: ctr2bit port map
(CLOCK => clk, Q_OUT => sel2); u1: mux4g port map (a => dig1, b => dig2, c => dig3, d => dig4, sel => sel2, y => y1); u2: seg7dec port map (q => y1, AtoG => AtoG); u3: Acode port map (Aen => anode, Asel => sel2, A => A); end dig7seg_arch;
ctr2bit
-- A 2-bit up-counterlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; entity ctr2bit is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (1 downto 0) );end ctr2bit;
ctr2bit (cont.)architecture ctr2bit_arch of ctr2bit isbeginprocess (clk, clr)variable COUNT: STD_LOGIC_VECTOR (1 downto 0);begin if clr = '1' then q <= "00"; elsif clk'event and clk='1' then COUNT := COUNT + 1; q <= COUNT; end if;end process;end ctr2bit_arch;
library IEEE;use IEEE.std_logic_1164.all; entity Acode is port ( Aen: in STD_LOGIC_VECTOR (3 downto 0); Asel: in STD_LOGIC_VECTOR (1 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) );end Acode;
Acode
architecture Acode_arch of Acode isbegin process(Aen, Asel) begin A <= "0000"; case Asel is when "00" => if Aen(0) = '1' then A <= "0001"; end if; when "01" => if Aen(1) = '1' then A <= "0010"; end if; when "10" => if Aen(2) = '1' then A <= "0100"; end if; when others => if Aen(3) = '1' then A <= "1000"; end if; end case; end process; end Acode_arch;
dig7seg
debounce
clrout
clkout step
A(4:1) AtoG(6:0)
step_display
dig4(3:0)
clr
anode"1111"
dig1dig4 dig3 dig2
osc_4kclk4
dig3(3:0) dig2(3:0) dig1(3:0)
step_display
step_displaylibrary IEEE;use IEEE.std_logic_1164.all;
entity step_display is port ( dig1, dig2: in STD_LOGIC_VECTOR (3 downto 0);
dig3, dig4: in STD_LOGIC_VECTOR (3 downto 0); step: in STD_LOGIC; clr: in STD_LOGIC; clkout: out STD_LOGIC; clrout: out STD_LOGIC; AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (4 downto 1) );end step_display;
architecture step_display_arch of step_display issignal anode: STD_LOGIC_VECTOR (3 downto 0);signal clk4: STD_LOGIC;begin anode <= "1111"; clrout <= clr; u1: dig7seg port map (anode => anode, dig4 => dig4, dig3 => dig3, dig2 => dig2, dig1 => dig1, clk => clk4, AtoG => AtoG, A => A); u2: osc_4k port map (clk => clk4); u3: debounce port map (inp => step, clk => clk4, clr => clr,
outp => clkout);end step_display_arch;
T4 Lab Exercise
mux2
Tregclkclr
Nregclkclr
ALU
T
N
tin
SW(1:8)
LD(1:8)
SW(4:5)
SW(1)
SW(2)
SW(3)
y
step_display
A(3:0) AtoG(6:0)
clk
clr
TN
BTN(1)
BTN(4)
clr
step
T4mainlibrary IEEE;use IEEE.std_logic_1164.all;
entity T4main is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN: in STD_LOGIC_VECTOR (1 to 4); LD: out STD_LOGIC_VECTOR (1 to 8); AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) );end T4main;
architecture T4main_arch of T4main is signal tin, T, N, y: std_logic_vector(7 downto 0);signal clr, clk: std_logic;begin U0: mux2 port map (a =>y, b => SW, sel => SW(1), y => tin); Treg: reg port map (d => tin, load => SW(2), clr => clr, clk =>clk, q => T); Nreg: reg port map (d => T, load => SW(3), clr => clr, clk =>clk, q => N); U1: alu port map (a => T, b => N, sel => SW(4 to 5), y => y); U2: step_display port map (dig1 => T(3 downto 0), dig2 => T(7 downto 4), dig3 => N(3 downto 0), dig4 => N(7 downto 4), step => BTN(4), clr => BTN(1), clkout => clk, clrout => clr, A => A, AtoG => AtoG); LD <= SW;end T4main_arch;