Chapter 6Co-synthesis Techniques

CosynthesisMethodical approach to system implementations using automated synthesis-oriented techniquesMethodology and performance constraints determine partitioning into hardware and software implementationsThe result is optimal system that benefits from analysis of hardware/software design trade-off analysis

Cosynthesis Approach to System ImplementationMemoryBehavioral Specification and Performance criteriaSystemInputPerformanceCostMixedImplementationPure SWPure HWConstraints[Gupta93]SystemOutput IEEE 1993

Co-synthesisImplementation of hardware and software components after partitioningConstraints and optimization criteria similar to those for partitioningArea and size traded-off against performanceCost considerations

Synthesis Flow HW synthesis of dedicated unitsBased on research or commercial standard synthesis toolsSW synthesis of dedicated units (processors)Based on specialized compiling techniquesInterface synthesisDefinition of HW/SW interface and synchronizationDrivers of peripheral devices

Co-Synthesis - The POLIS FlowESTEREL for functional specification language

Hardware DesignMethodologyHardware Design Process:Waterfall ModelHardwareRequirementsPreliminaryHardware DesignDetailedHardwareDesignFabricationTesting

Hardware DesignMethodology (Cont.)Use of HDLs for modeling and simulationUse of lower-level synthesis tools to derive register transfer and lower-level designsUse of high-level hardware synthesis toolsBehavioral descriptionsSystem design constraintsIntroduction of synthesis for testability at all levels

Hardware SynthesisDefinitionThe automatic design and implementation of hardware from a specification written in a hardware description languageGoals/benefitsTo quickly create and modify designsTo support a methodology that allows for multiple design alternative considerationTo remove from the designer the handling of the tedious details of VLSI designTo support the development of correct designs

Hardware Synthesis CategoriesAlgorithm synthesisSynthesis from design requirements to control-flow behavior or abstract behaviorLargely a manual processRegister-transfer synthesisAlso referred to as high-level or behavioral synthesisSynthesis from abstract behavior, control-flow behavior, or register-transfer behavior (on one hand) to register-transfer structure (on the other)Logic synthesisSynthesis from register-transfer structures or Boolean equations to gate-level logic (or physical implementations using a predefined cell or IC library)

Hardware Synthesis Process OverviewBehavioralSimulationOptional RTLSimulationBehavioralSynthesisSynthesis &Test SynthesisGate-levelSimulationGate-levelAnalysisPlace and RouteSpecificationImplementationVerificationSilicon VendorSiliconBehavioralFunctionalRTLFunctionalGateLayout

HW SynthesisSpecification AnalysisConcurrent Design System Integration

Stop

ICOS

Output Best Architecture

Error: Synthesis Impossible

No

Yes

Synthesis Rollback

(1) Specification Analysis Phase (2) Concurrent Design Phase (3) System Integration Phase

(3)

(2)

(1)

Yes

Simulation and Performance Evaluation

rollback possible?

Specification Analysis

Specification Error?

Initialization:

AddDH(root), AppendDQ(root)

PopDQ

Component

Design

...

Component

Design

Component

Design

Component

Design

Architecture specs

Performance specs

Synthesis specs

Specification Input

Class Hierarchy

Yes

DQempty?

No

No

No

Yes

design

complete?

Software DesignMethodologySoftware Design Process:Waterfall ModelSoftwareRequirementsSoftware DesignCodingTestingMaintenance

Software DesignMethodology (Cont.)Software requirements includes bothAnalysisSpecificationDesign: 2 levels:System level - module specs.Detailed level - process design language (PDL) usedCoding - in high-level languageC/C++Maintenance - several levelsUnit testingIntegration testingSystem testingRegression testingAcceptance testing

Software SynthesisDefinition: the automatic development of correct and efficient software from specifications and reusable componentsGoals/benefitsTo Increase software productivityTo lower development costsTo Increase confidence that software implementation satisfies specificationTo support the development of correct programs

Why UseSoftware Synthesis?Software development is becoming the major cost driver in fielding a systemTo significantly improve both the design cycle time and life-cycle cost of embedded systems, a new software design methodology, including automated code generation, is necessarySynthesis supports a correct-by-construction philosophyTechniques support software reuse

Why Software Synthesis?More software high complexity need for automatic design (synthesis)Eliminate human and logical errorsRelatively immature synthesis techniques for softwareCode optimizationssizeefficiencyAutomatic code generation

Software Synthesis Flow Diagram for Embedded System with Time Petri-Net

System Software Specification

Modeling System Software with Time Petri Net

Task Scheduling

Code Generation

Code Execution on an Emulation Board

Test Report

Feedback and Modification

Automatically Generate CODEReal-Time Embedded System Model? Set of concurrent tasks with memory and timing constraints!How to execute in an embedded system (e.g. 1 CPU, 100 KB Mem)? Task Scheduling!How to generate code? Map schedules to software code!Code optimizations? Minimize size, maximize efficiency!

Software SynthesisCategoriesLanguage compilersADA and C compilersYACC - yet another compiler compilerVisual BasicDomain-specific synthesisApplication generators from software libraries

Software Synthesis ExamplesMentor Graphics Concurrent Design Environment SystemUses object-oriented programming (written in C++)Allows communication between hardware and software synthesis toolsIndex Technologies Excelerator and Cadres Teamwork ToolsetsProvide an interface with COBOL and PL/1 code generatorsKnowledgeWares IEW GammaUsed in MIS applicationsCan generate COBOL source code for system designersMCCIs Graph Translation Tool (GrTT)Used by Lockheed Martin ATLCan generate ADA from Processing Graph Method (PGM) graphs

Software Synthesis Tool: The Design of Synthesis Tool for Interrupted-based Embedded Software

Motivation System Complexity Time to Market Hardware-Software Co-design Methodology Embedded Software Synthesis ToolsText-Edit User-Interface System ModelInterrupt BehaviorIntroduction

Designing of a Synthesis Tool System ModelInterrupt Time Petri Net, ITPNSchedulingInterrupt-Based Quasi-Dynamic Scheduling, IQDSCode GenerationMicrocontroller(89c51) C Program CodeReal-Time Embedded Software Synthesis ToolGraphical User-InterfaceIntroduction

System FrameworkIntroduction

Definition for ITPNITPN Definition

System ModelA ITPN is a 5-tuple.P is a non-empty finite set of places.T is a non-empty finite set of transitions.I(ti) is a input function.O(tj) is a output function.

Definition for ITPN:(t)=(, , ):Earliest Firing Time, EFT.:Latest Firing Time, LFT.:The type of interrupt for 8051.

A ITPN ExampleSystem Model

Interrupt-Based Quasi-Dynamic Scheduling (IQDS)Scheduling & Code GenerationStep2: Decompose the ITPN into two parts : static scheduling and choice block (CB) Step3: Search the routing path (choice clock set, CBS) for each CBStep4: Derive all routing path from Initial PlaceStep5: Check the real-time constraints for all routing path Step1: Find the Initial Place, End Place, and Choice Block

An example of IQDSScheduling & Code Generationp4p1p2p3p5p6p7p10p11p12t1(1, 2, 1)t2(1, 1, 1)t4(1, 2, 1)t3(1, 3, 1)t5(1, 2, 1)t6(1, 4, 1)t7(1, 3, 1)t8(1, 4, 1)

An example of IQDS (cont.)Scheduling & Code GenerationRoute ExtendedPresent Route

t1t2CBS1

t3t4t5Result

t1t2 t3t1t2 t4t1t2 t5Present Route

t1t2 t3t1t2 t4t1t2 t5CBS2t8t9Static Route

t6t7Result

t1t2 t3 t6t1t2 t4 t7t1t2 t5 t8t1t2 t5 t9

An example of IQDS (cont.)Scheduling & Code GenerationResult

t1t2 t3 t6t1t2 t4 t7t1t2 t5 t8t1t2 t5 t9

Real_Time_Check

SchedulableNot Schedulable

Code GenerationStep2: Print transitions content from Initial PlaceStep3: Print if then elseStep4: Combine main_function, sub_function, and ISRStep1: Differentiate ISR, main_function, and sub_function

SpecificationEnvironment:CPU : Pentium4 1.4GHzMemory : 256MB DDROS : Windows XPProgramming Language : Visual Basic 6.0Input : Graphical ITPNOutput : Keil CSoftware Synthesis Tool

Graphical User InterfaceSoftware Synthesis ToolITPN Edit, Scheduling and Code Generation

Real-time Stepping Motor Control (RSMC)System Function:Control Stepping Motor speed and direction.INT0, Timer1: Motors speed control.Timer0 : Motors direction control.Examples

Block Diagram of RSMCExample

ITPN Model for RSMCMain FunctionExamplet1 : Capture Keypad register.t2 , t3 : Turn on Stepping Motor.t4 : Shut off Stepping Motor.t5 : Set positive direct.t6 : Set opposite direction.t7 : Stop LED on.

ITPN Model for RSMC (cont.)Timer0 ISRExamplet8 : Reset t9 : Scan Keypad

ITPN Model for RSMC (cont.)Timer1 ISRExamplet10 : Resett11 : Increase countert12 : Reset countt13 : Undot14 : Control stepping motor

ITPN Model for RSMC(cont.)INT0 ISRExamplet15 : Get the key (Speed up or down)t16 : Check Max speedt17 : Check Min speedt18 : Undot19 : Speed upt20 : Speed downt21 : Undo

Scheduling and Code GenerationExample

Real Time ConstraintsExampleISRs time : - > 31 (8+8+15=31)Cycle Time > 105

InterruptISRs timeINT08Timer08Timer115

EmulationPlatform ArchitectureExample

SummaryExtended system model called Interrupt Time Petri Net, ITPNAn Interrupt-Based Quasi-Dynamic Scheduling, IQDS is proposedGenerate a microcontroller (8051) C program code Graphical user interface make the tool more user-friendlyConclusion

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