670 ieee sensors journal, vol. 4, no. 5, october …peter/534a/cmos_heater.pdf · soi cmos...

670 IEEE SENSORS JOURNAL, VOL. 4, NO. 5, OCTOBER 2004

SOI CMOS Compatible Low-Power MicroheaterOptimization for the Fabrication

of Smart Gas SensorsJean Laconte, Cédric Dupont, Denis Flandre, Member, IEEE, and Jean-Pierre Raskin, Member, IEEE

Abstract—In this paper, an original design of a polysiliconloop-shaped microheater on a 1- m thin-stacked dielectric mem-brane is presented. This design ensures high thermal uniformityand insulation and very low power consumption (20 mW forheating at 400 C). Moreover, the use of completely CMOScompatible tetramethyl ammonium hydroxide-based bulk-micro-machining techniques allows an easy, smart gas sensor integrationin SOI-CMOS technology.

Index Terms—Bulk micromachining, CMOS- compatibility, gassensor, microheater, silicon-on-insulator.

I. INTRODUCTION

I N RECENT years, thin-film microheaters are emerging asa topic of considerable interest for an extremely wide range

of applications [1], such as e.g., gas sensors. The major chal-lenges involved in the design of such structures are the needsfor high thermal uniformity, low-power consumption, low cost,and compatibility with standard IC processes to enable co-inte-grated microsystems.

In this paper, an original design that meets these four issuesis presented based on a polysilicon loop-shaped microheaterand the bulk micromachining of a 1- m thin-stacked dielectricmembrane (SiO -Si N -SiO ), using fully CMOS IC-compat-ible tetramethyl ammonium hydroxide (TMAH)-based etchingtechniques (Fig. 1). First, we describe the aimed application ofour microheater design, i.e., the full implementation of a smartgas sensor in silicon-on-insulator (SOI)-CMOS technology byintegrating both the sensing device and the control electronicson the same chip. We discuss why it is easier and more suitableto integrate this microsystem using SOI-CMOS technology.

The thin-film membrane is one of the most important partsof the total integrated structure to be studied, since it is the me-chanical support for the microheater (and the sensing film, in thecase of gas sensors) and since it is responsible for thermal iso-lation and uniformity and, therefore, low-power consumption.The shape of the heater also has an important impact on the con-sumption and the thermal uniformity. After the description of

Manuscript received October 30, 2002; revised December 3, 2002. This workwas supported in part by D.G.T.R.E. Projects—Ministery of Region Wallone,Belgium. The associate editor coordinating the review of this paper and ap-proving it for publication was Prof. Thaddeus Roppel.

The authors are with the Research Center in Micro and NanoscopicElectronics Devices and Materials (CeRMIN), Microelectronics Laboratory,Microwave Laboratory, Université catholique de Louvain, B-1348 Louvain-La-Neuve, Belgium (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Digital Object Identifier 10.1109/JSEN.2004.833516

base materials, a detailed analysis of the effect on microheaterperformances of parameters, such as resistor shape, membranesize, and membrane thickness, is presented based on ANSYSnumerical electrothermal simulations [2].

The microheater fabrication is then described on classical sil-icon substrate and compared with its fabrication using SOI tech-nology to explain the co-integration.

Finally, experimentals results of our microheater characteri-zation are discussed.

II. MOTIVATION

Our microheater is developed and optimized to finally builda fully integrated smart gas sensor in SOI-CMOS technology.The principle of this kind of sensor lies in a sensitive layer (typ-ically a metal-oxide layer such as SnO or WO ) for which theresistivity is shifted at a working temperature between 250 Cand 350 C in presence of gases as NO , SO or CO (Fig. 2).

For such a sensor, a microheater is necessary to heat the sensi-tive layer and interdigitated electrodes to measure the resistivityvariation of the sensing film. Electronics circuitry, such as anoperational amplifier, must also be added close to the sensor tomonitor the resistivity shift. SOI technology is uniquely suitedfor micropower as well as high temperature and radiation cir-cuit performances [3]. SOI substrates also offer a lot of advan-tages toward the joint fabrication of the membrane with the closeelectronics. The typical 400-nm buried thermal oxide of the SOIwafer can constitute the first layer of the membrane and also thenatural etch-stop layer for the backside silicon etching, whilethe upper monocristalline silicon film can integrate the elec-tronics close to, but totally isolated from the microheater. It is,therefore, easier and more suitable to integrate this microsystemusing SOI-CMOS technology combining excellent membraneuniformity and control over batches of wafers with high circuitperformance.

To complete a gas sensor on top of integrated circuits and mi-croheater, a thin layer of SiO is to be deposited and patterned inpost-processing to act as electrical insulator between the heaterand the gas sensitive layer. Sputtered gold/chromium interdigi-tated sensing electrodes patterned with liftoff are then depositedon the oxide film. The backside etching is performed using theburied oxide as etch-stop layer with a own TMAH-based solu-tion.

The use of TMAH is dictated by its excellent clean room andCMOS process compatibility (no metallic ions, unlike KOH),low toxicity which eases the manipulation (compared to EDP),

1530-437X/04$20.00 © 2004 IEEE

LACONTE et al.: SOI CMOS COMPATIBLE LOW-POWER MICROHEATER OPTIMIZATION 671

Fig. 1. Packaged polysilicon microheater on 440� 440 �m membrane. On-chip aluminum connections (bright lines) and gold wires to the package can be seen.

excellent selectivity to silicon oxide, silicon nitride and gold.In order to keep aluminum as the first metallic layer undergold electrodes, effective passivation of aluminum has to beachieved, since pure TMAH attacks aluminum interconnec-tions. Excellent results were obtained using optimized chemicalpassivation through additives in the etching solution [4], [5], aswill be described in Section V.

Finally, thick SnO and WO sensing films could bedeposited on the released membranes thanks to their highmechanical resistance, since a complete degradation of thesemetal oxide layers was observed after 3 h of etching in ourTMAH-based solution. Drop coated and printed sensitivelayers could then be used. They are furthermore preferred tosputtered layers because they show better sensitivity to gasesthanks to their higher thickness (around 10 m for printing anduncontrollable thickness for drop coating [6]).

III. MATERIALS SELECTION

A. Membrane

The materials chosen for the membrane of the microheatershould combine low thermal conductivity (i.e., small thickness)with high mechanical strength (i.e., large thickness). Whileinsuring compatibility with a micronic fully depleted (FD)SOI-CMOS process of interest for micropower or high-temper-ature applications [3], the 400-nm-thick buried thermal oxideof the SOI substrate can advantageously constitute the first partof the membrane. A second part of the membrane stack will beconstituted by the densified PECVD oxide layer related to theinterconnect dielectric between the polysilicon and aluminum

layers of the CMOS process. For mechanical robustness, a nitridelayer must be added and the thickness must be chosen to carefullycompensate the high residual stresses of the deposited films.The thermal oxide usually shows a compressive residual stressof about 250 MPa and nitride, a tensile residual stress of about1.2 GPa. The total stress of the sandwich layer is calculated by(1) where and are the thicknesses of oxide and nitride,respectively

(1)

The equation shows that the ratio between the two thicknesseswould be 4 to have a strain-free membrane. But, in practice, thebest choice is to take a ratio of about 2 to have a slightly tensilemembrane and to take into account its high critical lengthening7.8 10 [7]. Inpractice,basedon theoptimizationofSection

IV, we selected thicknesses of 300 nm for the LPCVD nitridelayer and 290 nm for the PECVD oxide layer for a total thicknessaround1 m.Fig.1showsthatwiththeseparameters,weobtaineda strain-free membrane (i.e., with no visible ripples). Membraneswith areas larger than 1 mm were successfully produced.

B. Heater

The design chosen for the heater is a loop-shaped phosphorousdoped polysilicon resistor (Fig.1) as optimized below by finiteel-ementmethod(ANSYSsoftware)toachievelowpowerconsump-tion and high thermal uniformity. A 340-nm-thick phosphorous-doped polysilicon is used for the heater because it is the commonmaterial and thickness for the gate in CMOS and SOI-CMOSfab-rication.ThedopinglevelisimposedbytheICprocesstohaveare-


Fig. 2. Fully integrated smart gas sensor concept in SOI-CMOS technology.

sistivity of around 25 /square (the material resistivity expressedin /square is obtained by dividing the material resistivity in .mdividedby its thickness).Asdemonstratedbelow, it is,by theway,an optimum for such microheaters.

IV. SIMULATIONS

ANSYS simulations were performed to optimize heater sizeand shape and total membrane area to ensure a uniform tem-perature distribution over the whole active area as well as toachieve low power consumption. Thanks to the symmetrical de-sign, simulations were performed on a quarter of membraneassuming the following boundary conditions: on the symmet-rical edge, the thermal conditions are adiabatic; the temperatureat the periphery of the membrane is constant and equal to theambient temperature (30 C); on the upper and lower surfacesof the membrane, the heat is dissipated through convective ex-change with the gaseous phase. The exchange coefficients weretaken as 250 and 125 W/m K for the upper and the lower areasurfaces, respectively [8]. Radiation losses were considered asnegligible. The heat generation is set by a power generator inthe resistor which is the ratio between the power consumptionand the volume of heater.

The conductivity values of the three stacked dielectric mem-brane were calculated at 7.6 W/m K using the parameters inTable I but the comparison of the simulated results and the lit-erature [8] to our measurements shows a better agreement for athermal conductivity of 5 W/m K due to the surface and inter-face defects. Vertical temperature gradient and conduction arealso negligible and the design can be simplified in a two-dimen-sional model.

A. Resistor Shape and Membrane Size

The conventional meander design found in most recent devicescovers the whole active (heated) area and, thus, creates acentral hot spot and a temperature gradient from the center to

TABLE ITHERMAL PARAMETERS OF MEMBRANE MATERIALS [17]

the border [7]–[12]. To compensate this lack of uniformity, theliterature [10], [13]–[16] often introduces either a silicon heatspreader under the active area, or a thermal conductive layer(e.g., aluminum) over the structure, but these solutions leadto higher thermal inertia and consumption. In our proposedgas sensor application, the membrane is only covered withhigh thermal conductivity gas sensitive layer (metallic–oxidelayer like SnO or WO ) to increase the conductivity and alsothe uniformity inside the heater perimeter without increasingthe power consumption (Fig. 3). In this case, a size of about200 200 m has been chosen as active area. From theliterature [4], [9], it was observed that for a specific thicknessof 1 m of the dielectric membrane, a difference of 400 Kappears over a distance of 200 m. Considering only thermalconductivity implies the linearity of the profile of temperaturein the membrane, so that in vacuum, the temperature profilewould be constant between two resistors heated at 400 C andseparated by 200 m. We, therefore, implement a loop-shaperesistor to provide good thermal uniformity in the enclosed area;in the same way, a minimum separation of 200 m betweenthe sensitive area and the edge of the membrane is required forachieving full thermal insulation on the device and maintainingthe silicon at ambient temperature (e.g., 30 C). Therefore,a minimum dimension of the membrane of approximately600 600 m is needed. There is thus a tradeoff between


Fig. 3. Thermal uniformity (in degrees Celsius) of a quarter (320� 320 �m ) of membrane (a) without and (b) with SnO layer on the top of the membrane.The straight lines locate the loop-shaped polysilicon resistor (power injected = 25 mW = 0.18 � 10 W/m ).

Fig. 4. Influence of the membrane thickness on the microheater power consumption versus membrane temperature (4 and � are simulations results)and comparison between simulated (4) and measured results (-) in case of a membrane thickness of 1 �m in first resistor configuration (membrane size:640� 640 �m ).

high thermal insulation and robustness of the membrane. Foroperation at temperatures up to 450 C, we have chosen a typicalmembrane size of 640 640 m for an active heated areaof 240 240 m . But, two other membrane sizes 440 440

m and 840 840 m were also tested.

B. Membrane Thickness

The effect of the membrane thickness on the power con-sumption and thermal uniformity has also been demonstratedby simulation (Fig. 4). If the membrane thickness is increased


by a factor 2, the thermal uniformity into the membrane isimproved because of the better thermal conduction achieved,but the power to achieve 400 C is increased by 30%.

On the other hand, a membrane thinner than 1 m leads to adecrease in power, thermal uniformity, and also in mechanicalresistance of the membrane. This confirms that a membrane of1 m of thickness offers a good tradeoff between uniformity,power consumption, and mechanical resistance thanks to the di-electric sandwich to compensate the residual stress.

V. DEVICE FABRICATION

A. On Bulk Silicon Substrate

To demonstrate the microheater prototype, we first emulatedour SOI process on bulk silicon substrate. The starting materialis a silicon p-type 200- m double-sided polished wafer(Fig. 5). The two first layers of the membrane are 400-nmgrown SiO to simulate the buried oxide of a SOI wafer and300-nm LPCVD Si N (SiH Cl /NH ratio equal to 3). 340nm of polysilicon are deposited, doped with phosphorousimpurities for obtaining a sheet resistance of 25 /square andpatterned to give the heater shape. After 290-nm intercon-nection PECVD–oxide deposition, which constitutes the thirdlayer of the membrane, via holes are opened, and a layer ofaluminum (900 nm) is deposited by sputtering and patternedto create bonding pads and contact polysilicon. The backsidewindow is then defined using the double-side mask alignmentand the three-layers mask (polysilicon, nitride, and thermaloxide) already previously deposited on the back wafer side, forsilicon protection in TMAH, are patterned by plasma RIE. Fi-nally, the membrane is created by a single post-processing step,consisting of a backside bulk micromachining. Anisotropicetch is performed with TMAH and stopped by the dielectricmembrane (Fig. 6).

A TMAH 5% solution was used at a working temperatureof 90 C. For aluminum passivation, the etching solution wassaturated with 16 g/l of Si powder. Dissolved silicon in solu-tion forms aluminosilicates which are less soluble than the alu-minum oxide that would otherwise form at the metal surface. In-troduction of silicates also decreases the pH of the solution and,therefore, lowers the etch rate and provides aluminum passiva-tion. TMAH solution with low pH produces very rough etchedsilicon surfaces due to the formation of bubbles on the etchedsurface which temporarily mask the silicon surface and there-fore form hillocks. The hillocks significantly reduce the etch ratebecause they expose silicon planes and are also aesthetics.Therefore, to reduce surface roughness, ammonium persulfate[APS, (NH ) S O ] is added as oxidizer, in powder shape, intosilicon doped TMAH solution to reduce oxygen production. Therequired amount is only 5 g/L of solution, but it is rapidly con-sumed (after about 45 min). Therefore, this amount is addedevery 45 min when the precipitate is completely dissolved.

Still, it is important to notice that silicic acid [Si(OH) ] canbe added to TMAH as an alternative source of silicates. It isa low-density powder and the volume necessary is quite large.Therefore, it is not easy to manipulate and makes the solutionopaque. The silicon powder has a much higher surface area anddissolves very rapidly, but foaming and excessive bubbling of

Fig. 5. Schematic process flow (a) 200-�m Si wafer, (b) thermal oxidation,(c) PECVD nitride deposition, (d) polysilicon deposition and patterning, (e)PECVD oxide deposition, (f) aluminum deposition and patterning, (g) backsidewindow definition, and (h) TMAH etching.

the solution occur during the dissolution if it is not done at muchlower temperature (about 50 C). After dissolution, the solutionis quite clear with some not harmful precipitates. Reasonableetching rates (1.2 m/min) have been obtained in TMAH dopedwith silicon in combination with persulfate. No deterioration ofthe aluminum interconnections has been observed (Fig. 7) afteran etching time of approximately 3 h which is needed to ensurea complete release of the dielectric membrane using 200- msilicon thick wafers. Our TMAH-based solution, therefore, con-stitutes an excellent post-processing etchant which has reason-able etch rate, is selective to aluminum, silicon dioxide, andsilicon nitride, and is safe and easy to use. Protection of alu-minum by dielectric passivation layer (like APCVD SiO ) wasalso tested and found to be hardly reliable because TMAH easilysweeps through layer defects, attacks the aluminum below, fis-sures the passivation layer, which unsticks with interconnec-tion layer (due to the good adherence between interconnectionPECVD SiO and APCVD SiO and the worst adhesion of thePECVD SiO with LPCVD nitride) and also attacks polysiliconbelow the interconnection layer.

Excellent lateral dimension control was achieved through thecareful design and alignment of the backside mask. The bottommask must be correctly aligned with the front mask, but alsowith the crystallographic direction to avoid an increaseof the membrane size. On the other hand, the thickness of the


Fig. 6. Cavity profile under the membrane and detail of the three-stacked dielectric layers of the membrane.

Fig. 7. Detail of two aluminum lines crossing a polysilicon line. The SEM photo has been taken after 3 h etching in a TMAH-based solution (+APS and Sipowder). It shows the excellent chemical passivation of aluminum.

wafer, the slope of the anisotropic etching (54.7 ), and the lat-eral dimensions of the backside window are fixed and, therefore,give a precise size for the membrane; in reality, the anisotropyratio is not equal to zero and there is some etching in thedirection which has been measured to be close to 5 m, afteretching of 3 h in a TMAH-based solution. The design of thebackside mask was carried out taking this experimental correc-tion factor into account, to achieve good dimension control.

Thanks to the excellent mechanical robustness of the mem-branes, no special care has to be taken for the dicing of the chips(by diamond scribing) and standard DIL ceramic high tempera-ture package and epoxy glue were used.

B. On SOI Substrate

In the case of SOI-CMOS technology, the starting materialis a SOI UNIBOND 200- m double-side polished wafer with


Fig. 8. Schematic process flow of integrated SOI-CMOS microheater. (Left) A SOI CMOS circuit is realized jointly with (right) the microheater on membrane.

Fig. 9. Four configurations of loop-shape polysilicon resistor.

a buried oxide of 400 nm and a 100-nm-thick silicon film[Fig. 8(a)].

Fig. 10. Dimension values of polysilicon resistor: L and L arerespectively equal to 120 and 200 �m in each configuration. Values of Sand S are given in Table II.

After an initial oxidation, the silicon film can be patternedat the future membrane location and completely etched in thisarea [Fig. 8(b)]. A standard nitride layer of 200-nm thick is thendeposited and patterned to protect the electronics active zonesfrom the LOCOS field oxidation [Fig. 8(c)]. After LOCOS, this


Fig. 11. Thermal resistance calibration: Resistance variation versus applied temperature.

Fig. 12. DC Power consumption versus temperature elevation measurementsfor three different sizes of square membranes (840 �m, 640 �m, and 440 �mon one side) supporting the same resistor configuration (number 4).

nitride is removed and replaced by a new nitride layer of 300 nm[Fig. 8(d)] to implement the two first layers of our three stackeddielectric membrane with the 400-nm-thick SOI buried oxide.The next steps [Fig. 8(e)] of the process are the same than for aclassical SOI-CMOS process and completed by the TMAH bulkmicromachining.

TABLE IIDIMENSIONAL PARAMETERS FOR THE LOOP-SHAPED MICROHEATER SHOWN IN

FIG. 11 (l AND l ARE, RESPECTIVELY, TOTAL LOOP AND ACCESS

LENGTH) AND CALCULATED RESISTANCES OF THE POLYSILICON LINE

TABLE IIICOMPARISON OF OUR DESIGN WITH RECENT

PUBLISHED MICROHEATERS RESULTS


Fig. 13. Comparison of measured power consumption for the four resistor configurations (membrane size: 640� 640 �m ).

Outside of the membrane, the upper monocristalline siliconfilm is advantageously used to integrate reliable electronics closeto the microheater at the same time. It would be more difficult tomake this co-integration using standard bulk technology.

VI. MICROHEATER CHARACTERIZATION AND RESULTS

Four configurations (Figs. 9 and 10) of loop-shaped heatershave been tested. Meanders are introduced to increase the resis-tance in the loopand, therefore, increase the thermalconductivity.The difference between the first and the second is the width of thepolysilicon access lines to measure their impact on the electricalpower consumption. The third has a larger meander period andthe fourth has the classical configuration as a control.

The four metallic contacts allow a four-point measurementof resistance (and then temperature) simultaneously with Jouleheating. Before the measurements, we calibrated the polysiliconresistance variation when changing the temperature applied tothe chip on a temperature ring hot chuck (Fig. 11).

This calibration was made at very low power ( 1 mW) notto disturb the thermal measurement. The observed variationis linear with a positive thermal coefficient (the thermal con-ductivity decreases if the temperature increases), which is theproperty of conductors. It means that when the temperatureincreases, the power dissipation increases in a hotter area and,thus, creates hot spots. A negative coefficient (insulator or semi-conducting behavior) would be better to have a more uniformtemperature distribution but it imposes a lower doping level ofpolysilicon, and, therefore, the increase of resistance involves apower consumption increase, which is not acceptable. As in our

case, a polysilicon resistance of 25 /square is a good tradeoffbetween good thermal uniformity and low-power consumptionfor microheaters and corresponds to usual values for IC process.

For heater measurement, an increasing current is applied ontwo bonding pads and the voltage is measured on the others.The resistance is extracted for each current and using the cal-ibrated curves, temperature can be found for each current andthus the power consumption versus membrane temperature. Per-formance of the heater can be judged in terms of power con-sumption versus temperature elevation. As shown in Fig. 12, theactive area of our membranes can be heated to working temper-atures of 400 C with less than 20 mW.

These results outperform most recent realizations (Table III).Moreover, our design provides better thermal uniformity overthe membrane as demonstrated by our simulations and at muchlower cost, since we use only standard CMOS materials. Ourexcellent results are mainly related to the comparatively smalltotal thickness of the membrane, which allows extremely highthermal insulation (about 15.000 C/W) from the bulk, and tothe novel loop shape of the polysilicon microheater.

The effect of membrane dimensions has been thoroughly in-vestigated (Fig. 12). It shows that power consumption decreasesslowly with larger membranes because the thermal insulation ismoreefficient.Italsoallowsit toworkathigher temperature,elim-inating the larger thermal flux to the substrate. There is, thus, atradeoff between robustness of the membrane and consumption.

The impact of access lines has also been considered, as theyare responsible for the main part of thermal flux to the substrate.The area perpendicular to the flux is four times larger in the first


Fig. 14. DC power consumption versus temperature elevation. Comparison between simulated (4 and �) and measured values (-) for a 640� 640 �m and 1-�mthick membrane in first resistor configuration (membrane size: 640� 640 �m ).

and third configurations of the heater than in the second one withsmaller access lines (Fig. 9) and its influence on measured powerconsumption corresponds to an increase of 2–3 mW (Fig. 13).An interesting observation has been done about the configura-tion 4 (see Fig. 9). In this configuration, 40% of the power isconsumed in the access lines against, respectively, 6%, 20%,and 3% for the types 1, 2, and 3. In these three configurations,the loop has a higher resistance than the access (see Table II) andsince the polysilicon access lines are set at a smaller tempera-ture than the resistor loop, they have a smaller resistivity andtherefore consume less power. In configuration 4, the accesseshave almost the same resistance as the loop (see Table II) and,therefore, consume almost the same power.

In conclusion, Fig. 13 shows that, for a given membranesize, the best results are obtained with the second configurationthanks to its confined accesses and its small meanders in theloop to increase the thermal uniformity.

Finally, the comparison between simulations and exper-imental results (Fig. 14) shows a good agreement betweenmeasurements and simulated values with a thermal coefficientof 5 W/m K, which confirms our previous assumption.

VII. CONCLUSION

To reduce the power consumption of a fully CMOS com-patible microheater, we propose a new solution using a newloop-shaped resistor design supported by a 1- m thin stackeddielectric membrane. This membrane is released in post-pro-cessing using optimized fully CMOS IC compatible TMAH-

based etching technique. Very high thermal insulation and uni-formity were exhibited by ANSYS simulator and confirmed byour experimental results. The membrane temperature over con-sumed power ratio of our microhotplate polysilicon heater wascharacterized and found to be 15 C/mW, which is an excel-lent result in comparison with recent published microheatersresults. This allows the fabrication of robust smart gas sensorsin CMOS-SOI technology by deposition of metallic–oxide gas-sensitive layer after the simultaneous realization of the micro-heater and the close electronics in the silicon thin film. Thanksto the excellent thermal uniformity over the membrane and thegood thermal conductivity of metallic oxide, thermal simula-tions confirm a very low temperature variation on the whole240 240 m of active heated area. This uniformity is ob-tained without using additional aluminum or silicon spreaderswhich increase the consumption of most recent devices.

ACKNOWLEDGMENT

The authors would like to thank Dr. E. Llobet and his staff(Universitat Rovira i Virgili, Department of Electronic Engi-neering) for providing gas sensors with SnO and WO as sen-sitive layers. They would also like to thank the UCL staff forhelp in microheater fabrication.

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Jean Laconte was born in Brussels, Belgium,in 1976. He received the Industrial Engineer de-gree from the Ecole Centrale des Arts et Metiers,Belgium, in 1998 and the M.S. degree in appliedsciences from the Université catholique de Louvain(UCL), Louvain-la-Neuve, Belgium, in 1999. He iscurrently pursuing the Ph.D. degree at the Micro-electronics Laboratory, UCL.

He has studied in depth some material properties,like residual stresses in standard microelectonicslayers and polyimides. He has a lot of experience

and a real interest in clean-room processes and process equipment, especiallyphotolithography and silicon wet etching. He is member of the Research Centerin Micro and Nanoscopic Materials and Electronic Devices, UCL, and authoror co-author of more than 20 scientific articles. He is currently working onmicromachined sensors on membranes (microheaters, gas, flow, and humiditysensors) integrated in CMOS-SOI technology to provide complete smartsensors in one chip. His research interests are the modeling, design, characteri-zation, and fabrication of these kinds of sensors fully compatible with CMOSprocesses.

Cédric Dupont was born in Vienna, Austria. Hereceived the Engineer’s degree in electromechanicalengineering from the Université catholique de Lou-vain, Louvain-La-Neuve, Belgium, in 2001 and theM.S. degree in electrical engineering from StanfordUniversity, Stanford, CA, in 2002.

He is currently a Research Engineer at theElectronics Research Laboratory of Volkswagenof America, Palo Alto, CA. His research interestsinclude processing of electronic materials andpolymer/organic electronics.

Denis Flandre (M’91) was born in Charleroi, Bel-gium, in 1964. He received the Electrical Engineerdegree, the Ph.D. degree, and the Post-DoctoralThesis degree from the Université catholique deLouvain (UCL), Louvain-la-Neuve, Belgium, in1986, 1990, and 1999, respectively. His doctoralresearch was on the modeling of SOI MOS devicesfor characterization and circuit simulation, andhis post-doctoral thesis was on a systematic andautomated synthesis methodology for MOS analogcircuits.

In 1985, he was a summer student trainee at NTT Headquaters, Tokyo, Japan.From October 1990 to September 1991, he was with the Centro Nacional deMicroelectrònica, Barcelona, Spain, working on the characterization and nu-merical simulation of SOI MOS processes and devices. He was with the Lab-oratoire de Microélectronique (DICE), Louvain-la-Neuve, Belgium, as SeniorResearch Associate of the National Fund for Scientific Research (FNRS, Bel-gium). Since 2001, he has been a full-time Professor at UCL teaching courseson integrated analog circuit design and device physics. Since September 2003,he has been the Head of the UCL Microelectonics Laboratory. He is a memberof the Advisory Board of the EU Network of Excellence for High-Tempera-ture Electronics (HITEN), the Scientific Board of the “Microserv” large infra-structure EU program of the CNM-Barcelona, the Executive Board of SINANO(the new EU Network of Excellence in Silicon Nano-devices), and the DirectorBoard of the Cyclotron Research Center (CRC, Louvain-la-Neuve, Belgium).He is a founding member of the Centre de Recherche en Matériaux et DispositifsElectroniques Micro- et Nanoscopiques, UCL, and chairs the Users Commiteeof the UCL Micro/Nano-Technology facility. He is a co-founder of CISSOIDS.A., a start-up company which spun off from the UCL in July 2000, focusingon SOI circuit design services. He has authored or coauthored more than 180technical papers or conference contributions and holds several patents. He iscurrently involved in the research and development of SOI MOS devices, dig-ital and analog circuits, as well as sensors and MEMS, for special applications,more specifically for high-speed, low-voltage, low-power, microwave, rad-hard,and high-temperature electronics and microsystems.

Prof. Flandre is the recipient of the 1992 Biennial Siemens—FNRS Awardfor an original contribution in the fields of electricity and electronics, the 1997Wernaers Prize for innovation in pedagogical presentation of advanced researchwork, and the 1999 CEN�SCK prize for innovation in nuclear science instru-mentation.

Jean-Pierre Raskin (M’97) was born in Aye, Bel-gium, in 1971. He received the Industrial Engineerdegree from the Institut Superieur Industriel d’Arlon,Belgium, in 1993 and the M.S. and Ph.D. degreesin applied sciences from the Université catholiquede Louvain (UCL), Louvain-la-Neuve, Belgium, in1994 and 1997, respectively.

From 1994 to 1997, he was a Research Engineerat the Microwave Laboratory, UCL. He workedon the modeling, characterization, and realizationof MMICs in SOI technology for low-power,

low-voltage applications. In 1998, he joined the Electrical Engineering andComputer Science Department, University of Michigan, Ann Arbor. He hasbeen involved in the development and characterization of micromachiningfabrication techniques for microwave and millimeter-wave circuits and mi-croelectromechanical transducers/amplifiers working in hard environments.Since January 2000, he has been an Associate Professor at the MicrowaveLaboratory, UCL. He is a member of the Research Center in Micro andNanoscopic Materials and Electronic Devices, UCL. He is author or co-authorof more than 100 scientific articles. His research interests include the modeling,characterization, and fabrication of SOI MOSFETs for RF and microwaveapplications, planar circuits at millimeter and submillimeter waves frequencies,and RF microelectromechanical systems (MEMS) and micromachined sensors.

670 ieee sensors journal, vol. 4, no. 5, october …peter/534a/cmos_heater.pdf · soi cmos...

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