64607370 t spice examples

T-Spice Examples Guide—Contents

T-Spice12 Examples Guide 1

1 Introduction 3The T-Spice Pro™ Circuit Simulation System . . . . . . . . . . . . . . . . . . . . 3

2 Circuit Analysis Examples 5Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Example 1: DC Operating Point Analysis . . . . . . . . . . . . . . . . . . . . . . . . 6

Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6SPICE Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Export the Netlist to T-Spice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Run the Simulation In T-Spice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Open the Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Example 2: DC Transfer Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Example 3: Transient Analysis: Inverter . . . . . . . . . . . . . . . . . . . . . . . . 13Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Example 4: AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Example 5: Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Example 6: Transient Analysis: CMOS D-Latch . . . . . . . . . . . . . . . . . . 21Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Example 7: Transient Analysis, Powerup Mode. . . . . . . . . . . . . . . . . . 24Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Example 8: Transient Analysis, Preview Mode. . . . . . . . . . . . . . . . . . . 27Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Example 9: Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Example 10: Table Model Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . 32T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Example 11: Transistor Subthreshold Behavior . . . . . . . . . . . . . . . . . 33T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Example 12: MOS Transconductance Amplifier. . . . . . . . . . . . . . . . . . 36

T-Spice Examples Guide—Contents(Continued)

T-Spice12 Examples Guide 2

Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Design Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Wide-Band GaAs IC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Voltage Controlled Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Index 40

Credits 47

T-Spice 12 Examples Guide 3

1 Introduction

The T-Spice Pro™ Circuit Simulation System

T-Spice Pro is a complete circuit design and analysis system that includes:

S-Edit schematic editor. S-Edit is a powerful design capture and analysis package that can generatenetlists directly usable in T-Spice simulations.

T-Spice circuit simulator. T-Spice performs fast and accurate simulation of analog and mixedanalog/digital circuits. The simulator can analyze large, complex designs with hundreds ofthousands of circuit elements. Included within T-Spice is the Advanced Model Package. TheT-Spice Advanced Model Package includes the latest and best device models available, to help youget the most realistic simulation results possible. The Advanced Model Package also includescoupled line models and support for user-defined device models via tables or C functions.

W-Edit waveform viewer. W-Edit displays T-Spice simulation output waveforms as they are beinggenerated during simulation.

The design cycle for the development of electronic circuits includes an important pre-fabricationverification phase. Because of the expense and time pressures associated with the fabrication step,accurate verification is crucial to an efficient design process. The role of T-Spice is to help design andverify a circuit’s operation by numerically solving the differential equations describing the circuit.T-Spice simulation results allow circuit designers to verify and fine-tune designs before submittingthem for fabrication.

T-Spice is in many ways like the industry-standard SPICE simulation program:

Input language. T-Spice uses an extended version of SPICE’s input language.

Analysis modes. T-Spice performs the same basic analyses as does SPICE (DC, AC, transient, andnoise).

Device models. T-Spice incorporates all of SPICE’s device models, and more: resistors, capacitors,inductors, mutual inductors, single and coupled transmission lines, current sources, voltagesources, controlled sources, and a full complement of semiconductor device models for p-n diodes,BJTs, JFETs, MESFETs, and MOSFETs.

T-Spice also incorporates numerous innovations and improvements not found in other SPICE andSPICE-compatible simulators:

Speed. T-Spice provides highly optimized code for evaluating device models, formulating thesystems of linear equations, and solving those systems. In addition to the standard direct modelevaluation, T-Spice also provides the option of table-base transistor model evaluation, in which theresults of device model evaluations are stored in tables and reused. Because evaluation of devicemodels can be computationally expensive, this technique can yield dramatic simulation speedincreases.

Convergence. T-Spice uses advanced mathematical methods to achieve superior numericalstability. Large circuits and feedback circuits, impossible to analyze with other SPICE products,can be simulated in T-Spice.


Chapter 1: Introduction The T-Spice Pro™ Circuit Simulation System

Accuracy. T-Spice uses very accurate numerical methods and charge conservation to achievesuperior simulation accuracy.

Advanced models. T-Spice incorporates the latest and best transmission-line and semiconductordevice models to give you simulation results which are closer to real-world behavior, including thelatest Berkeley, Philips Labs, and MOSFET.

Macromodeling. T-Spice simulates circuits containing “black box” macrodevices. A macrodevicecan directly use experimental data as its device model. Macrodevices can also represent complexdevices, such as logic gates, for which only the overall transfer characteristics are of interest.

Input language extensions. The T-Spice input language is an enriched version of the standardSPICE language. It contains many enhancements, including parameters, algebraic expressions, anda powerful bit and bus input wave specification syntax.

External model interface. Users can develop custom device models using C or C++.

Runtime waveform viewing. The W-Edit waveform viewer displays graphical results duringsimulation. T-Spice analysis results for voltages, currents, charges, and power can be written tosingle or multiple files.

T-Spice maintains compatibility with traditional circuit simulation tools, while using the best availablesimulation technology to deliver results as quickly and accurately as possible.


2 Circuit Analysis Examples

Overview

This collection of examples provides a hands-on introduction to the integrated components of theT-Spice Pro circuit analysis suite. The most common types of analysis and simulation features will bedemonstrated, including:

DC operating point computations

DC transfer sweeps

Transient analysis

AC and noise analysis

Direct versus table-based model evaluation


Chapter 2: Circuit Analysis Examples Example 1: DC Operating Point Analysis

Example 1: DC Operating Point Analysis

DC operating point analysis finds a circuit’s steady-state condition, obtained (in principle) after theinput voltages have been applied for an infinite amount of time.

Schematic

This CMOS inverter is also used in Example 2: DC Transfer Analysis, Example 3: Transient Analysis:Inverter, and Example 10: Table Model Evaluation.

Each of the components visible in the schematic has properties associated with it. Properties are textualelements, created in S-Edit, that are attached to an object and provide key information about its designand simulation commands in T-Spice. For example, the physical dimensions of the component M1 aredefined by the properties:

L = 5UW = 8U

M1 is an instance of the symbol MOSFET_N, which represents an n-channel MOSFET transistor.Propertiess that describe the operation of a generic n-channel MOSFET are defined at the symbol level.Properties specific to component M1, such as length and width, are defined when M1 is created.Property values defined at the component level take precedence over default (symbol) values.

SPICE Simulation Setup

Prior to running the T-Spice simulation, the analysis commands and all processing options need to beestablished. This is accomplished through the Setup SPICE Simulation dialog.

Schematic inverter_op

T-Spice Input inverter_op.sp

Output inverter_op.out



Ensure that you are viewing the top level schematic. For this example, the top level cell is namedinverter. Double clicking inverter in the Library Navigator window will open the proper schematic.

Press the Setup Simulation toolbar icon to launch the Setup SPICE Simulation dialog. For theinverter_op example, the proper simulation settings have already been established for you. Note thatthe DC Operating Point Analysis box is checked. Also note the settings in the General options forFile Search Path and Include file.

Export the Netlist to T-Spice

In the inverter_op schematic, use Tools > Design Checks to execute the Design Checker.

The Design Checker will display any violation or errors in the Command window. If the fileinverter_op is unaltered, there should not be any errors.

Press the T-Spice icon ( ) to export a T-Spice netlist file named inverter_op.sp. S-Edit will launchT-Spice with the inverter_op.sp netlist open.

T-Spice Input

********* Simulation Settings - General section *********.option search="C:\S-Edit v12\Examples\models".include "ml2_125.md"

********* Simulation Settings - Parameters and SPICE Options *********

m1n out in Gnd Gnd nmos L=5u W=8uVdd Vdd Gnd 3m1p out in Vdd Vdd pmos L=5u W=12uc2 out Gnd 800f



vin in Gnd 1

********* Simulation Settings - Analysis section *********.op

.end

Two transistors, M1N and M1P, are defined in inverter_op.sp. These are MOSFETs, as indicated by thekey letter M that begins their names. Following each transistor name are the names of its terminals in therequired order: drain–gate–source–bulk. Then the model name (nmos or pmos in this example) andphysical characteristics, such as length and width, are specified.

A capacitor C1 (signified by the key letter C) connects nodes OUT and GND with a capacitance of 800femtofarads. (Strictly speaking, the capacitor could be omitted from the circuit for this example, since itdoes not affect the DC operation of the inverter.)

Two DC voltage sources are defined: VDD, which sets node VDD to 3.0 volts relative to system ground,and VIN, which sets node IN to 1.0 volt relative to ground.

Notice that the simulation settings which were entered in the SPICE Simulation Setup dialog resultedin .option, .include, and .op commands being written to the T-Spice input file. The .INCLUDEcommand causes T-Spice to read the contents of the model file ml2_125.md for the evaluation oftransistors M1 and M2, and the search option identifies the path to the include (.include ...) and library(.lib ...) files. In this case, the model file contains two .model commands, describing MOSFET modelsnmos and pmos:

.model nmos nmos+ Level=2 Ld=0.0u Tox=225.00E-10+ Nsub=1.066E+16 Vto=0.622490 Kp=6.326640E-05+ Gamma=.639243 Phi=0.31 Uo=1215.74+ Uexp=4.612355E-2 Ucrit=174667 Delta=0.0+ Vmax=177269 Xj=.9u Lambda=0.0+ Nfs=4.55168E+12 Neff=4.68830 Nss=3.00E+10+ Tpg=1.000 Rsh=60 Cgso=2.89E-10+ Cgdo=2.89E-10 Cj=3.27E-04 Mj=1.067+ Cjsw=1.74E-10 Mjsw=0.195

.model pmos pmos+ Level=2 Ld=.03000u Tox=225.000E-10+ Nsub=6.575441E+16 Vto=-0.63025 Kp=2.635440E-05+ Gamma=0.618101 Phi=.541111 Uo=361.941+ Uexp=8.886957E-02 Ucrit=637449 Delta=0.0+ Vmax=63253.3 Xj=0.112799u Lambda=0.0+ Nfs=1.668437E+11 Neff=0.64354 Nss=3.00E+10+ Tpg=-1.000 Rsh=150 Cgso=3.35E-10+ Cgdo=3.35E-10 Cj=4.75E-04 Mj=.341+ Cjsw=2.23E-10 Mjsw=.307

ml2_125.md assigns values to various Level 2 MOSFET model parameters for both n- and p-channeldevices. T-Spice uses these parameters to evaluate Level 2 MOSFET model equations, and the resultsare used to construct internal tables of current and charge values. Values read or interpolated from thesetables are used in computations called for by the input file.

The .OP command performs a DC operating point calculation and writes the results to the file specifiedin the Simulation > Run Simulation dialog.



Run the Simulation In T-Spice

With inverter_op.sp open in T-Spice, use File > Save to save the file.

Click the Run Simulation button ( ) in the T-Spice simulation toolbar.

In the Run Simulation dialog, click Start Simulation.

T-Spice will open a new window displaying the simulation results.

Output

The output file lists the DC operating point information for the circuit. You can read the file in T-Spiceor a text editor.

Open the Output File

Select View > Simulation Manager from the T-Spice menu to bring up the Simulation Manager (if notalready displayed):

Select the inverter_op display line in the window, and then left-click on the Show Output button toopen the output file, inverter_op.out, in a new T-Spice window.

If you prefer to view the output in a text editor, simply open inverter_op.out as a text file. (It is locatedin the same directory as the input file.)

The output file contains the following DC operating point information (in addition to comments ofvarious kinds, not shown here):

DC ANALYSIS - temperature=25.0 v(in) = 1.0000e+000v(out) = 2.9317e+000v(Vdd) = 3.0000e+000i(Vdd) = -5.8077e-006i(vin) = 0.0000e+000


Chapter 2: Circuit Analysis Examples Example 2: DC Transfer Analysis

Example 2: DC Transfer Analysis

DC transfer analysis is used to study the voltage or current at one set of points in a circuit as a functionof the voltage or current at another set of points. This is done by sweeping the source variables overspecified ranges and recording the output.

Schematic

This schematic includes a .print command, which measures and records voltages at the input and outputnodes of the circuit. The command is contained within the DC analysis output cell.

T-Spice Input

.probe

.option probev

.include "C:\S-Edit v12\Examples\models\ml2_125.md"m1n out in Gnd Gnd nmos L=5u W=8um1p out in Vdd Vdd pmos L=5u W=12uc2 out Gnd 800fvin in Gnd 1vdd Vdd Gnd 3.print dc v(in) v(out).dc lin vin 0 3 .02 lin vdd 2 4 .5

Schematic inverter_dc

T-Spice Input inverter_dc.sp

Output inverter_dc.out



The .DC command, indicating transfer analysis, is followed by the parameter LIN, which specifies alinear sweep. Next is a list of sources to be swept, and the voltage ranges across which the sweeps are totake place.

In this example, VIN will be swept from 0 to 3 volts in 0.02 volt increments, and VDD will be sweptfrom 2 to 4 volts in 0.5 volt increments.

The transfer analysis will be performed as follows: VDD will be set at 2 volts and V1 will be swept overits specified range; VDD will then be incremented to 2.5 volts and V1 will be reswept over its range; andso on, until VDD reaches the upper limit of its range.

The .DC command ignores the values assigned to the voltage sources VDD and V1 in the voltage sourcestatements; however, they must be declared in those statements.

The resulting voltages for nodes IN and OUT are reported by the .PRINT DC command to the specifieddestination.

Output

When W-Edit launches, simulation results of the same data type, which in this case is voltage, areautomatically plotted on a single chart. In this example, traces were separated into different charts andreorganized (according to data type) using the commands Chart > Options—General and Chart >Options—Axes in the W-Edit menu.

The following charts show input and output voltages to the circuit, with separate traces for each sweepof VIN. To view detailed information about a trace, double-click on the trace or on the trace labellocated in the upper right corner of the chart. The Trace Properties dialog displays the value ofparameter VDD corresponding to each trace, as well as labels and line properties. For more informationon trace properties, see Properties in the W-Edit User Guide.


Chapter 2: Circuit Analysis Examples Example 3: Transient Analysis: Inverter

Example 3: Transient Analysis: Inverter

Transient analysis provides information on how circuit elements vary with time.

The basic T-Spice command for transient analysis has three modes. In the op mode (default), the DCoperating point is computed, and T-Spice uses this as the starting point for the transient simulation.Example 3 illustrates this option. (The other modes, powerup and preview, are treated in Example 7:Transient Analysis, Powerup Mode on page 24 and Example 8: Transient Analysis, Preview Mode onpage 27.)

Schematic

T-Spice Input

.option search="C:\S-Edit v12\Examples\models"

.probe

.option probev

.option probei

.include "ml2_125.md"m1n out in Gnd Gnd nmos L=5u W=8um1p out in Vdd Vdd pmos L=5u W=12uc2 out Gnd 800fvin in Gnd pwl (0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V 300ns 0V 305ns 3V

400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V)vdd Vdd Gnd 3.print tran v(in) v(out)

Schematic invert_tran

T-Spice Input invert_tran.sp

Output invert_tran.out


Chapter 2: Circuit Analysis Examples Example 3: Transient Analysis: Inverter

.tran 1n 600n

.end

This circuit is identical to that of Example 1, except that voltage source VIN here generates a piecewiselinear waveform input (indicated by the keyword PWL) to IN, rather than setting a constant value.

The times and voltages that define “legs” of the waveform are specified in the arguments to PWL.Between 0 and 100 nanoseconds, the voltage at IN is zero; between 100 and 105 nanoseconds, thevoltage is linearly interpolated (ramps up) between 0 and 3; between 105 and 200 nanoseconds, thevoltage stays at 3; and so on.

The .TRAN command specifies the characteristics of the transient analysis to be performed: it will lastfor 600 nanoseconds, with time steps no larger than 2 nanoseconds.

Output


Chapter 2: Circuit Analysis Examples Example 4: AC Analysis

Example 4: AC Analysis

AC analysis characterizes the circuit’s behavior dependence on small-signal input frequency. Itinvolves three steps: (1) calculating the DC operating point; (2) linearizing the circuit; and (3) solvingthe linearized circuit for each frequency.

Example 4 involves a standard operational amplifier, consisting of seven MOSFETs (four n-channeland three p-channel) and two capacitors.

Schematic

T-Spice Input

.option Accurate

.option search="C:\S-Edit v12\New Examples\models"

.probe

.option probev

.include "ml2_125.md"Vdd Vdd Gnd 5cout out Gnd 2pmp1 vm1 vm1 Vdd Vdd pmos L=6u W=6u mp2 vf1 vm1 Vdd Vdd pmos L=6u W=6u mp3 out vf1 Vdd Vdd pmos L=6u W=20u mn1 vn1 vbias Gnd Gnd nmos L=10u W=6u

Schematic opamp_ac

T-Spice Input opamp_ac.sp

Output opamp_ac.out



vdiff in2 in1 -700u AC 1 90mn2 vm1 in1 vn1 Gnd nmos L=6u W=6u mn3 vf1 in2 vn1 Gnd nmos L=6u W=6u mn4 out vbias Gnd Gnd nmos L=10u W=6u vin1 in1 Gnd 2vbias vbias Gnd 800mccomp vf1 out 2p.print ac vdb(out) vp(out).op.ac dec 5 1 100meg.end

Three voltage sources (in addition to VDD) are defined.

VDIFF sets the DC voltage difference between nodes IN2 and IN1 to –0.0007 volts; its ACmagnitude is 1 volt and its AC phase is 90 degrees.

VIN1 sets node IN1 to 2 volts, relative to GND.

VBIAS sets node BIAS to 0.8 volts, relative to GND.

The .AC command performs an AC analysis. Following the .AC keyword is information concerning thefrequencies to be swept during the analysis. In this case, the frequency is swept logarithmically, bydecades (DEC); 5 data points are to be included per decade; the starting frequency is 1 Hz and theending frequency is 100 MHz.

The .PRINT command writes the voltage magnitude (in decibels) and phase (in degrees), respectively,for the node OUT to the specified file.

Output

The AC simulation will automatically result in DC Operating Point information and AC small-signalmodel parameters being written to the output file, in addition to all output generated from.print statements.


Chapter 2: Circuit Analysis Examples Example 5: Subcircuits

Example 5: Subcircuits

Subcircuit definitions allow arbitrarily complex arrangements of nodes and devices to be easily reusedmultiple times in a circuit. A subcircuit definition in S-Edit is contained within a cell definition, and iscomprised of both a schematic view and a symbol view. Each instance of the symbol encapsulates thesubcircuit schematic, allowing a simple but complete representation of subcircuit dynamics.

Example 5 uses a NAND gate to illustrate the use of subcircuit definitions and subcircuit parameters.

Schematic

An instance of the subcircuit NAND is created in the schematic and labeled XNAND1. To access nandfrom the main schematic, double-click on the NAND item in the Library Navigator window.

As discussed in Example 1, symbol properties are used to define component properties such as lengthand width. This example introduces a new symbol property, SPICE.PARAMETER, which allowsparameters to be passed through a hierarchical netlist. The symbol that represents nand has theproperty:

SPICE.PARAMETER = L NW PW

This statement specifies that the cell properties L, NW, and PW are subcircuit parameters of NAND. Thecell also contains the 3 property definitions:

Schematic nandgate

T-Spice Input nandgate.sp

Output nandgate.out



L = 5uNW = 10uPW = 10u

These parameters define properties of all n-channel and p-channel MOSFETS within the subcircuit:

L represents the length property of both n- and p-channel MOSFETS.

NW represents n-channel width.

PW represents p-channel width.

Attaching these parameters to NAND allows component properties within the subcircuit definition to becontrolled in the subcircuit call.

T-Spice Input

********* Simulation Settings - General section *********.option search="C:\S-Edit v12\Examples\models".probe.option probev.include "ml2_125.md".ic nand1/nn1=2V*************** Subcircuits *****************.subckt NAND in1 in2 out Gnd Vdd L=5u PW=10u NW=10u mt1 out in1 nn1 Gnd nmos L='l' W='nw' mt2 nn1 in2 Gnd Gnd nmos L='l' W='nw' mt3 out in1 Vdd Vdd pmos L='l' W='pw' mt4 out in2 Vdd Vdd pmos L='l' W='pw' .ends********* Simulation Settings - Parameters and SPICE Options *********Xnand1 a b outab Gnd Vdd NAND L=5u PW=12u NW=8u va a Gnd pwl(0 0 100n 0 105n 5 200n 5 205n 0 300n 0 305n 5 400n 5 405n 0 500n 0 505n 5 600n 5)vb b Gnd 5vvdd Vdd Gnd 5.print tran v(a) v(outab) v(nand1/nn1)********* Simulation Settings - Analysis section *********.op.tran 1n 600n.end

Subcircuits are defined by blocks of device statements bracketed with the .SUBCKT and .ENDScommands, and instanced by statements beginning with the key letter X.

The .SUBCKT command includes the name of the subcircuit being defined (NAND), a list of terminals,and three subcircuit parameters. The terminals do not have a predefined order, but whatever order isused in the definition must be used in instances. Parameters can be written in any order in both thedefinition and the instances. Parameter values specified in the definition are used as defaults when notspecified in instances.

Within the subcircuit definition, four MOSFETs are defined in the usual manner (and in thesestatements the order of terminals is important: drain–gate–source–bulk). Node N1 is the source oftransistor MT1 and the drain of transistor MT2. Subcircuit parameters, enclosed by single quotes, areused in place of numerical values.

After the subcircuit is defined, you can create an instance of the subcircuit. The instance statementbegins with the key letter X, but the name of the instance (by which it is to be identified in the rest of theinput file) is NAND1, not XNAND1.



The list of terminals in the instance statement must have the same order as on the first line of thesubcircuit definition: A B OUT(instance) corresponds to IN1 IN2 OUT (definition). The next argument ofthe instance statement is the original subcircuit name (NAND).

Two of the default subcircuit parameter values, as originally specified by the definition, are overriddenby instance-specific assignments. These assignments may appear in any order. The parameter omittedfrom the instance statement (L) retains its default value.

Initial conditions on node voltages and currents can be set for the purposes of computing the DCoperating point. The .IC command sets node NAND1/N1 (that is, node N1 of instance NAND1) to 2 voltsfor the duration of the DC operating point calculation. When transient analysis begins, the node willreturn to a floating voltage state.

Voltage source VA supplies a PWL (piecewise linear) input waveform to node A.

Two analyses are carried out on this circuit: a DC operating point calculation (.OP) and a transientsimulation (.TRAN) with a duration of 600 nanoseconds and a maximum timestep of 1 nanosecond.

The .PRINT command reports simulation results for the voltages at nodes A, OUT, and NAND1/N1.

Output


Chapter 2: Circuit Analysis Examples Example 6: Transient Analysis: CMOS D-Latch

Example 6: Transient Analysis: CMOS D-Latch

Transient analysis on a CMOS static D-latch demonstrates the analog D-latch characteristics of a digitalcircuit. The circuit has four inverters and four transmission gates.

Schematic

T-Spice Input

MTG3P N3 PHI2 N5 VDD PMOS L=5U W=12U MINV3P Q N5 VDD VDD PMOS L=5U W=12U MINV4P N4 Q VDD VDD PMOS L=5U W=12U MINV3N Q N5 GND GND NMOS L=5U W=8U MINV4N N4 Q GND GND NMOS L=5U W=8U MTG4P N5 PHI1 N4 VDD PMOS L=5U W=12U MTG3N N3 PHI1 N5 GND NMOS L=5U W=8U

VDD VDD GND 3V

VDATA DATA GND BIT ({1000} ON=3 OFF=0 DELAY=0 PW=20N RT=1.25N FT=1.25N)VPHI1 PHI1 GND BIT ({0011} ON=3 OFF=0 DELAY=0 PW=10N RT=1.25N FT=1.25N)VPHI2 PHI2 GND BIT ({1100} ON=3 OFF=0 DELAY=0 PW=10N RT=1.25N FT=1.25N)

MINV1N N3 N1 GND GND NMOS L=5U W=8U MINV1P N3 N1 VDD VDD PMOS L=5U W=12U MINV2P N2 N3 VDD VDD PMOS L=5U W=12U

Schematic dlatch

T-Spice Input dlatch.sp

Output dlatch.out



MINV2N N2 N3 GND GND NMOS L=5U W=8U MTG1N DATA PHI2 N1 GND NMOS L=5U W=8U MTG2P N1 PHI2 N2 VDD PMOS L=5U W=12U MTG1P DATA PHI1 N1 VDD PMOS L=5U W=12U MTG2N N1 PHI1 N2 GND NMOS L=5U W=8U MTG4N N5 PHI2 N4 GND NMOS L=5U W=8U

.TRAN 0.2N 200N

.INCLUDE ML2_125.MD

.GLOBAL VDD

.PRINT TRAN V(N3)

.PRINT TRAN V(Q)

.PRINT TRAN V(PHI1)

.PRINT TRAN V(DATA)

.PRINT TRAN V(N1)

.PRINT TRAN V(N5)

.PRINT TRAN V(PHI2)

.END

Voltage source VDD sets the voltage between power and ground to 3 volts.

The next three statements beginning with V define voltage sources for custom input waveforms.Following each voltage source name are the names of the input nodes and the type of waveform. Here,however, not piecewise linear but rather bit waveforms are used. Following the keyword BIT inparentheses are parameters specifying the waveform characteristics. The four-digit sequence in braces {} specifies the sequence of the wave’s states (either 1, “on,” or 0, “off”). This sequence will be repeateduntil the simulation is complete. The pulse width (PW) is 2 nanoseconds. The OFF voltage is zero, theON voltage is 3 volts, and the rise (RT) and fall (FT) times are each one-quarter of a nanosecond.

The .TRAN command instructs T-Spice to perform a 200-nanosecond simulation while printing nodevoltages at least every 0.2 nanoseconds.

The .PRINT commands write simulation results for the voltages at each of seven nodes to the specifiedfile.

Output

The following chart shows the seven output voltages measured during simulation, plotted across time.The traces have been expanded and reordered from the default setting.

When a chart is expanded, the traces will be displayed in the same order in which they were loaded.Traces can be loaded or unloaded on a chart with the Chart > Options—Format dialog.

Note: When a trace is added to an existing chart, the axes scaling is not automatically updated. To rescale theaxes for optimal display, you can use the HOME key.



Select Chart > Options—Axes to choose appropriate spacing of the major and minor tick marks.


Chapter 2: Circuit Analysis Examples Example 7: Transient Analysis, Powerup Mode

Example 7: Transient Analysis, Powerup Mode

Some circuits do not have a DC steady state or “quiescent” point. Because such circuits are constantlyfluctuating with time, finding the starting point for their simulation is a problem. More precisely, thechallenge is to define the initial state of a circuit which has no definite DC steady-state condition. Thisis done in T-Spice with the powerup option of the .tran command. The powerup option essentially setsthe entire circuit to zero for time equal to zero. As the simulation proceeds, the voltage sources areallowed to ramp up to their specified values.

The ring oscillator is an example of such a time-dependent circuit.

Schematic

T-Spice Input

.SUBCKT INVERT IN OUTM1 OUT IN GND GND NMOS L=5U W=8U M2 OUT IN VDD VDD PMOS L=5U W=12U C1 OUT GND 800FF.ENDS

VDD VDD GND 3VXINV1 N1 N2 INVERTXINV2 N2 N3 INVERTXINV3 N3 N4 INVERTXINV4 N4 N5 INVERT

Schematic ring

T-Spice Input ring.sp

Output ring.out



XINV5 N5 N6 INVERTXINV6 N6 N7 INVERTXINV7 N7 N1 INVERTC1 N1 GND 400FF .TRAN/POWERUP 1N 1U.INCLUDE ML2_125.MD.GLOBAL VDD

.PRINT TRAN V(N1)

.PRINT TRAN V(N2)

.PRINT TRAN V(N7)

.END

A subcircuit named INVERT is defined with two terminals. (This inverter is structurally identical to theone used in Example 1 and Example 4.)

Seven instances of the subcircuit, labeled INV1 through INV7, are defined next. The output of eachinverter is connected to the input of the next in the ring.

The POWERUP option of the .TRAN command eliminates the DC convergence problem for unstablecircuits. If the POWERUP option were not specified, then T-Spice would try to calculate a DC operatingpoint, which would lead to problems for this oscillator.

This simulation example also introduces us to two of the more powerful advaanced features of T-Spice:parameter sweeping and the .measure command.

In the T-Spice Simulation Setup, a parameter sweep is defined, in which the capacitor value is varied ina linear sweep from 200 femto-Farads to 1000 femto-Farads in increments of 200. This results in 5 setsof simulation results being generated, one for each capacitor value.

The .measure command is a tool for capturing and summarizing the electrical behavior of a circuit.Information such as delay, rise and fall times, minimum and maximum signal values, and a host of othercomputed results can be aquired with these measurements. In this example, 3 measurements arecomputed, period, pulsewidth, and delay. Since the simulation also includes a parameter sweep, aseperate set of measurement values will be computed for each parameter value (capacitance), anddisplayed in a summary table at the end of the Simulation log.



Output


Chapter 2: Circuit Analysis Examples Example 8: Transient Analysis, Preview Mode

Example 8: Transient Analysis, Preview Mode

Before a lengthy transient simulation is run on a large circuit, the input waveforms can be examinedusing the preview option of the .tran command. This option instructs T-Spice to report only specifiedinput stimuli, and to forego simulation of the remainder of the circuit.

In addition to illustrating the preview mode, this simple “wave” circuit showcases the variety andflexibility of input patterns available to current and voltage sources in T-Spice.

Note: This example does not include a schematic. The T-Spice netlist is located in the spice subdirectory ofthe examples installation. In T-Spice, use File > Open to open the provided netlist directly.

Schematic

For a description of this circuit, see Input, below.

T-Spice Input

r1 n1 GND 2kr2 n2 GND 2kr3 n3 GND 2kr4 n4 GND 2kr5 n5 GND 2kr6 n6 GND 2kr7 n7 GND 2kr8 n8 GND 2kr9 n9 GND 2kv1 n1 GND pwl (0n 0 100n 0 101n 5 300n 5 301n 0 + 500n 0 680n 5 700n 0 880n 5 900n 0)v2 n2 GND pwl (0n 0 100n 0 101n 1 200n 1 201n 2 300n 2 301n 3+ 400n 3 401n 4 500n 4 501n 5 600n 5 601n 4 + 700n 4 701n 3 800n 3 801n 2 900n 2 901n 1)v3 n3 GND sin (2.5 2.5 30MEG 100n)v4 n4 GND bit ({01010 11011} on=5.0 off=0.0 pw=50n rt=10n ft=30n)v5 n5 GND bit ({5(01010 5(1))} pw=10n on=5.0 off=0.0).vector bb {n6 n7 n8 n9}vb bb GND bus ({50(Ah) 30(7d4) 20(1000)} pw=5n on=5.0 off=0.0).print tran n1 n2 n3 n4 n5 n6 n7 n8 n9.tran/preview 1n 1u

Nine resistor/node/voltage source combinations, numbered 1 through 9, are defined. Each resistor has aresistance of 2 kilohms; each voltage source, connected across the corresponding resistor to ground,supplies its characteristic waveform to the corresponding node.

Two voltage sources, v1 and v2, generate pwl (piecewise linear) inputs. v1 produces a single pulsefollowed by a pair of sawtooth cycles, and v2 produces a staircase waveform which takes 1-volt stepsfrom zero up to 5 volts and back down to 1 volt.

T-Spice Input wave.sp

Output wave.out



Voltage source v3 generates a sin (sinusoidal) input. It has an amplitude of 2.5 volts, a frequency of 30MHz, an offset of 2.5 volts from system ground, and a time delay of 100 nanoseconds after the start ofthe simulation before the wave begins.

Voltage source v4 generates a bit input. Enclosed in braces { } are two binary-valued five-bit patternsspecifying the waveform. The two patterns alternate in time. The on voltage value is 5.0 volts; the offvoltage value is zero. The pulse width (pw), 50 nanoseconds, is the time the wave is either (ramping upand) on, or (dropping down and) off. The rise time (rt), 10 nanoseconds, is the time given for the waveto ramp from off to on; the fall time (ft), 30 nanoseconds, is the time given for the wave to drop from onto off.

Voltage source v5 generates a repeating bit input. Two distinct patterns are given again, but nowmultiplier factors are included. The wave consists of two alternating patterns: the first pattern containsfive bits, the second is a single bit. The five-bit pattern is followed by five successive repetitions of thesingle-bit pattern, and this sequence is repeated five times. (The same pattern could be described by{5(3(01) 4(1))}.) The pulse width and on and off voltages are again specified, but the rise and fall timestake default values.

The .vector command defines the bus waveform generated by voltage source vb. The command assignsthe bus a name (bb) and specifies by name the number of bits the bus waveform will have (four: n6through n9). The voltage source statement, which contains the bus keyword, specifies waveforms withone or more patterns, along with pulse width and level information. The patterns can be in binary,hexadecimal, octal, or decimal notation. (For decimal patterns the number of lower-order bits to becollected is also given.)

The first pattern is Ah (hex) = 1010 (binary). Thus, using the names given on the .vector command,n6=1, n7=0, n8=1, and n9=0. The pattern is repeated 50 times (that is, maintained for a time periodequal to the pulse width multiplied by 50).

The next pattern is 7d4 — that is, 7 (decimal) = 111 (binary), or, to four lower-order bits, 0111. Son6=0, n7=1, n8=1, and n9=1. The pattern is repeated 30 times.

The last pattern is 1000 (binary), so n6=1, n7=0, n8=0, and n9=0. The pattern is repeated 20 times.

The .print command writes the results at the output nodes of all nine voltage sources.

The .tran/preview command reports the input waveforms in place of running the simulation.



Output


Chapter 2: Circuit Analysis Examples Example 9: Noise Analysis

Example 9: Noise Analysis

Real circuits are never immune from small random fluctuations in voltage and current levels. InT-Spice, the influence of noise in a circuit can be simulated and reported in conjunction with ACanalysis. The purpose of noise analysis is to compute the effect of the noise associated with variouscircuit devices on an output voltage or voltages as a function of frequency.

Schematic

For a description of this circuit, see Example 4.

T-Spice Input

MN2 N1N4 IN1 VN1 GND NMOS L=6U W=6U MN3 N1N16 IN2 VN1 GND NMOS L=6U W=6U MP2 N1N16 N1N4 VDD VDD PMOS L=6U W=6U MN1 VN1 BIAS GND GND NMOS L=10U W=6U MP3 OUT N1N16 VDD VDD PMOS L=6U W=20U CCOMP N1N16 OUT 2PF MP1 N1N4 N1N4 VDD VDD PMOS L=6U W=6U MN4 OUT BIAS GND GND NMOS L=10U W=6U COUT OUT GND 2PF VBIAS BIAS GND 0.8VVDIFF IN2 IN1 DC -0.0007 AC 1 90VIN IN1 GND 2VVDD VDD GND 5V.PRINT NOISE TRANS='TRANSFER'.PRINT NOISE DN(MN1).NOISE V(OUT) VBIAS 5.PRINT NOISE ONOISE INOISE DB(ONOISE) DB(INOISE).AC DEC 5 1 100MEG.INCLUDE ML2_125.MD.GLOBAL VDD.END

Noise analysis is performed in conjunction with AC analysis; if the .AC command is missing, then the.NOISE command is ignored. With the .AC command present, the .NOISE command causes noiseanalysis to be performed at the same frequencies: starting at 1 Hz, ending at 100 MHz, with 5 datapoints per decade.

The .NOISE command takes two required arguments: the output at which the effects of noise are to becomputed, and the input at which the noise can be considered to be concentrated for the purpose ofestimating equivalent noise spectral density. Additionally, a third optional argument specifies thefrequency interval at which a noise report will be printed to the simulation log, listing every devicenoise contribution.

The .PRINT NOISE command, with six arguments, writes to the output file eleven numbers for eachfrequency analyzed. Many other options are available.

Schematic opamp_noise

T-Spice Input opamp_noise.sp

Output opamp_noise.out


Chapter 2: Circuit Analysis Examples Example 9: Noise Analysis

Output


Chapter 2: Circuit Analysis Examples Example 10: Table Model Evaluation

Example 10: Table Model Evaluation

T-Spice employs two fundamental techniques of simulation: direct model evaluation and table-basedevaluation.

In direct model evaluation, values are computed as needed from analytical equations, returningresults as accurate as the models used allow.

In table-based evaluation, tables of values are precomputed from analytical equations at finiteresolution, and needed values are linearly interpolated from stored values. This technique is slightlyless accurate, but is significantly faster.

Direct evaluation is T-Spice’s default simulation technique. Table-based model evaluation can beexplicitly selected, as in Example 10, which repeats the transient analysis of Example 1: DC OperatingPoint Analysis on page 6.

T-Spice Input

M1 OUT IN GND GND NMOS L=5U W=8U M2 OUT IN VDD VDD PMOS L=5U W=12U C1 OUT GND 800FF VDD VDD GND 3VVIN IN GND PWL (0 0 100N 0 105N 3 200N 3 205N 0 300N 0 305N 3 400N 3 + 405N 0 500N 0 505N 3 600N 3) .OPTIONS DEFTABLES=0 ABSTOL=5.0E-10 RELTOL=1.0E-4 CHARGETOL=1.0E-14 + RELCHARGETOL=1.0E-4 ACCT=1 VERBOSE=2 MAXORD=4.TRAN 2N 600N.INCLUDE ML2_125.MD

.GLOBAL VDD

.PRINT TRAN V(IN)

.PRINT TRAN V(OUT)

.END

This input file is identical to that of Example 3, with the added command .OPTIONSMODELMODE=CACHETABLE. This turns on the cache table generation in which model table aredynamically filled and interpreted during the simulation. Several other simulation options and defaultvalues are listed in the .OPTIONS command line.

Output

Compare inverter_table.out, obtained using internal table-based model evaluation, to invert_tran.out,obtained using direct modelevaluation. For the inverter or other digital circuits there will be only slightdifferences in the results. For analog circuits, however, there can be greater discrepancies betweenresults from the two evaluation techniques.

Schematic inverter_table

T-Spice Input inverter_table.sp

Output inverter_table.out


Chapter 2: Circuit Analysis Examples Example 11: Transistor Subthreshold Behavior

Example 11: Transistor Subthreshold Behavior

Modern analog designs are required to meet strict specifications with tight tolerances. Designerstherefore need models that can accurately simulate semiconductor device behavior over all regions ofoperation.

It has been traditionally difficult to model the operation of MOSFETs in the subthreshold region,particularly through the transition from subthreshold to above threshold. This region is of specialinterest to designers of low-power and advanced analog designs, in which MOSFETs are sometimesintentionally biased to operate in this transition region.

In subthreshold, the saturation drain current of a MOSFET is an exponential function of the gatevoltage, and the drain current saturates at a drain voltage that is independent of gate voltage. Well abovethreshold, the transistor drain current is a quadratic function of the gate voltage, and the drain currentsaturates at a drain voltage which is a function of the gate voltage.

T-Spice supports the simulation of MOSFETs in the subthreshold region in the following ways.

The MOSFET Level 47, 49, and 53 models (BSIM3 Revisions 2 and 3) in the Advanced ModelPackage include subthreshold characteristics.

The T-Spice simulation engine can accurately simulate low-current operation without convergenceproblems even when internal tables are used for improved speed.



Example 11 simulates the gate characteristics of a transistor in subthreshold by sweeping its gatevoltage while holding drain voltage fixed.

Note: Because this example does not include a schematic, you will bypass the S-Edit project and open yourinput file directly from T-Spice. Launch T-Spice and use File > Open to open the netlist, which islocated at ../spice/trangm.sp.

T-Spice Input

.include ml5_20.mdmn5 drain gate GND GND nmos l=10u w=6uvdrain drain GND 5vgate gate GND 0.85.dc vgate .5 1.5 0.01.print dc id(mn5).options abstol=1E-14

Voltage source vgate is attached to the gate terminal of the MOSFET mn5 and is swept from 0.5 to 1.5volts by the .dc command. Voltage source vdrain is attached to the drain terminal with a fixed value of5 volts, which keeps the transistor well in saturation. The source and bulk terminals are grounded.

The .print dc command reports current through the drain terminal of mn5.

The .options accurate command changes several option values in order to increase the overallsimulation accuracy, so that low-current and subthreshold behavior can be simulated accurately. .

Output

The logarithm of the current is a straight line for low gate voltages and shows a smooth transitionbetween low-current exponential behavior and high-current quadratic behavior.

T-Spice Input trangm.sp

Output trangm.out


Chapter 2: Circuit Analysis Examples Example 12: MOS Transconductance Amplifier

Example 12: MOS Transconductance Amplifier

The basic transconductance amplifier produces an output current proportional in magnitude to thedifference between the input voltages. Proper modeling of the transconductance amplifier’s outputcurrent behavior, over a broad range of differential voltages, requires accurate subthreshold modeling ofits transistors. Otherwise, the predicted transconductance characteristics will be inaccurate. This circuitcan be simulated correctly in subthreshold by T-Spice.

Schematic

T-Spice Input

.option Accurate

.option search="C:\S-Edit v12\Examples\models"

.include "ml5_20.md"

********* Simulation Settings - Parameters and SPICE Options *********

Vdd Vdd Gnd 5mp1 vm1 vm1 Vdd Vdd pmos L=6u W=6u vout out Gnd 2.5mp2 out vm1 Vdd Vdd pmos L=6u W=6u mn1 vn1 vbias Gnd Gnd nmos L=10u W=6uvdiff in2 in1 0mn2 vm1 in1 vn1 Gnd nmos L=6u W=6u mn3 out in2 vn1 Gnd nmos L=6u W=6u

Schematic transamp

T-Spice Input transamp.sp

Output transamp.out


Chapter 2: Circuit Analysis Examples Example 12: MOS Transconductance Amplifier

vin1 in1 Gnd 2vbias vbias Gnd 700m.print dc i1(vout) id(mn3) id(mn2)

********* Simulation Settings - Analysis section *********.op.dc lin vdiff -1 1 .01

.end

This circuit is identical to the one described in Example 4, except that the output stage (inverter) hasbeen removed, and a voltage source has been connected to the output so that the transconductancecharacteristics of the amplifier can be measured.

The .OPTIONS ACCURATE command changes, among other options, the absolute value of the currenttolerance that T-Spice uses, allowing low-current and subthreshold behavior to be simulated accurately.

Output


Chapter 2: Circuit Analysis Examples Design Examples

Design Examples

Following are design examples created and simulated by T-Spice Pro. These examples are intended toprovide a practical synthesis of the concepts presented in Examples 1-12, as well as to present somemore advanced features of T-Spice.

The design examples consist of two tutorial projects:

Wide-Band GaAs IC Amplifier

This example project describes the design and performance of a wide-band GaAs IC amplifier. Theamplifier consists of two cascaded stages. It features a high-voltage gain (>20 dB), wide bandwidth, andvery low input VSWR. This amplifier is useful for many signal processing and instrument/measurement applications.

The examples folder contains four examples for characterizing the AC, DC and transient performanceand measuring S-parameters of the circuit:

Each of the schematics amp_ac, amp_dc, and amp_tran contains components to generate T-Spiceanalysis functions that were explored in previous examples.

The transient analysis example, amp_tran, contains a polynomial voltage controlled voltage source.This provides a ramp-up sinusoidal wave as an input source.

The circuit shown in the schematic amp_sparam is wired in the same way that s-parameters aremeasured. The components labeled GAASAMP are instances of the basic GaAs IC Amplifier schematic,amp. AC analysis on nodes S11, S21, S12, and S22 provides the corresponding s-parameters: S11, S21,S12, and S22.

T-Spice reads the contents of model file gaas.md to obtain parameter values used in the evaluation ofMESFET and diode model equations. The model file is located in the main project directory.

T-Spice Pro GaAs Amp Files needed for simulation of a sample wide-band GaAs IC amplifier.

T-Spice Pro Ring VCO Files needed for simulation of a sample voltage-controlled ring oscillator.

amp_ac The amplifier schematic, containing commands for AC, noise, and small-signal parameter analysis.

amp_dc The amplifier schematic, containing commands for DC transfer analysis.

amp_sparam Schematic of a circuit design appropriate for measurement of the amplifier s-parameters.

amp_tran The amplifier schematic, containing commands for transient analysis.


Chapter 2: Circuit Analysis Examples Design Examples

Voltage Controlled Ring Oscillator

This example describes the design and performance of a voltage-controlled ring oscillator. The ringVCO consists of a control stage that provides bias and tuning voltage and seven differential cells thatform a ring oscillator. The tuning voltage from the control stage controls the frequency of the ringoscillator. The applications of VCO include frequency modulators, tone generators, A/D converters, anddigital voltmeters.

Additional files located in the ringvco directory include:

This example provides the option to model the ring VCO using the user-defined external model featurein T-Spice. The file vco.c is the ring VCO model written in the C programming language. This C file iscompiled and built into a dynamically linked library, vco.dll, before simulating the circuit. The filevco.dll can then be included in the SPICE input file for simulation in T-Spice.

Note: For more information on the external model feature in T-Spice, see User-Defined External Models in the T-Spice User Guide and Reference.

ringvco The ring oscillator schematic, containing commands for transient analysis.

control Subcircuit schematic for the bias control stage in the ring VCO.

diffcell Subcircuit schematic for a differential amplifier.

mosis2u.md MOSIS MOSFET 2um model parameters. This is the model that is used in simulating the design.

vco.c An external T-Spice macromodel of a voltage-controlled oscillator.

vco.dll A DLL which contains the VCO macromodel described above. This DLL is used by T-Spice during simulation.

vcomacro.sp A Spice file showing the performance of the VCO macro-model. This file has macromodel parameters tuned to match the performance of the actual circuit in ringvco.


Index

A

abstol keyword, 34AC analysis, 15.ac command, 16accuracy, 4, 34Advanced Model Package, 3, 4amplifiers

GaAs IC, 38transconductance, 36

analysisAC, 15DC operating point, 6–9DC transfer, 10noise, 30transient, 13, 24, 27

attributesdefined, 6PARNAM, 18

axesformatting, 23logarithmic, 34

B

binary notation, 28bit keyword, 22bitwise input, 22bus keyword, 28

C

C, key letter, 8capacitor, 8charts

expand/collapse operations, 11new, 22

collapsing charts, 11


Index

convergence, 3, 25current tolerance, 34

D

.dc command, 11DC operating point analysis, 8dec keyword, 16decimal notation, 28deftables keyword, 32dialogs

Simulation Manager, 9Trace Properties, 11

digital circuit example, 21DLL, 39DxDesigner

attributes, 6subcircuits, 18

E

.ends command, 19evaluation methods

compared, 32direct model, 32table-based, 32

examplesAC Analysis, 15–17DC Operating Point Analysis, 6–9DC Transfer Analysis, 10–12Direct Model Evaluation, 32MOS Transconductance Amplifier, 36–37Noise Analysis, 30–31Subcircuits, 18–20Transient Analysis, 13–14, 21–23Transient Analysis, Powerup Mode, 24–26Transient Analysis, Preview Mode, 27–29Transistor Subthreshold Behavior, 33–34Voltage Controlled Ring Oscillator, 39Wide-Band GaAs IC Amplifier, 38

expanding charts, 11export netlist, 7external models, 39


Index

F

frequencysweeping, 16

G

GaAs amplifier, 38.gridsize command, 34

H

hexadecimal notation, 28

I

.ic command, 20

.include command, 8initial conditions, 20, 24input, previewing, 27instance

subcircuit, 19–20

K

key letter, 8C, 8M, 8X, 19

L

lin keyword, 11logarithmic sweep, 16


Index

low-current simulation, 34, 37

M

M, key letter, 8macromodels, 4, 39.model command, 8model evaluation

direct, 32model files, 8models, external, 39MOSFET

regions of operation, 33subthreshold simulation, 33T-Spice definition, 8

N

netlist, exporting, 7noise analysis, 30.noise command, 30

O

octal notation, 28.op command, 8.options command, 32, 34, 37oscillator, voltage-controlled, 39output files

opening, 9

P

parameterspassing through hierarchy, 18subcircuit, 19sweeping, 10–11

PARNAM, 18piecewise linear, 14


Index

powerup keyword, 24, 25preview keyword, 27.print command, 10, 16.print noise command, 30PWL keyword, 14

R

resolution, 34ring VCO, 39run simulation, 9

S

semiconductor device simulation, 33simulation commands

.ac, 16

.dc, 11

.ends, 19

.gridsize, 34

.ic, 20

.include, 8

.model, 8

.noise, 30

.op, 8

.options, 32, 34, 37

.print, 10, 16

.print noise, 30

.subckt, 19–20

.tran, 14

.tran/powerup, 24–25

.tran/preview, 27, 28

.vector, 28simulation, running, 9sin keyword, 28s-parameters, 38speed, 3stability, problems with, 25subcircuit, 18–20

definition, 19–20described, 18DxDesigner, 18instance, 19–20parameters, 19

.subckt command, 19–20subthreshold

behavior


Index

transconductance amplifier, 36transistor, 33

modeling, 36region, 33

sweeps, 10frequency, 16linear, 11logarithmic, 16

symbolsattributes, 6, 18

T

tables, 3, 8tolerance, current, 34traces

loading, 22order of, 22properties, 11

.tran command, 14

.tran/powerup command, 24–25

.tran/preview command, 27, 28transconductance amplifier, 36transfer analysis, 10transient analysis, 21

default mode, 13op mode, 13powerup mode, 24, 25preview mode, 27

transition region, 33T-Spice

accuracy, 4advantages, 3–4convergence, 3speed, 3

U

unstable circuits, 25

V

variables


Index

sweeping, 10–11.vector command, 28voltage source

bit, 22, 28bus, 28DC, 8piecewise linear, 14, 27polynomial, 38repeating bit, 28sinusoidal, 28voltage-controlled, 38

W

W-Editadd chart, 22axes, formatting, 22, 34traces, 11, 22

X

X key letter, 19

T-Spice Pro 12 Examples Guide 47

Credits

Software Development

Ken Van de Houten

Quality Assurance

Luba Gromova Lena NeoKen Van de Houten

Documentation

Judy Bergstresser Ken Van de Houten

64607370 t spice examples

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