64-bit z/architecture overview - part i: application facilities - kcats.org
TRANSCRIPT
Copyright IBM Corporation 2000, 2001
64-bit z/Architecture Overview Part I: Application Facilities
zSeries
Bob Rogers
IBM Corporation
1-845-435-1647
SHARE
Nashville, TN
Session 2824
zSeries
Copyright IBM Corporation 2000, 2001
Architecture Elements
Part I - Non-Authorized Facilities
Addressing Modes
General Purpose Registers
Non-modal and modal Instructions
Addressing Mode Switching Instructions
New Instructions in Support of 64-bit
New Immediate Instructions
Some other Interesting Instructions
Extended Translation Facility 2
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Copyright IBM Corporation 2000, 2001
The Style of z/Architecture
z/Architecture has extended ESA/390 to 64-bit in a manner somewhat different than other platforms. For example, in PowerPC architecture, 64-bit addressing and 64-bit operation are inseparable. When running in 64-bit mode, all register operations also have 64-bit definitions. The ability to switch between modes is restricted to the supervisor.
The z/Architecture definition separates the control of 64-bit addressing mode from 64-bit operations. This style of definition allows software to be extended to 64-bit in an evolutionary manner. 32-bit and 64-bit operations are supported in 24-, 31- and 64-bit addressing mode. Any program can switch between addressing modes and intermix 32-bit and 64-bit operations.
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Addressing Modes
z/OS Apparent PSW
31-bit IA
PSW bits 31 and 32 designate addressing mode.The 31-bit addressing mode bit is on in 64-bit mode.
A PSW indicating 64-bit addressing mode will seem to
indicate 31-bit mode to "unknowing" programs
Address generation uses 64-bit Base and Index values and produces 64-bit addresses.
Effective addresses are truncated to 31 or 24 bits in 31-bit or 24-bit addressing mode.
Actual PSW64-bit instruction address
Addressing mode bits:00 = 24-bit mode
01 = 31-bit mode
11 = 64-bit mode
31-32
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Renaming the bits
The z/Architecture is a 64-bit architecture with several types of 64-bit registers and areas, such as 64-bit General Purpose Registers. The numbering of the bits for these entities is change to be 0 to 63. This may cause confusion when dealing with some of the compatible aspects of the architecture. For example, The ESA/390 Load instructions sets bits 0-31 of a General Purpose Register. In z/Architecture, the Load instructions sets bits 32-63, due to the renumbering of the bits. To ease understanding, sometimes the ESA/390 bit positions will also be provided in braces. Bit positions are usually designated after a dot. For example:
LR R1,R2 sets R1.32-63{0-31} from R2.32-63{0-31}
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General Purpose Registers
0 6364-bit General Purpose Register
32{0} 63{31}
32-bit GPR
The register is treated as 64-bits for:
Address generation in 64-bit mode
GPR operands of non-modal 64-bit instructions
GPR operands of modal instructions in 64-bit mode
The register is treated as 32-bits for:
Address generation in 24/31-bit modes (so it seems)
GPR operands of non-modal 32-bit instructions
GPR operands of modal instructions in 24/31-bit modes
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Copyright IBM Corporation 2000, 2001
Address Generation
Address generation takes the value contained in a 64-bit base register plus (optionally) the value contained in a 64-bit index register plus the value of the 12-bit displacement in the instruction.
The result is then truncated on the left depending upon the current addressing mode.
In 24-bit mode, the leftmost 40 bits are set to zeros.
In 31-bit mode, the leftmost 33 bits are set to zeros.
In 64-bit mode, the 64-bit address is not truncated.
0 63
64-bit General Purpose Register
Base Register +0 63
64-bit General Purpose Register
Index Register + Displacement
0 11
Op R1,D2(X2,B2) [this is an RX example]
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Copyright IBM Corporation 2000, 2001
Since z/Architecture allows the intermixing of addressing modes and operand precisions, care was taken to ensure that old 32-bit programs could not inadvertently destroy register information which new 64-bit programs assumed to be preserved.
The high-order halves of the 64-bit registers are visible only in 64-bit mode or when executing new instructions. When executing in 24- or 31-bit addressing mode and issuing only instructions which are defined in ESA/390, the high-order 32-bits of the 64-bit registers are opaque.
Old programs, which do not save/restore the full 64-bit registers, cannot unknowingly alter the contents of the high-order halves of the registers.
A "meta rule" of z/Architecture
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Modal vs Non-Modal Instructions
The term Non-Modal applies to instructions which perform the same operation regardless of addressing mode.
For these instructions, addressing mode is only used during storage operand address generation.
E.g. L always loads R1.32-63{0-31} from D2(X2,B2).0-31
The term Modal is applied to instructions for which the operation is different in 64-bit addressing mode than in 24-/31-bit mode.
Specifically, the width of some or all register operands depends upon addressing mode.
E.g. LA set R1.32-63{0-31} or R1.0-63 depending on mode.
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Non-modal instructions (32)
Storage Operand
ESA/390 32-bit operand instructions which behave as in ESA/390 - regardless of addressing mode.
Bits 0-31 of the 64-bit GPRs are unexamined and unmodified
Examples: LR, AR, ALR, L, A, AL
32-bit Register
32-bit Register
R1
R2
D2(X2,B2)
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Non-modal (32) Example
Storage Operand
ADD (32) takes the value of a fullword in storage and arithmetically adds it to the contents of the low-order 32-bits of a general purpose register.
The high-order 32-bits of the general purpose register are neither interrogated nor modified.
The operation is the same in all addressing modes.
32-bit Register
A R1,D2(X2,B2)
R1
D2(X2,B2)
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Copyright IBM Corporation 2000, 2001
64-bit GPR
Storage Operand
New 64-bit operand instructions operate on 64-bit operands - regardless of addressing mode.
All 64-bits of the first operand register are modified
The second operand is also 64-bits wide
Examples: LGR, AGR, ALGR, LG, AG, ALG
Non-modal instructions (64)
64-bit Register Operand
R1
R2
D2(X2,B2)
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64-bit GPR
Storage Operand
ADD (64) takes the value of a 8-bytes in storage and arithmetically adds it to the contents of the full 64-bit general purpose register.
The entire 64-bit general purpose register is both input to and output of the operation .
The operation is the same in all addressing modes.
Non-modal (64) Example
AG R1,D2(X2,B2)
R1
D2(X2,B2)
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Copyright IBM Corporation 2000, 2001
64-bit Analogs of ESA/390 Instructions
AG[R]
AGHI
ALG[R]
NG[R]
BCTG[R]
BXHG
BXLEG
BRCTG
BRXHG
LG[R]
LGH
LGHI
LMG
LNGR
LPGR
MGHI
MSG[R]
OG[R]
BRXLG
CG[R]
CSG
CDSG
CGHI
CLG[R]
CVBG
CVDG
XG[R]
SLAG
SLLG
SRAG
SRLG
SG[R]
SLG[R]
STG
STMG
Non-priviledged General Purpose Instructions
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64-bit Analogs of ESA/390 Instructions
CEGR
CDGR
CXGR
CGER
CGDR
CGXR
LCTLG
LURAG
STCTG
STURG
TRACG
CEGBR
CDGBR
CXGBR
CGEBR
CGDBR
CGXBR
Hex Floating Point Binary Floating Point Privileged Operations
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Copyright IBM Corporation 2000, 2001
New Instructions w/ 64-bit Analogs
Load Reversed - LRV, LRVR
Multiply Logical - ML, MLR
Divide Logical - DL, DLR
Add Logical w/ Carry - ALC
Subtract Logical w/ Borrow - SLB
Store Reversed - STRV
Rotate Left Single Logical - RLL
LRVG, LRVGR
MLG, MLGR
DLG, DLGR
ALCG
SLBG
STRVG
RLLG
Non-modal 32-bit Instructions Non-modal 64-bit
* All these 32-bit non-modal instructions are added to ESA/390
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Copyright IBM Corporation 2000, 2001
64-bit General Purpose Register
Storage Operand
New instructions operate on 32-bit second operands into 64-bit first operands - regardless of addressing mode.
The 32-bit second operand is internally extended to 64-bits before the operation is performed
All 64-bits of the first operand register participate
E.g. LGFR, AGFR, ALGFR, LGF, AGF, ALGF
Non-modal instructions (64/32)
32-bit Reg Operand
sign propagation or
padding with zeros
sign propagation or
padding with zeros
R1
R2
D2(X2,B2)
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Copyright IBM Corporation 2000, 2001
64-bit General Purpose Register
Storage Operand
ADD (64/32) takes the value of a fullword in storage, propagates the sign to extend it to 64-bits, and then arithmetically adds the sign-extented value to the contents of the 64-bit general purpose register.
The entire 64-bit general purpose register is both input to and output of the operation .
The operation is the same in all addressing modes.
Non-modal (64/32) Example
AGF R1,D2(X2,B2)
sign propagation
R1
D2(X2,B2)
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Copyright IBM Corporation 2000, 2001
64/32 Instructions
AGF[R]
ALGF[R]
CGF[R]
CLGF[R]
LGF[R]
LPGFR
LNGFR
MSGF[R]
SGF[R]
SLGF[R]
64/32 Analogs of ESA/390 Instructions
Other 64/32 InstructionsLLGF[R] LLGT[R]
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Copyright IBM Corporation 2000, 2001
Modal instructions
Instructions which operate differently depending upon addressing mode. Usually the difference is the width of register operands.
e.g. LA, MVCL, TRT, BASR, BASSM
Note: instructions like BCR are not considered modal because address generation naturally truncates the address taken from the register according to current addressing mode.
64-bit mode
64-bit General Purpose Register
24/31-bit mode
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Copyright IBM Corporation 2000, 2001
Modal Instruction Example
Load Address produces a result dependent upon the current addressing mode.
24-/31-bit mode: a 24-/31-bit address is placed in R1.40-63{8-31} /R1.33-63{1-31} and R1.32-39{0-7}/R1.32{0} is set to zero. R1.0-31 remains unchanged.
64-bit mode: a 64-bit address is placed in R1.0-63.
64-bit mode
64-bit General Purpose Register
24/31-bit modeLA R1,D2(X2,B2)
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Copyright IBM Corporation 2000, 2001
Modal Non-privileged Instructions
Branch and Link (BAL, BALR)
Branch and Save (BAS, BASR)
Branch and Save and Set Mode
Branch Relative and Save
Branch Relative and Save Long
Checksum1
Compare and Form Codeword2
Compare Logical Long
Compare Logical Long Extended1
Compare Logical String
Compare Until Substring Equal1
Convert Unicode to UTF-81
Convert UTF-8 to Unicode1
Load Address
Load Address Extended
Load Address Relative Long
Load Real Address (LRA only)
Move Long
Move Long Extended1
Move String
Search String
Translate Extended1
Translate and Test
Update Tree
1The length registers are 32 bits in 24/31-bit mode and 64 bits in 64-bit mode2See the Principle of Operation for mode-dependent differences
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Copyright IBM Corporation 2000, 2001
Addressing Mode Switching
There are 3 new instructions which change addressing mode without branching:
Set Addressing Mode to 24-bit (SAM24)
Set Addressing Mode to 31-bit (SAM31)
Set Addressing Mode to 64-bit (SAM64)
There are 2 instructions which change addressing mode and branch:
Branch and Save and Set Mode (BASSM)
Branch and Set Mode (BSM)
* SAM24 and SAM31 are added to ESA/390
zSeries
Copyright IBM Corporation 2000, 2001
Mode Switching Branches
64-bit General Purpose Register
32{0} 63{31}
63 32 Amode to switch to
0 0 24-bit mode
0 1 31-bit mode
1 x 64-bit mode
In all modes, BASSM and BSM switch addressing mode based on the contents of R2.63 and R2.32.
In 64-bit mode:BASSM sets a 64-bit return address with R1.63{31}=1.
BSM sets R1.63{31)=1 (when R1 is not 0).
BALR and BASR do not set R1.63{31}=1
In 24/31-bit mode, these instructions set a return address as in ESA/390, and leave R1.0-31 unchanged.
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Copyright IBM Corporation 2000, 2001
New Instructions in support of 64-bit
Test Addressing Mode
Load Logical Thirty-one
Load/Store Multiple High
Load/Store Multiple Disjoint
Load Logical (word, halfword and character)
Insert Characters Under Mask High
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Copyright IBM Corporation 2000, 2001
Test Addressing Mode -TAM
Test Addressing Mode sets the condition code based on the current addressing mode:
CC=0: 24-bit mode
CC=1: 31-bit mode
CC=3: 64-bit mode
PSW
64-bit instruction address
Addressing mode bits: 00 = 24-bit; 01 = 31-bit; 11 = 64-bit
Condition Code
* TAM is added to ESA/390
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Copyright IBM Corporation 2000, 2001
Load Logical Thirty One - LLTG[R]
Storage Operand
Load Logical Thirty One (LLTG, LLTGR) takes the low-order 31-bits of the 32-bit second operand and place them in bits R1.33-63, and set bits R1.0-32 to zeros.
It produces a clean 64-bit address from a 31-bit address, regardless of addressing mode.
31-bit Address
32-bit Register
33 bits of 0 padding
LLTG
LLTGR
R1
R2
D2(X2,B2)
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Copyright IBM Corporation 2000, 2001
Load/Store Multiple High - LMH, STMH
Load Multiple High (LMH) works like LM except that it loads into the high-order 32-bits of the 64-bit registers.
Store Multiple High (STMH) works like STM except that it stores from the high-order 32-bits of the 64-bit registers.
Storage Operand
Low-order 32-bitHigh-order 32-bit
Storage Operand
High-order 32-bit
- - - -
- - - -
D2(B2)
R1 R3
Low-order 32-bit
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Copyright IBM Corporation 2000, 2001
Load Multiple Disjoint - LMD
Load Multiple Disjoint (LMD) works like a Load Multiple plus a Load Multiple High.
It can be used when the registers could not be stored in a single contiguous area, as on a call from an old 31-bit program to a new 64-bit one.
It's performance is not better than LM plus LMH
Storage Operand
Low-order 32-bitsHigh-order 32-bits
Storage Operand
High-order 32-bits
- - - -
- - - -
D2(B2)
R1 R3
Low-order 32-bits
Storage Operand Storage Operand- - - -
D4(B4)
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Load Logical - LLGF[R]
Storage Operand
The 32 bit (or low-order 32 bits for LLGFR) of the second operand are loaded into the low-order 32 bits of the first operand register.
The high-order 32 bits of the first operand register are set to zeros.
Low-order 32 bits
32-bit Register
000000000000000000000000000000000R1
R2
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Copyright IBM Corporation 2000, 2001
Load Logical Halfword- LLGH
Storage Operand
The 16 bit of the second operand are loaded into the low-order 16 bits of the first operand register.
The high-order 48 bits of the first operand register are set to zeros.
Low-order 16 bits
0000000000000000000000000000000000000000000000000R1
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Load Logical Character- LLGC
Storage Operand
The 8 bits of the second operand are loaded into the low-order 8 bits of the first operand register.
The high-order 56 bits of the first operand register are set to zeros.
Low-order 8 bits
000000000000000000000000000000000000000000000000000000000R1
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Copyright IBM Corporation 2000, 2001
Insert and Store Characters Under Mask High (ICMH and STCMH) work exactly like ICM and STCM except that they operate on the 4 high-order bytes of the first operand register.
Insert/Store Characters Under Mask High
R1
D2(B2)
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Copyright IBM Corporation 2000, 2001
New Immediate Instructions
Load Logical Immediate
Insert Logical Immediate
AND Immediate
OR Immediate
Test Under Mask (High/Low)
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Copyright IBM Corporation 2000, 2001
The Load Logical Immediate Instructions (LLIHH, LLIHL, LLILH, LLILL) load an immediate 16-bit value into any of the 4 halfwords of a 64-bit register.
The other 3 halfwords are cleared to zeros.
Load Logical Immediate - LLIxx
OP R1 Immediate
R1
LLIHH LLIHL LLILH LLILL
Instruction
0 16 32 48 63
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The Insert Logical Immediate Instructions (ILIHH, ILIHL, ILILH, ILILL) insert an immediate 16-bit value into any of the 4 halfwords of a 64-bit register.
The other 3 halfwords are left unchanged.
Insert Logical Immediate - ILIxx
OP R1Immediate
R1
ILIHH ILIHL ILILH ILILL
Instruction
0 16 32 48 63
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Copyright IBM Corporation 2000, 2001
The AND Immediate Instructions (NIHH, NIHL, NILH, NILL) logically AND an immediate 16-bit value into any of the 4 halfwords of a 64-bit register.
The other 3 halfwords are left unchanged.
AND Immediate - NIxx
OP R1Immediate
R1
NIHH NIHL NILH NILL
Instruction
0 16 32 48 63
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Copyright IBM Corporation 2000, 2001
The OR Immediate Instructions (OIHH, OIHL, OILH, OILL) logically OR an immediate 16-bit value into any of the 4 halfwords of a 64-bit register.
The other 3 halfwords are left unchanged.
OR Immediate - OIxx
OP R1Immediate
R1
OIHH OIHL OILH OILL
Instruction
0 16 32 48 63
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Copyright IBM Corporation 2000, 2001
The Test Under Mask High/Low Instructions (TMHH, TMHL, TMLH, TMLL) tests the 16 bits of any of the 4 halfwords of a 64-bit register against a 16-bit immediate mask.
The condition is set like with Test Under Mask (TM).
Test Under Mask High/Low - TMxx
OP R1Immediate
R1
TMHH TMHL TMLH TMLL
Instruction
0 16 32 48 63
* TMLH and TMLL exist in ESA/390 as TMH and TML
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Copyright IBM Corporation 2000, 2001
New Long Relative
Instructionsb
Branch Relative on Condition Long (BRCL) is like BRC but has a 32-bit signed immediate value.
Branch Relative and Save Long (BRASL) is like BRAS but has a 32-bit signed immediate value.
Load Address Relative Long (LARL) computes the address as would BRCL or BRASL, but instead of branching, it places the address in the first operand register. Note: the immediate designates a number of
halfwords. Therefore, LARL can only be used to load the address on a halfword boundary.
*BRCL and BRASL are added to ESA/390
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Copyright IBM Corporation 2000, 2001
Rotate Left Single Logical -RLL/RLLG
The value in R3 is rotated to the left and the result is stored in R1. R3 is unchanged.
The rightmost 6 bits calculated from D2(B2) determines the number of positions to rotate
RLL and RLLG are both model instructions
For RRL, bits 0-31 of R1 and R3 are unexamined and unchanged.
RLL R1,R3,D2(B2)
RLLG R1,R3,D2(B2)
* RLL is added to ESA/390
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Load/Store Reversed
The low-order 2, 4 or 8 bytes of a register are loaded or stored in byte-wise reverse order. This is an assist in converting between big/little endian.
For Load Reversed, the high-order portion of the register is remain unchanged.
For Load Reversed of 4 or 8 bytes, the second operand can be a register (LVR, LVGR)
STRVH R1,D2(B2) STRV R1,D2(B2) STRVG R1,D2(B2)
LRVH R1,D2(B2) LRV R1,D2(B2) LRVG R1,D2(B2)
* LRVH, LRV, LRVR, STRVH, STRV are added to ESA/390
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Copyright IBM Corporation 2000, 2001
Add Logical with Carry (ALC, ALCR, ALCG, ALCGR) and Subtract Logical with Borrow (SLB, SLBR, SLBG, SLBGR) use the condition code set by a previous instruction to participate in the operation so that arithmetic can be performed on large integers.
Multiply Logical (ML, MLR, MLG, MLGR) and Divide Logical (DL, DLR, DLG, DLGR) treat their operands as unsigned numbers, again facilitating arithmetic on very large integers.
New Logical Arithmetic Instructions
*ALC, ALCR, SLB, SLBR, ML, MLR, DL and DLR are added to ESA/390
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Copyright IBM Corporation 2000, 2001
Divide Single (DSG, DSGR, DSFG, DSGFR) is like Divide except that the 64-bit dividend is in the odd 64-bit register only rather than in both even and odd 32-bit registers. The quotient and remainder are both 64 bits.
DSG and DSGR divide a 64-bit R1+1 by a 64-bit second operand. The 64-bit quotient is placed in R1+1 and the 64-bit remainder is placed in R1
DSGF and DSGFR divide a 64-bit R1+1 by a 32-bit second operand. The 64-bit quotient is placed in R1+1 and the 64-bit remainder is placed in R1
Divide Single
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Extended Translation Facility 2
The facility consists of 11 instructions which facilitate the manipulation of ASCII and Unicode data are added to z/Architecture.
They augment Extended Translation Facility 1 (Translate and Test Extended, Translate ASCII to UTF-8 and Translate UTF-8 to ASCII) which are available on G5/G6 and z900 processors.
This facility is not available at initial GA of z900, but will be added at GA2.
Bit 16 of the list produced by Store Facility List indicates the presence/absence of this facility.
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Copyright IBM Corporation 2000, 2001
Move/Compare Long Unicode
Move Long Unicode (MVCLU) is like MVCLE except that it moves pairs of bytes rather than single bytes. It only operates on an even number of bytes.
Compare Long Unicode (CLCLU) is like CLCLE except that it compare pairs of bytes rather than single bytes. It only operates on an even number of bytes.
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Copyright IBM Corporation 2000, 2001
Pack/Unpack ASCII
Pack ASCII (PKA) converts ASCII numeric
characters to packed decimal format.The low-order 4-bits of each byte are treated as a decimal digit. The result is always positive (sign=1100)
The first operand length is 16; second is 1 to 32
Unpack ASCII (UNPKA) converts packed decimal
to ASCII characters.Each digit is extended on the left with 0011 binaryThe sign is indicated by condition code settingThe second operand length is 16; first is 1 to 32
Digits are not checked for validity and results are unpredictable if the operands overlap.
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Copyright IBM Corporation 2000, 2001
Pack/Unpack Unicode
Pack Unicode (PKU) converts Unicode Basic Latin
numerics to packed decimal format.The low-order 4-bits of each double-byte are treated as a decimal digit. The result is always positive (sign=1100)
The first operand length is 16; second must be even
Unpack Unicode (UNPKU) converts packed decimal
to Unicode Basic Latin characters.Each digit is extended on the left with 003 hexThe sign is indicated by condition code settingThe second operand length is 16; first must be even
Digits are not checked for validity and results are unpredictable if the operands overlap.
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Copyright IBM Corporation 2000, 2001
Test Decimal - TP
Test Decimal (TP) tests for valid decimal digits and valid sign codes. The results of the test are reported in the condition code.
CC=0: all digits and sign validCC=1: sign invalidCC=2: at least one digit invalidCC=3: sign invalid and at least one digit invalid
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Copyright IBM Corporation 2000, 2001
Translate One to One - TROO
Translate One to One (TROO) translates from a single-byte code to another single-byte code
The single-byte characters of the second operand are used to select single-byte function characters from a table pointed to by general purpose register 1The function characters are compared against a single-byte character in general purpose register 0. If the function character equals this value, the operation terminates. If not, the function character is moved to the first operand locationThe length of the second operand is in register R1+1The second operand is not modifiedThe length of the table is 256 bytes
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Translate One to Two - TROT
Translate One to Two (TROT) translates from a single-byte code to a double-byte code
The bytes of the second operand are used to select double-byte function characters from a table pointed to by general purpose register 1The function characters are compared against a double-byte character in general purpose register 0. If the function character equals this value, the operation terminates. If not, the function character is moved to the first operand locationThe length of the second operand is in R1+1The second operand is not modifiedThe length of the table is 512 bytes
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Translate Two to One - TRTO
Translate Two to One (TRTO) translates from a doube-byte code to a single-byte code
The double-byte characters of the second operand are used to select single-byte function characters from a table pointed to by general purpose register 1The function characters are compared against a single-byte character in general purpose register 0. If the function character equals this value, the operation terminates. If not, the function character is moved to the first operand locationThe length of the second operand is in register R1+1The second operand is not modifiedThe length of the table is 65,536 bytes (64K)
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Translate Two to Two - TRTT
Translate Two to Two (TRTT) translates from one double-byte code to another double-byte code
The double-bytes of the second operand are used to select double-byte function characters from a table pointed to by general purpose register 1The function characters are compared against a double-byte character in general purpose register 0. If the function character equals this value, the operation terminates. If not, the function character is moved to the first operand locationThe length of the second operand is in R1+1The second operand is not modifiedThe length of the table is 132,072 bytes (128K)