H8 Peek(H8S, H8SX, 300H Tiny, SLP)

February 2005

December, 2004 2

H8/300

H8/300H

H8S

32-bit

16-bit

8-bit

H8SX

X : eXtension , eXpansion

Original Core

16 MB Linear AddressingEnhanced external mode

1 Instruction/1 state

Enhanced Bus width to 32bit

fmax: 16MHz

fmax: 50MHz

Bus:8bit(64kB)

Bus:16bit(16MB)

Bus:32bit(4GB)

fmax: 33MHz

fmax: 25MHzBasic instruction execution state

Data Bus widthNumber of

instructions

Address space

300 300H H8S H8SX

8bit 32bit

57 62 69 87

64KB 4GB16MB

16 bit

2 state 1 state

1) Superior CPU performance at the same frequency 2) Superior Instruction code efficiency 3) H8 devices are compatible at the object code level

H8 CPU Core Road MapH8 CPU Core Road Map

Number of addressing modes 8 8 8 11

December, 2004 3

H8/H8S/H8SX Family FeaturesProductsSeries

Features Target segments

Maximumfrequency

ProcessTechnology

Development& Sales strategy

H8S/2600

H8S/2300

H8S/2200

H8S/2100

H8S/300H

32bit, CISC

16bit,MultiplierS-DRAM I/F

16 bit, standard

16bit, USB2.0

Printer

Projector,Camera, POSPOS,Card readerKBC, PC server

ODD,Motor control

f=33MHz => 48MHz

f=33MHz

f=25MHz

0.18um(F-MONOS)

0.5 - 0.18um

0.8 - 0.18um

A.S.S.P.

A.S.S.P.=Application Specific Standard Products

Standard Products

A.S.S.P. ,SLP

IKAP- 4,IPMI

Standard => A.S.S.P.

Printer, ODDAuto

A.S.S.P.

H8S/2500

H8SX

16bit, KBC

16bit, Popular

16 bit, CAN, IE

0.5 - 0.18um(F-MONOS)

0.18um

0.5 - 0.35um

0.5 - 0.18um

f=24MHz

f=33MHz

f=25MHz

f=25MHz

Car Audio A.S.S.P.

f=25MHzH8S/2400 16 bit, MultiplierDDC1/2B 0.18um Monitors A.S.S.P.

December, 2004 4

H8S/2168 Series

115 I/O

8-bit D/A (2ch)10-bit A/D (8ch)

14-bit PWM (4ch)

DTC

LPC (3ch)

RAM, 40kB

Flash256KB

H8S/2000 CPU

WDT (2ch)

16bit FRT (1ch)

8-bit PWM (16ch)

8bit TMR x4 16bit TMRx1

I2C (6ch)

SCI x2 (Smart Card I/F)

H-UDI

Specific functions

• High performance and low power– Maximum speed: 33MHz– Operating voltage 3.0 to 3.6V

• Large on chip memory– Flash: 256KB: H8S/2168– Flash: 384KB: H8S/2167– Flash: 512KB: H8S/2166

• 6-channel I2C serial bus• 3-channel Low Pin Count (LPC) Interface

– Each channel supports I/O read/write mode

• 3-channels of SCI• 16/24-bit external bus interface• Rich set of timers • Analog Interface• Package: TQFP-144

Block DiagramFeatures

December, 2004 5

Features•H8S/2000CPU: Single Chip mode - 24 MHz/3.0 V to 3.6 V (when the USB is used.) - 24 MHz/3.0 V to 3.6 V, 16 MHz/2.7 V to 3.6 V (when the USB is not used.) - 6 MHz/2.4 V to 3.6 V (H8S/2211M only, when the USB is not used.) • Built-in memory - 128 KB/12 KB (H8S/2212: Flash) - 64 KB/8 KB (H8S/2211: Flash, MASK) - 32 KB/4 KB (H8S/2210M: MASK) • USB Ver2.0 Full speed Function: 12 Mbps - Transfer mode: 3 modes - Endpoints: 4 points (Control x 1, Bulk x 2, Interrupt x 1) - FIFO Total 456 bytes (MAX: 64 bytes) • RTC (Real Time Clock) • E-10A support (H8S/2212F, 2211F only) • Package (FP-64) - FP-64E (10 x 10 mm, 0.5 mm pitch) max 24 MHz

USB

DMAC

ROM

RAM

WDT

TPU x 3 ch

RTC

H8S/2000 CPU

Interrupt cotroller

SCI x 2 ch(Smart Card I/F

function)

A/D converter x 6 ch

PLLOscillator(system

clock)

Oscillator(subclock)

48 MHz

32 kHz

Block Diagram

: Special functions

H8S/2212 Group Overview

December, 2004 6

- Built-in flash memory -

Group Block Diagram

* : F-ZTAT Version with 25 MHz/3.3 V Version.

Features • Low-voltage and high-speed operation - 3 V/20 MHz, 3.3 V/25 MHz operation - Minimum instruction execution time: 50 ns/40 ns

• Various lineup - 512 KB /8 KB - 384 KB/32 KB - -/32 KB - 256 KB/8 KB - 128 KB/8 KB - 32 KB/8 KB - -/8 KB - -/4 KB - -/4 KB

• Upwardly pin compatible with H8S/2655, 2350, 2355 and 2357 Group - QFP-128, TQFP-120

• Supports on-chip debugging function (E10A) - H8S/2329EF

H8S/2326F*

H8S/2329F*, 2329EF*H8S/2329BF*(Shrink Version)H8S/2324SH8S/2328BF*, 2328H8S/2327H8S/2323H8S/2322RH8S/2321 (DRAM I/F, DMAC deleted )H8S/2320

H8S/2000 CPU ROM RAM

Bus controller

Interrupt controller

A/D x 8 ch

D/A x 2 ch

DMAC x 4 ch

PPGWDT

16-bit timer x 6 ch

8-bit timer x 2 ch

SCI x 3 ch

DTC (85ch)

H8S/2329 and H8S/2328 Group Overview

December, 2004 7

Block Diagram

- F-ZTAT Version with enhanced serial communications function and analog functions -

Features • Low-voltage high-speed operation - 3.0 V to 3.6 V/33 MHz - Minimum instruction execution time: 30 ns • Enhanced serial communications function and analog functions - SCI x 5 ch (I2C x 2 ch optional) - A/D x 16 ch, D/A x 6 ch • Built-in SDRAM interface - H8S/2378RF, 2377RF, 2375R, 2373R • Supports on-chip debugging function (E10A) - H8S/2378F, 2378RF, 2377F, 2377RF, • Lineup - 512 KB/32 KB: H8S/2378F, 2378RF - 384 KB/24 KB: H8S/2377F, 2377RF - 384 KB/30 KB: H8S/2376F*1

- 256 KB/16 KB: H8S/2375, 2375R - -/16 KB: H8S/2373, 2373R • Multiple-pin package - LQFP-144

*1: Reduced peripheral functionsNote: Not pin-compatible with the H8S/2338 and 2678 Group H8S/2378F and 2378RF have VCL pin.

H8S/2376F: No EXDMAC, no DMAC, no PPG, no DRAMI/F, D/A x 4 chH8S/2375, 2373 and 2373R : No EXDMAC, D/A x 2 ch

EXDMAC x 2 ch

H8S/2000 CPU ROM RAM

Bus controller

Interrupt controller

A/D x 16 ch

D/A x 6 ch

DMAC x 4 ch

PPGWDT

16-bit timer x 6 ch

8-bit timer x 2 ch

SCI x 5 ch

DTC (85 ch)

PLL

I2C x 2 ch(Option)

H8S/2378 Group Overview F-MONOSF-MONOS0.18um0.18um

December, 2004 8

Downsizing of Flash Memory (Example: 512kB Flash memory)

0.35um0.35um(H8/3052F)(H8/3052F)

0.18um0.18um(H8/3069F)(H8/3069F)

MONOSMONOS0.18um0.18um

(H8S/2378F)(H8S/2378F)

100100％％ 5252％％100100％％

2222％％4141％％

24.84 mm2

(12.42 mm2 × 2)12.94 mm2 5.37 mm2

December, 2004 9

December, 2004 10

Block Diagram

: Function improvements from the H8S/2678 Group

Features

• 33 MHz (3.0 V to 3.6 V)

• Minimum instruction-execution time - 30 ns (33 MHz/3.3 V)

• ROMless Version

- H8S/2674R (-/32 k)

• Internal SDRAM interface - 64-Mbit direct connection interface

- Hold times are assured by the dedicated

SDRAM φ - Includes a clock suspension function

• Functional improvement module - A/D registers: 4 → 8 (more useful)

• Package - LQFP-144

- Includes an on-chip SDRAM interface compatible with that of H8S/2678 Group products -

H8S/2600 CPU

Multiplier

BuscontrollerInterruptcontroller

DMAC x 4 ch

D/A x 4 ch

EXDMAC x 4 ch

SCI x 3 ch

16-bit timer x 6 ch

8-bit timer x 2 ch

WDT

DTC

PPG

RAM

A/D x 12 ch

H8S/2678R Group Overview

December, 2004 11

High performanceHigh performanceH8SX CPU CoreH8SX CPU Core

Improved Improved system throughputsystem throughput

1 cycle access with 32bit Bus

VBR (Vector Base Register)

Reduced powerReduced power 1mA/MHz, 0.18μm and new Flash process

SBR (Short address Base Register)

Reduced instruction fetches

50MHz Performance

Address/Data multiplex I/O I/F

Big/Little endian access

Products Concepts Products Concepts Products FeatureProducts Feature

High Performance multiplier & divider

Reduced code sizeReduced code size New instructions and addressing modes

H8SX series products concepts & featuresH8SX series products concepts & features

December, 2004 12

H8SX CPU@50MHz

Instruction FIFO(16bit x 8)

32bit Divider/Multiplier

BSC

Peripheral BUS(16bit)

External BUS(8bit/16bit)

PORT

Timer

DMAC DTC

SCIOtherfunction

EXDMACBuffer(32Byte)

SBR

H8SX microcomputer

RAMFlash

<Interrupt response time><Interrupt response time>Improved 1.4usec/1 interrupt by VBR :30% DOWN

<1cycle access with 32bit Bus><1cycle access with 32bit Bus>

<New Instruction & function><New Instruction & function>Easily analyze the header information from network.Big/Little endian can automaticallyconvert.

<Easy & early I/O access by SBR><Easy & early I/O access by SBR>Reduce code size : 30% DOWNimproved performance: 20% UP

Internal BUS(32bit)

VBR

<High-speed execution of <High-speed execution of instruction>instruction>

Network(USB/Ether)SDRAM

ASIC(Image/audio)

<Burst access between SDRAM and I/O by EXDMAC><Burst access between SDRAM and I/O by EXDMAC>

H8SX advantage points for embedded systemsH8SX advantage points for embedded systems

December, 2004 13★Mass production　★★ :Working Sample　☆ :Under development

H8SX/1527F

★★Automotive(Air bag)

H8SX products Line-up

ROM/RAMevolution

Higher Operation frequency

Enhanced peripheral module

Keyword to next generation

H8SX

H8SX/1657FH8SX/1657F H8SX/16xxH8SX/16xx

Large capacity Flash memory : Over 1MB

Pin compatible with H8SX/1650Added DMAC

★★ ☆

Operation frequency : 35MHzROM Less / 24kB RAMTQFP-120ODD, printer,consumer equipment

H8SX/1650H8SX/1650

★

For 3.3V General MCU

Operation frequency : 35MHz768kB Flash / 24kB RAMTQFP-120

Operation frequency : 40MHz256kB Flash / 12kB RAMTQFP-100CAN,SSU

Printer Card readerePOS

Operation frequency : 50MHzEnhanced serial communication I/F （ USB2.0 full speed ､ High Speed SCI）

H8SX/1653FH8SX/1653F

384 or 512kB Flash / 40kB RAMTQFP-120 & LQFP-144

For 3.3V ASSP MCU

☆

H8SX/1582F

★★OA, FA equipment

Operation frequency : 48MHz256kB Flash / 12kB RAMLQFP-120SSU, DMAC, DTC

For 5V General MCUFor 5V ASSP MCU

H8SX Product Line-up

December, 2004 14

H8/36902/12 (uTiny)H8/36902/12 (uTiny)

On-chip Debug

Power on Reset and Low Voltage Detect

Main Clock Oscillator ( Crystal/Ceramic or RC

Selectable)

H8/300H CPU Core 10MHz @ 5V, 64KB address

RAM (1.5KB)

Memory

2, 4, 8KB

Timer V, B1 (2ch, 8-bit)

Timer W (1ch, 16-bit, PWM mode)

Watchdog Timer

Address Break Controller

* I2C Bus Interface (1

Channel)

SCI3-1ch (async/sync)

A/D (10-bit,

4ch)

I/O with high current pin

16-bit H8/300H CPU Core (0.35 um Process)

Oscillator

- Crystal/Ceramic 2 to 12 MHz, 3.0V-5.5V

- RC Oscillator Typical 8MHz, +/-2%(after trimming)

Timers

-8 Bit, Timers V and Timer B1(H8/36912)

-16 Bit, Timer W

- One Watchdog Timer (with internal oscillator circuit)

Serial I/O

-1-ch Async./Sync. Serial Com. Interface

-IIC Bus Interface (H8/36912)

A/D Converter

- 10 Bit, 4 Channel

I/O

•18 I/O (5 large current) + 4 input only

Memory capacity• 8k Bytes Flash, 1.5K Bytes SRAM

• 8k Bytes Mask, 512 Bytes SRAM

• 4k Bytes Mask, 256 Bytes SRAM

• 2k Bytes Mask, 256 Bytes SRAM (only in H8/36902)

Packages32 pin SSOP, LQFP( 7mm x 7mm)

32 SDIP

December, 2004 15

2% RC Oscillator over Temperature

December, 2004 16

H8/3687 Series H8/3687 Series (Enhanced 3694)(Enhanced 3694)

H8/3684/87F block diagram

Clock Oscillator

SubClock Osc (32 KHz)

14-bit PWM On-chip debug

H8/300H CPU Core

20Mhz @ 5V, 10 MHz @ 3V, 64KB

address

RAM 4KB

Flash Memory 32/56KB

RTC (1ch, 8-bit)

Timer B1 (1ch, 8-

bit)

Timer V (1ch,8-bit)

Timer Z (2ch, 16-bit)

I2C2 Bus Interface (1

Channel)

SCI3-2ch (async/sync)

A/D (10-bit, 8

ch)

45 I/O (8 w/ 20mA drive) + 8 Input Only

Watchdog Timer

Address BreakPOR, LVD (Optional)

• H8/300H CPU Core 1 to 10 MHz, 2.7-5.5V*(F-ZTAT:3.0 to 5.5V) 1 to 20 MHz, 4.5-5.5V

• Timers 8 Bit, Timers A ,V & Real time clock16 Bit, Timer Z (2ch)14-bit PWM Watchdog Timer with ring oscillator

• Serial I/O IIC2 Bus Interface Async/Sync communication- 2ch

• A/D Converter- 10 Bit, 8 Channel

• I/O and Interrupts 45 I/O + 8 Input Only, External 11, Internal 38

•Memory capacity Flash/RAM: 56k/4K Bytes, 32K/4K Bytes Mask ROM: 16KB-56KBPackages

FP-64A(14mm×14mm)FP-64E(10mm×10mm)

December, 2004 17

~ ‘97 ‘03‘00

Minimum Operation Voltage

1.8V

2.5V

3.0V

2.0V H8/38076R

1.8V

MaskOTP

2.7V

1.8V

2.2V

H8/38024R

H8/38004

FashOptimization of the sense

amplifier part to realize

4MHz / 1.8V operation

Technical approach

Sense amplifier

D D

Sense starting

Tuning the size ofsense amplifier MOS

Easier to use! The same low voltage operation as the Mask version.

Wide Operating Voltage

December, 2004 18

High-precision, high-resolution and ΔΣ type A/D with the high noise removal effect were mounted in the microcomputer.

Input

MUX

Ain1

Ain2

LCD 3V Booster

1.2V Band gap reference

BUFREF1.2V

PGA

VrefDout

(16bit ; effective data is 14 bits)

PSS

Clock & Interrupt controller

Inte

rna

l dat

a b

us

IRRSDADC

Control register

Data register (16 bit )

Second-order sigma delta ADCReference voltage

generator

System clock

fovs= no system clock frequency, 2 frequencies, 4 frequencies, 8 frequencies, 16 frequencies, 32 frequencies.

Programmable Gain Amplifier

ACOM

High noise shaping effect High noise shaping effect with a built-in digital filterwith a built-in digital filter

Built-in reference voltage generation circuitBuilt-in reference voltage generation circuitmakes external reference voltage unnecessary*2makes external reference voltage unnecessary*2

ΔΣA/D block diagram(built-in H8/38086)

*1 typ value*2 An external reference voltage can be input as well.

14bit resolution14bit resolution 　　 ±1.5LSB±1.5LSB*1*1

It’s possible to set up It’s possible to set up the conversion time the conversion time from 64us to 1.2msfrom 64us to 1.2ms

Built-in programmable gain amp,Built-in programmable gain amp,set up to 1/3, 2 and 4 times.set up to 1/3, 2 and 4 times.

H8/38076RH8/38086R14 bit Sigma-Delta A/D

December, 2004 19

　 An asynchronous event counter is a 16-bit event counter which independently of basic clock of microcomputer. Edge sense to count, rising, falling and both edge, is selectable by software.

　 It’s possible to set up loading period by software setting of a built-in PWM waveform generator.

Even if it operates the main part of microcomputer at a low speed, it can count a high-frequency external event. This leads to reduction of power consumption. AEC is a suitable for various sensor use and battery powered applications

AEC

AEVHAEVL

Sensor

PWM waveform generation circuit

Edge count maximum number is 65536 times.

-Event input-Settable event input period-Both edge, rising and falling edge sense

Count edges Count edges ト

Event input available during PWM High

All SLPAsynchronous Event Counter

December, 2004 20

H8/300H CPU 10MHz/2.7V ～ 3.6V (MASK & FLASH) 4.2MHz/1.8V ～ 3.6V (MASK & FLASH)ROM / RAM 16k byte / 1k byte 8k byte / 512 byte

Timers 8bit x 2ch (RTC, Interval timer) 16bit x 2ch 　　　　　 (Input capture /Output compare,　　　　　　 Asynchronous Event Counter / PWM output)　　　　 WDT 　SCI UART/ Synchronous/ IrDA x 1ch SSU** / IIC 　　　　　　　　 x 1chADC 10bit x 6ch

Comparator 　 x 2ch

Power On Reset

On-chip oscillator

Package 　　 TNP-32 (5.0x6.0, 0.5mm pitch)

H8/38602R(Flash/MASK)H8/38602R(Flash/MASK)

H8/300HCPU

ROM(MASK&FLASH)

RAM

Interrupt Controller

Timer B1(8bit)

10 bit A/D 6ch

RTC

WDT

AEC

SCI x 1ch

AddressBreak function

Comparator2ch

Power OnReset

SSU / IIC1ch

Timer W(16bit timer)

Large current port x 3ch

Block configuration

Under Development

E7supported*Real chip debugging is

available.

*Only for FLASH

** SSU : SPI compatible interface

Functions