5three phase three level stacked neutral (1)

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2856 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 6, JUNE 2013

Novel Three-Phase Three-Level-Stacked NeutralPoint Clamped Grid-Tied Solar Inverter

With a Split Phase ControllerYong Wang, Member, IEEE, and Fei Wang

AbstractCharacterized by the low leakage current and highefficiency, a three-level neutral point clamped (3L-NPC) inverterbecomes more popular for a transformerless photovoltaic gridconnected system. The three-level-stacked neutral point clamped(3L-SNPC) structure is a derivative of 3L-NPC providing moreadvantages such as a double apparent switching frequency andparallel load current paths. In this paper, the power loss distribu-tion and features of 3L-SNPC are analyzed first when applied tosolar inverters. Based on the analysis, a novel 3L-SNPC leg struc-ture is proposed for solar applications in order to reduce the power

loss particularly for the low power range, given the fact that solarinverters generally operate in the low power range during most ofthe daytime. Then, a two-stagesolar inverter topology, applying theproposed structure to the phase leg, is described. Further, a splitphase controller is applied for the two-stage solar inverter, con-sisting of the maximum power point tracking control, optimizeddc-link voltage control, and grid current control. Finally, a newdead-time elimination pulsewidth modulation strategy is proposedand conveniently implemented to each phase based on the splitphase controller. Experimental results are illustrated to demon-strate the applicability of the proposed topology and controller.

Index TermsGrid connected, split phase control, three-level-stacked neutral point clamped (3L-SNPC), topology.

I. INTRODUCTION

PHOTOVOLTAIC (PV) energy has become a convenient

and promising renewable energy source since last decade

and current PV systems are capable of generating electricity in

a very clean, quiet, and reliable way. In order to achieve low

cost, compact size, high reliability and efficiency, transformer-

less topologies have been proposed and increasingly analyzed

in the literature. The efficiency and the leakage current are two

main factors that should be considered during the development

of transformerless solar inverters. The study in [1][4] pro-

posed different topologies and modulation techniques to sup-

press the ground leakage current in transformerless solar invert-

ers. The study in [5] and [6] proposed several novel topologies

Manuscript received May 10, 2012; revised July 27, 2012 and September 11,2012; accepted October 18, 2012. Date of current version December 7, 2012.This work was supported by the National Nature Science Foundation of Chinaunder Project 51177100. Recommended for publication by Associate Editor S.Choi.

The authors are with the Key Laboratory of Control of Power Transmis-sion and Conversion, Ministry of Education, Department of Electrical En-gineering, Shanghai Jiao Tong University, Shanghai 200240, China (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2226475

for single-phase transformerless inverters to achieve higher ef-

ficiencies. Thereafter, among different transformerless topolo-

gies, three-level neutral point clamped (3L-NPC) inverter, as

shown in Fig. 1(a), is becoming more attractive for its higher

efficiency and lower leakage current [7][14]. Derived from

3L-NPC topologies, Floricau et al. [15] proposed the three-

level-stacked neutral point clamped (3L-SNPC) structure, as

shown in Fig. 1(b). A 3L-SNPC is made of six switches (i.e.,

S1 , S1c , S2 , S2c , S3 , and S3c ) disposed on three sides and twoclamp diodes(i.e.,Dnpc1 andDnpc2 ). Its exterior sides are madeof two switches which are connected serially to support the VDCvoltage. The middle side is made of two switches, connected in

an opposite way in order to form a bidirectional current path.

The clamp diodes are connected similar to the 3L-NPC topol-

ogy. Floricau et al. [16] proposed an active stacked neutral

point clamped converter (3L-ASNPC) as shown in Fig. 1(c).

The topology of a 3L-ASNPC is a derivative of the 3L-SNPC

structure, having two additional active switches connected

antiparallel with the clamp diodes.

Various pulsewidth modulation (PWM) strategies have been

proposed for the topologies of a 3L-SNPC and 3L-ASNPC.

Those topologies together with their PWM strategies are be-lieved to have better performance over a traditional 3L-NPC, in

terms of increased apparent switching frequencies, the parallel

load current paths, etc.

Meanwhile, thestudy in [15] also provided a PWM-1 strategy

for 3L-SNPC as shown in Fig. 2 and Table I. In Fig. 2, V is thereference voltage.

With the aforementioned PWM-1 strategy, the simulation re-

sults of the 3L-SNPC total power loss distribution, including

the switching and conduction losses, are shown in Fig. 3, where

fsw , Vdc , and Irm s,load are the switching frequency, dc voltage,and load current, respectively.

Apart from the aforementioned 3L-SNPCs advantages, com-pared with a 3L-NPC, it could also be found from Fig. 3 that

a 3L-SNPC also have disadvantages, such as, S1 and S1c andS3 and S3c are highly stressed in the switching power loss,especially for the cases with high switching frequencies. How-

ever, the most prominent disadvantage is the relatively high

insulated-gate bipolar transistor (IGBT) conduction loss in the

low power range due to IGBTs high saturation voltage. This is-

sue becomes a key problem in solar inverters due to the fact that

the three-phase PV inverter operates in a relatively low power

range during most of the daytime.

In this paper, based on the analysis and comparison for power

loss distributions in all PV power ranges, a novel 3L-SNPC

0885-8993/$31.00 2012 IEEE


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WANG AND WANG: NOVEL THREE-PHASE THREE-LEVEL-STACKED NEUTRAL POINT CLAMPED GRID-TIED SOLAR INVERTER 2857

Fig. 1. Topologies of a 3L-NPC, 3L-SNPC, and 3L-ASNPC. (a) 3L-NPC. (b) 3L-SNPC. (c) 3L-ASNPC.

Fig. 2. PWM-1 strategy proposed in [15].

TABLE IOUTPUT VOLTAGE AND SWITCHING SEQUENCE OF PWM-1

Output

Voltage

(VAO)

Switch

State

Switch Sequence

S1 S1c S2 S2c S3 S3c

-VDC/2 N 0 1 0 1 0 1

0O1- 0 1 0 1 1 0

O2+ 0 1 1 0 1 0

VDC/2 P 1 0 1 0 1 0

leg together with its PWM strategy is proposed to develop a

novel three-phase 3L-SNPC inverter for solar applications in

order to improve the efficiency. However, different from state-

of-the-art technologies where the efficiency at low power ranges

is not emphasized, this paper mainly focuses on the efficiency

at the low power range, considering the solar inverter operat-

ing below 80% power almost all the daytime. A new IGBT +CoolMosfet hybrid power device together with its switching

strategy is applied to reduce the outer power devices power

loss. IGBT + CoolMosfet hybrid parallel current paths are also

Fig. 3. Total power loss distribution simulation of PWM-1, courtesy of [15](modulation index = 0.95, fsw = 1 kHz, Vd c = 3000 V, Irm s , load = 130 A).

configured to alleviate the power losses. Moreover, a two-stage

solar inverter system with the split phase controller is proposed

and tested.

II. PROPOSED TWO-STAGE PV INVERTER AND ANALYSIS

OF POWER LOSS

The structure of the proposed two-stage transformerless PV

inverter is shown in Fig. 4.

In Fig. 4, two independent solar strings feed energy to

the dc link via two conventional boost converters. Energy

from the dc link is inverted to the grid through the proposed

3L-SNPC inverter. This design is mainly focused on the effi-

ciency improvement in both low and medium power ranges. In

each boost converter, two IGBTs are connected in parallel to

reduce the conduction loss. However, the main improvementlies in the proposed 3L-SNPC phase leg structure, as called out

in Fig. 5.

In Fig. 5, two CoolMosfets are paralleled with the outer

IGBTs. Moreover, the CoolMosfet and diode structure replaces

the IGBTs S1c -Lx and S3-Lx in 3L-SNPC. It is shown laterin this section that the switching loss and the conduction loss,

especially in the low power range, are reduced due to those

modifications. Additionally, two diodes Dp1 -Lx and Dn1 -Lx areadded to replace the body diodes in the load current path to

alleviate the diodes loss.

Fig. 6 shows theproposed 3L-SNPC topological stages in one

grid cycle when PWM-1 as illustrated in Fig. 2 is applied.


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Fig. 4. Proposed two-stage PV inverter topology using the proposed 3L-SNPC phase leg.

Fig. 5. Improved 3L-SNPC phase leg circuit.

In Fig. 6, in the positive half-cycle, the P state commutateswith the O2+ state as shown in Fig. 6(a) and (b). It indicates that

S2-Lx and S3-Lx keep ON while S1-Lx and S1c -Lx are switchingwith fsw .Different from the conventional 3L-SNPC or 3L-NPC, the

outer IGBT S1-Lx is paralleled with CoolMosfet to reduce theconduction loss in thePstate, especially in the low powerrange,because CoolMosfet has less ON-state voltage especially in the

low current case. Moreover, S3-Lx is replaced by CoolMosfetcompared with the conventional 3L-SNPC. Therefore, in the

O2+ state, IGBT ofS2-Lx and CoolMosfet ofS3-Lx form a par-allel load current path to reduce the conduction loss, particularly

in the low power range.

The same analysis can be extended to the negative half-cycle

as shown in Fig. 6(c) and (d).

The previous analysis shows that CoolMosfet with the lowconduction resistance can alleviate the conduction loss of the

hybrid switch S1-Lx and S3c -Lx . However, on the other hand,they themselves are still highly stressed with the switching loss

because of the modulation mode as shown in Fig. 6, particularly

when the switching frequency increases. Therefore, this paper

proposes to switch ON earlier and switch OFF later CoolMosfet

than its parallel IGBT. With this switching scheme, CoolMosfet

dominates most of the dynamic switching process. Forexample,

the power loss caused by the IGBT tail current can be avoided.

The aforementioned features lead to a better power losses

distribution in all devices. Therefore, the switching frequency

could be pushed to a higher level.

Table II shows the power device selection of the pro-

posed phase leg topology with the design consideration

aforementioned.

Thepower loss distribution with Table II andPWM-1iscalcu-

lated as follows. For simplicity, the ripple current is supposed to

be zero. Therefore, Dp1 -Lx and Dn1 -Lx do not conduct any cur-rent during the cycle. Since S1c -Lx does not actually conduct, it

hasno switching loss during thepositivehalf-cycle andthesameto S3-Lx in the negative half-cycle. Therefore, in the positive

half-cycle, power losses only happen on S1-Lx , S2-Lx , S3-Lx ,and Dnpc1-Lx .

Theconduction lossesof the outer devicesS1-Lx can be givenas

PS1-Lx -cond =1

T

T2

0

Vce (Pou t ) Pou t

2 sin(t)ULx

d(t)dt

(1)

where Pou t , Vce (Pou t ), d(t), ULx , Lx L1 , L2 , L3 are the onephase output ac power, IGBT, and CoolMosfet hybrid structure

on state voltage at thecertain phase poweroutput, theduty cycle,and the phase voltage, respectively. The switching loss ofS1-Lxis shown in Fig. 7, where E is the function between the IGBTand CoolMosfet hybrid structure switching loss per pulse and

the inverter current, f is the grid frequency, and k is the totalswitching time during one grid period.

It should be noted that the switching loss is mostly shared

by CoolMosfet because it is designed to turn ON earlier and

turn OFF later than the parallel IGBT. More importantly, in this

paper, Vce and Efor the IGBT and CoolMosfet hybrid structureare not directly from the devices datasheet but derived from the

actual test circuit as shown in Fig. 8.

Since the ripple current is supposed to be zero, the inner IGBTS2-Lx and CoolMosfet S3-Lx only have the conduction loss inthe positive half-cycle, given as

PS2-Lx -cond =1

T

T2

0

Vce (Pou t ) Pou t

2 sin(t)ULx

dt

(2)

PS3-Lx -cond =1

Ts

T2

0

Rs(Pou t ) Pou t

2 sin(t)ULx

2

(1 d(t))dt. (3)


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Fig. 6. Topological stages of PWM-1. (a) P state. (b) O2+ state. (c) N state. (d) O1 state.

TABLE IIPOWER DEVICE SELECTION WITH fsw = 34 kHZ

Dnpc1-Lx=Dnpc2-Lx=Dp2-Lx=Dn2-Lx FFP30S60S

Dp1-Lx =Dn1-Lx SIDC23D120F6

S1-Lx =S3c-Lx IPW60R045CP

S2-Lx =S2c-Lx =S1c-Lx =S3-Lx HGTG40N60

Fig. 7. Flowchart for the switching loss iteration calculation algorithm.

In (3), Rs(Pou t ) is the CoolMosfet on state resistance at the

certain phase output power.

Fig. 8. CoolMosfet and IGBT structure test circuit.

The clamping diodes losses are given as

PDnpc1-Lx =1

T

T2

0

VFW Pou t

2 sin(t)ULx

(1 d(t))dt

(4)

where VFW is the diode forward voltage.Equations (1)(4) can be extended to S1c -Lx , S2c -Lx , S3c -Lx ,

andDnpc2-Lx in the negative half-cycle easily. Therefore, basedon those equations, the power loss distribution is plotted in

Fig. 9(a). The power loss distributions of a 3L-SNPC and

3L-NPC as shown in Fig. 1(b) and (c) are also simulated for

comparison.


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Fig. 9. Power devices losses distribution analysis (fsw = 34 kHz, Vd c = 700 V). (a) Proposed 3L-SNPC. (b) 3L-SNPC. (c) 3L-NPC.

Fig. 10. Two-stage PV inverter with the proposed topology and its split phase controller.

As shown in Fig. 9(b) and (c), a 3L-SNPC improves the

3L-NPCs inner IGBT conduction loss by the parallel load

current path. However, the power loss of the outer IGBTs,

S1-Lx , S3c -Lx in a 3L-SNPC, are the same with a 3L-NPC.Therefore, as shown in Fig. 9(a), the proposed 3L-SNPC re-

duces S1-Lx , S3c -Lx power losses by the IGBT and CoolMosfethybridstructure. At thesame time, powerlossesof the inner four

power devices in the proposed 3L-SNPC, S2-Lx , S3-Lx , S1c -Lx ,and S2c -Lx , are also reduced due to the IGBT and CoolMosfethybrid current parallel path. It can be seen from Fig. 9 that the

total power loss reduced by using the proposed 3L-SNPC, com-

pared to a 3L-SNPC, is about 510 w, which is about 0.2% of

the rated power.

III. SPLIT PHASE CONTROLLER DESIGN

A split phase controller, including the maximum power point

tracking (MPPT), the optimized dc-link voltage control, etc., is

proposed and applied to the two-stage PV inverter as shown in

Fig. 10.

In Fig. 10, the PV input voltage range is 2001000 V and the

desired dc-link voltage is 700 V, slightly changed according to

the instantaneous grid voltage. Therefore, when the PV voltage

is lower than 700 V, it will be boosted to 700 V. However, whenthe input PV voltage is larger than 700 V, the boost converter

will be bypassed by the diodes.

The string voltages are controlled at Upv1Ref and Upv2Ref bythe boost converters in order to achieve MPPT control. The PV

voltages are boosted to the dc-link voltage UdcRef which is thelowest possible dc-link voltage to feed power into the grid as

shown in (5). It is verified that the lower UdcRef, the higher theboost efficiency [17]

UdcRef = [2

2 max(UL1 , UL2 , UL3 )/mm ax LX + margin]

(5)


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where UL1 , UL2 , UL3 ,mm ax LX ,margin are the three-phasegrid voltages, the maximum phase modulation index, and a 30

50 V voltage margin considering the grid voltage fluctuation

and analog-digital (AD) sampling error, respectively.

When the PV voltage Upv1Ref and Upv2Ref are larger thanthe dc-link reference voltage UdcRef calculated by (5), e.g.,700 V, the controller chooses the larger one between Upv1Refand Upv2Ref as the dc-link voltage reference. The boost con-verter is now bypassed. Therefore, the MPPT is controlled by

the inverter dc-link voltage control loop. Moreover, ifUpv1Refand Upv2Ref are significantly different from each other (e.g.,there is shadow or snow), a tradeoff PV reference voltage will

be calculated to optimize the total yielding which can be an in-

teresting future research topic. Therefore, a maximum selection

or tradeoff calculation block (as shown in Fig. 10) is designed

to determine the input reference voltage for two dc-link voltage

P controllers.Meanwhile, thepositive andnegative half dc-link voltagesare

both sampled and fed back to two independent P controllers.

Two P controllers are commutated at 150 Hz, considering thatthe dc-link voltage referred to the neutral point has 150 Hz

ripple. In this way, the positive and negative half dc voltages are

kept balanced.

Iam p , as given in (6) and (7), is the dc voltage P controllersoutput variable added with PV power feedforward component

responding to the PV panel power fluctuation to improve the

dc-link dynamic response

Iam p = kp (1/2 UdcRefUdc ,Po s )+ k (Ppv 1 + Ppv 2 )/UdcBus (6)

or

Iam p = kp (1/2 UdcRef|Udc ,Ne g |)+k (Ppv 1 + Ppv 2 )/UdcBus (7)

where UdcBus = Udc ,Po s + Udc ,Ne g and k is the input powerfeedforward coefficient.

The product ofIam p and the digital phase lock loop outputvariable sin LX (as shown in (8)) is the current reference forthe proportional resonance (PR) controller which is proved to

have better performance in canceling the steady-state ac current

error and in rejecting grid disturbances

Ire f,L 1 = Iam p

sinL1

Ire f,L 2 = Iam p sinL2Ire f,L 3 = Iam p sinL3 .

(8)

The grid currents Igrid,L 1 , Igrid ,L 2 , and Igrid,L 3 are other in-put variables for PR controllers as shown in Fig. 11. It composes

of fundamental current controller Gc(s) and the harmonic cur-rent compensators Gh (s) = G3 (s) + G5 (s) + G7 (s), acting asnotch filters to the third, fifth, and seventh harmonics.

The fundamental current controller Gc(s) is defined as

Gc(s) = kp1 + ki1s

s2 + 2LX(9)

where LX is the grid phase frequency in radian per second.

Fig. 11. Grid current PR controller.

The harmonic compensators Gh (s) are defined as

Gh (s) =

h= 3,5,7

kihs

s2 + (LX h)2. (10)

Gd-Lx (s) and Gf-Lx (s) in Fig. 11 are the inverter and LCL

filter transfer function, respectively.Again in Fig. 10, Ucommand-Lx , as the output of the PR

controller, is taken as the inverter voltage reference. With

Ucommand-Lx , the modulation function mLx can be defined as

mL1 =Uc o m m a n d L 1

Ud c B u s sinL1t


Ud c B u s sinL2t


Ud c B u s sinL3t.

(11)

In the grid-tied inverter, the modulation function mLx is ob-tained from and in phase with the output current Igrid,Lx given

the utility power factor. That is, even though S1c -Lx is switch-ing complementarily with S1-Lx in the positive half-cycle, itactually does not conduct the current. Therefore, the switching

signal for S1c -Lx could be disabled ifmLx is positive. However,the switching signal for S1c -Lx should be enabled around thezero-crossing point to conduct a high-frequency ripple current

which could both have positive and negative current polarities

within one switching period. Based on the analysis earlier, this

paper proposes a new split phase PWM control strategy for the

improved 3L-SNPC as shown in Fig. 12. Phase L1 is used to

explain the switch states.

Table III shows the switching states with the improved PWM

strategy as shown in Fig. 12.

Compared to Fig. 2 and Table I, in this case, O1+ and O2are the added states specific to the new PWM strategy, in which

switching signals ofS1c -Lx or S3-Lx are disabled. The P statecommutates with O1+ during [1 , 2 ], and the N state com-mutates with O2 during [3 , 4 ] as shown in Fig. 12. Onlyaround zero-crossing region [2 , 3 ], switchingsignals ofS1c -Lxor S3-Lx are enabled. The P state commutates with O2+ dur-ing [2 , 0] and the N state commutates with O1 during [0,3 ] as shown in Fig. 12. Therefore, in Fig. 12, S2-Lx and S2c -Lxwork completely with the line frequencywhileS1c -Lx andS3-Lxonly work with the switching frequency in the short period

[2 , 3 ] conducting very low current. Therefore, the dead-time

is only necessary in the region of[2 , 3 ] where 2 and 3 are


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Fig. 12. Improved PWM strategy for a novel three-phase 3L-SNPC.

TABLE IIISWITCHING STATES OF THE NEW PWM STRATEGY

Switch states Switch sequence

S1-Lx S2- Lx S2c- Lx S3c- Lx S1c- Lx S3- Lx

P 1 1 0 0 0 1

O1+ 0 1 0 0 0 1

O2+ 0 1 0 0 1 1

O1- 0 0 1 0 1 1

O2- 0 0 1 0 1 0

N 0 0 1 1 1 0

determined by

ILx sin 2 =|Igrid ,Lx |

2=

|(udcBus uLx ) mLx |2LiLx fsw (12)

ILx sin 3 =

|Igrid,Lx |

2

=|(udcBus uLx ) mLx |

2LiLx fsw(13)

where ILx ,Igrid,Lx , udcBus, uLx , LiLx , fsw arethegridphasecurrent amplitude, the grid current ripple, the dc-link voltage,

the grid voltage, the inverter-side inductance, and the switching

frequency, respectively.

The flowchart of judging the region is shown in Fig. 13.

As shown in Fig. 13, when the ripple current amplitude is

larger than thegrid current, themodulation function is withinthe

zero-crossing region [2 , 3 ]. The switching signals for S1c -Lxor S3-Lx should be enabled to provide the load current path.

With the proposed PWM strategy based on the split phase

controller, the topological stages in one grid cycle for the pro-

posed inverter is shown in Fig. 14.

Fig. 13. Flowchart for working region and states judging.

In the positive half-cycle as shown in Fig. 14(a), (b), and (c),

the P state commutates with O2+ only in the narrow region of[2 , 0], the same as the situation shown in Fig. 6. In [2 , 0], both

S1-Lx andS1c -Lx areswitchingwith fs ; therefore, thedead-timemust be inserted between those two states. However, in the most

region of the positive half-cycle apart from [2 , 0], the P statecommutates with the O1+ state as in Fig. 14(b). Therefore, onlyS1-Lx is switching ON and OFF and no dead-time is necessary.The same analysis can be extended to the negative half-cycle as

shown in Fig. 14(d), (e), and (f).

With the new dead-time elimination PWMstrategy, the maxi-

mummodulation ratio as shownin (14) canbe improvedbecause

Td , the dead-time, is almost zero

mma x -Lx = 1 TdTs

(14)

where Td and Ts are the dead-time and control period, respec-tively.

Moreover, with enhanced mm axLx , the dc-link referencevoltage UdcRef as shown in (5) can be reduced to improve thesystem efficiency.

IV. SYSTEM PARAMETERS DESIGN

A 17-kW two-stage PV inverter prototype with the proposed

phase leg and its split phase controller is designed and builtup in

this paper, in which the switching frequency is improved to 34k

to reduce the filter size. Therefore, the inverter-side inductance

Li

Lx is designed as 1 mH to suppress the inverter peak ripple

current IpkLx to be within 20% Igrid,rated , as shown

Ipk -Lx =|(udcBus/2 uLx ) mLx |

Li-Lx fsw < 20% Igrid ,Lx ,rated(15)

where Igrid ,Lx ,rated is the rated inverter current.Next, in order to further attenuate the current ripple to a

desired level, an LC second-order filter is used as a part of the

LCL filter. The attenuation at the switching frequency can be

determined by plotting the bode plot of the transfer function

[i.e., (16)], as shown in Fig. 15

Igrid ,Lx (s)

Ii,Lx (s)=

1

1 + CfLx LgLx s2. (16)


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Fig. 14. Topological stages corresponding to the switching states. (a)P state. (b) O1+ state. (c) O2+ state in [2 , 0]. (d) N state. (e) O2 state. (f) O1 state in[0, 3 ].

Fig. 15. Bode plot of theLgLx CfLx filter transfer function.

The LgLx CfLx is designed as LgLx = 150 uH and

CfLx = 4.7 uF to get around 30 dB attenuation at the switch-ing frequency as it can be seen in Fig. 15. Thus, the grid-sidecurrent is highly attenuated. Main system parameters are listed

in Table IV.

V. EXPERIMENTAL RESULTS

The prototype is build up and tested to verify the proposed

topology and controller.

The experimental waveforms are shown from Figs. 16 to

23. For comparison and simplicity, the open circuit and MPPT

voltage UO C/UPV are fixed at 800 and 640 V, respectively.In Figs. 16 and 17, the drive signals of S1-L1 and S1c -L1

are used to demonstrate the new PWM strategy, where S1-L1 is

TABLE IVMAIN EXPERIMENTAL PARAMETERS

Open circuit voltage range OCU 200V-1000V

PV operating voltage rangePVU 0.8* OCU

V008-V062egnarTPPM

AC output voltagegridU

230V

LxiL @0A/ LxfC / LxgL @0A1mH/4.7uF/150uH

BoostL @0A2.7mH

Inverter switching frequency 34kHz

Boost switching frequency 17kHz

-k03026amorhClenapraloS

1000/30kW-1000V


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Fig. 16. Drive signals and grid current with a new PWM strategy at 8-kWoutput (green: grid current, 20 A/div, blue: S1-L1 , 10 V/div, yellow: S1c -L1 ,10 V/div, time: 10 ms/div).

Fig. 17. Drive signals and grid current with a new PWM strategy at 12-kWoutput (green: grid current, 30 A/div blue: S1-L1 , 10 V/div, yellow: S1c -L1 ,10 V/div, time: 10 ms/div).

Fig. 18. Drive signals for S1-L 1-C o o l M o s f e t (yellow, 5 V/div) andS1-L 1-I G BT (blue, 5 V/div), time: 400 ns/div.

working with fsw . However, S1c -L1 is working with fsw onlyin the narrow region across the zero crossing point. The region

width is determined by the load current as shown in Fig. 13.

Therefore, in Fig. 17, the region width ofS1c -L1 switching isreduced soundly compared to Fig. 16, because the power has

been increased from 8 to 12 kW.

Figs. 16 and 17 also show that in the negative half-cycle,

S1c -L1 is ON state to conduct the current parallel to S2c -L1 .Figs. 18 and 19 show the drive signals for S1-L1 -IGBT and

S1-L1 -CoolMosfet where CoolMosfet is switching ON earlier and

Fig. 19. Drive signals for S1-L 1-C o o l M o s f e t (yellow, 5 V/div) andS1-L1 -I G B T (blue, 5 V/div) time: 1 us/div.

Fig. 20. Positive dc-link voltage (yellow, 100 V/div), negative dc-link voltage(blue, 100 V/div), UL 1 (green, 250 V/div), UL 2 (250 V/div, purple), time:10 ms/div.

Fig. 21. Positive dc-link voltage (yellow, 100 V/div), negative dc-link voltage(blue, 100 V/div) UL 1 (purple, 250 V/div), UL 2 (green, 250 V/div), time:

10 ms/div.

switching OFF later than IGBT to share most of turn ON/OFF

power losses.

Figs.20 and21 show thedc-link voltage control results,where

the dc-link voltage is not fixed but slightly changed according to

the grid voltage fluctuation. Moreover, the positive and negative

dc-link voltages can reach very good balance not only with bal-

anced grid voltage as shown in Fig. 20, but also with unbalanced

grid voltage as shown in Fig. 21.

Fig. 22 shows three-phase current waveforms with full power.

It shows relatively large total harmonic distortion, particularly

around the zero crossing point because the proposed PWM


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Fig. 22. Three phase currents (50 A/div for all, time: 10 ms/div).

Fig. 23. Efficiency versus output power: (a) efficiency of the proposed proto-type for different open-circuit voltage of the PV generator (Vo c ), (b) efficiencycomparison between the conventional 3L-NPC and the proposed 3L-SNPCtopology for Vo c = 1000 V.

strategy cannot compensate the dead-time effect around the

zero crossing point. Moreover, the uncompensated region will

become larger if the inverter is generating reactive power.

Fig. 23 shows the efficiency plot in all power range and

the comparison with the conventional 3L-NPC solar inverter.

It shows that the efficiency, especially in low power range, is

soundly improved.

VI. CONCLUSION

This paper has investigated the power loss distribution in the

conventional 3L-NPC and 3L-SNPC structures for solar invert-

ers. Much attention has been paid on power losses in the low

power range. To overcome the drawbacks, the authors proposed

an improved 3L-SNPC phase leg topology together with a new

PWM strategy. With the novel construction and PWM strategy,

the power losses are reduced especially in the low power range.

A 17-kW two-stage solar inverter topology is described and a

split phase controller is designed. The novel PWM strategy is

also proposed and easily applied to each phase leg with the split

phase control scheme.

The experimental results from the prototype are shown to

verify the applicability of the proposed schemes.

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Yong Wang (M12) received the Ph.D. degreein power electronics from Zhejiang University,Hangzhou, China, in 2005.

From 2005 to 2008, he was a Senior Researcherin Samsung Advanced Institute of Technology,Korea, researching on the fuel cell grid-tied inverter.From 2008 to 2010, he was a Power ElectronicsHardware Engineer in Danfoss, Denmark. In 2010,he joined Shanghai Jiao Tong University, Shanghai,China, where he is currently an Associate Professorin the Department of Electrical Engineering. His re-

search interest includes the power electronics applications in renewable energy,especially the grid-tied inverter.

Fei Wang received the B.E. degree in electricalengineering from Shanghai Jiao Tong University,Shanghai,China, in June 2012, where she is currentlyworking toward the Masters degree in electrical en-gineering, majoring in power electronics and powerdrives.

Her current research interests include photovoltaicinverter and wind-power converter.

5three phase three level stacked neutral (1)

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