Task I: Simulation of Regulated power supply to generate 5 volt supply and Simulation of Square wave generator using 555 Timer.AIM/OBJECTIVE:Generate a regulated power supply of +/- 5V DC from 230V, 50 Hz AC mains using a transformer or a Capacitor. After generating the supply, use the power to run a 555 timer IC to generate a square wave of 50% duty cycle.EQUIPMENT REQUIRED:For +/- 5V Generation: One IC 7805 One IC 7809 Two 1000uF Capacitors Two Bridge Rectifiers One Transformer (22:1) One OscilloscopeFor Square wave Generation: 555 Timer IC One 10nF Capacitor One Silicon Diode Two 7.21k Resistors One OscilloscopeSOFTWARE USED: Proteus ISIS ProfessionalSUMMARY ON DATASHEET:IC 7805: It is a 3-pin (Input/ Ground/ Output) voltage regulator integrated circuit. The voltage regulator IC maintains the output voltage at a constant voltage (In this case +5V). The absolute maximum input voltage is 35 to 40V for the output lying in the range of 4.8V to 5.2V. Operating temperature range is from -40C to 125C. Maximum peak current is 2.00A.IC 7905: It is a voltage regulator IC which gives a -5V DC output. The operating temperature is from 0 C to 125C.The input voltage should be in the range of -25V to -30V to get an o/p voltage in the range -4.8V to -5.2V. Peak o/p current is 2.2A.THEORY:Regulator circuit: IC 7805 and 7905 are fixed linear voltage regulators. The voltage source in a circuit may have voltage fluctuations and would not give a fixed desired voltage output. The IC maintains the output voltage at a constant level. In this project, IC 7805 keeps the output voltage at +5V and IC 7905 keeps it at -5V.555 Timer:

The circuit given above is that of a 555 timer. It is a 8 pin IC that is for producing delays and generating square waves or oscillators.

The above circuit shows when 555 timer is used to produce a square wave. Due to the voltage dividers, the voltage at nodes is 3.33V and 1.66 V. Now, comparator 1 produces a high o/p when voltage at (+) is higher than 3.33V and comp 2 gives a high o/p when voltage at (-) is lower than 1.66V. Now the output Q goes high when Comp2 gives a high pulse. Therefore the transistor is off and the capacitor starts charging towards +5V through Ra and Rb. This continues till the voltage at comparators increases by 3.33V. Due to this Reset pin gets On and transistor short circuits the path and capacitor starts discharging but only via Rb and not through both the resistors. Therefore the On time is C(Ra+Rb) whereas the Off time is C(Rb). Therefore the duty cycle is (Ra+Rb)/(Ra+2Rb). But to get 50% duty, we cannot simply remove the Ra. We can place a diode in parallel to Rb due to which during charging, the time constant is CRa and during discharging, the time constant is CRb. Now if we select 2 resistors of equal value, we can get 50% duty cycle.PROCEDURE: Proteus ISIS software was started and a new project was started. Components like Sine wave generator, Transformer, Rectifier Bridge, Capacitors, IC 7805 and IC 7905 were selected from the toolbar and dropped to the virtual board. All the components were connected ion proper order to get a regulated supply output of 5v from IC 7805 and -5V from IC 7905. The oscilloscope probes were connected to both the outputs from ICs and 1 to the input. Results were observed. For the generation of the square wave with 50% duty cycle, after proper calculations, components like 555 Timer IC, 2 resistors of equal value and 1 capacitor were selected from the toolbar and dropped on the design area. The connections were done as per the pin diagram and circuit diagram as described in the Theory section. The oscilloscope probes were connected to the input and output of 555 Timer and the Square wave obtained was analyzed.

RESULTS:Voltage Regulator Circuit:

Zoomed Output:

555 Timer IC:

Output square wave:

CONCLUSION:The voltage was successfully regulated to +5V and -5.2V by IC 7805 and IC 7905 respectively from a 220V, 50Hz AC supply. Then, this supply was used effectively in running a 555 Timer IC to produce a square wave of 50% duty cycle. The simulations results have been attached. 6 | Page