5003_lownoiseamplifier

12 www.rfdesign.com November 2003

R adio link range is a key performanceparameter in cost-sensitive WLAN sys-tems targeted for the consumer market. Astransmitter output power is limited by gov-ernment regulations, receiver sensitivity is ofprime importance. The receivers low noiseamplifier block dominates the receiversnoise figure.

A high-performance, low-cost, highlyrepeatable two-stage low noise amplifier(LNA) for use in 5 GHz to 6 GHz wirelessapplications is presented. The LNA makesuse of standard, low-cost FR4 board material,inexpensive 0402 case-size chip components,and new, cost-effective silicon-germanium(SiGe) transistors in standard surface-mountpackages. Gain in excess of 20 dB is achievedwith 1.5 dB noise figure in a design consum-ing 16 mA at 3.3 Volts, while requiring 80mm2 of PC board area. A discrete transistordesign provides design flexibility whileallowing for fast time-to-market.

Despite the ongoing trend toward higherintegration levels, discrete RF componentsstill have their place in contemporary wirelessdesigns. While component vendors for moremature market segments, such as cellular andpersonal communication system (PCS), offera wide range of proven, cost-effective andhighly integrated devices, RF designerstasked with bringing product quickly to mar-ket at higher frequencies in new, emergingareas have fewer choices available in terms offully integrated components.

Furthermore, early generation integrateddevices for such emerging markets oftenexhibit poor performance. Discrete RFdevices offer advantages such as superior per-

formance, tremendous design flexibility andversatility, faster time-to-market, low cost andreduced risk.

Silicon- and silicon-germanium (SiGe)based transistors and monolithic microwaveintegrated circuits (MMICs) have demonstrat-ed tremendous improvements in both perfor-mance and cost, and are steadily expandinginto areas that previously were only served bymore expensive gallium arsenide (GaAs)based devices.

The final product used throughout this arti-cle is Infineon Technologies AGs (www.infi-neon.com) BFP640 silicon germanium RFtransistor, which is shown in a two-stageLNA application targeted for WLANs andother systems using the 5 GHz to 6 GHz fre-quency range.

Figure 2 shows Infineons current SiGetransistor family, and Figure 6 and Figure 7give a schematic diagram and bill of material(BOM) for the LNA.

Measurement results are presented in Table1. These results are mean values taken from asample lot of 12 circuit boards. Please notethat the reference planes for all measurementdata shown in Table 1 are at the PC boardsSMA RF connectors in other words, iflosses at the LNA input were subtracted, thenoise figure values would be slightly lowerthan shown.

Transistor descriptionThe BFP640 is a SiGe heterojunction bipo-

lar transistor, manufactured in a B7HFprocess, is a derivative of Infineons originalSiGe transistor, the BFP620.

In the BFP640, a lower or lighter dopant

concentration in the transistors collectorregion is used. The lighter collector dopingincreases the minimum collector-emitterbreakdown voltage (VCEO), reduces the tran-sistors internal parasitic collector-base capac-itance (CCB), and reduces undesired internalfeedback, yielding increased gain andimproved stability margin. See Figure 1.

The higher minimum breakdown voltage(4.0 V VCEO, versus 2.3 V for the BFP620)makes operation in 3 volt systems more con-venient, as it is not possible to exceed thetransistors maximum collector-emitter volt-age in a system using a 3 volt power supply.

The higher breakdown voltage permits theelimination of circuit elements previouslyneeded to reduce the 3 volt system supplyvoltage to below 2.3 volts, which wererequired for safe operation with the older tran-sistor. In addition to being useful in LNAapplications, the new transistor has been suc-cessfully employed as a power amplifier (PA)driver in 5 GHz WLAN designs.

The BFP640s two siblings, the BFP650and BFP690, utilize the same processenhancements as the BFP640, but have largeremitter areas, allowing for increased collectorcurrent and higher RF output power levels.The maximum ratings for the BFP640,BFP650 and BFP690 are given in Table 2. Achart showing details of Infineons new SiGetransistor is given in Figure 2.

Semiconductors/ICs/DSPs

A low-cost, two-stage, low noise amplifier for 5 GHz to 6 GHz applications using the silicon-germanium BFP640 transistor

Radio link range is a key performance parameter in cost-sensitive WLAN systems targeted for theconsumer market. In this article, a high-performance,low-cost, highly repeatable two-stage low noiseamplifier for use in 5 GHz to 6 GHz wirelessapplications is presented. This discrete transistordesign provides design flexibility while allowing for fast time-to-market.

By Gerard WeversFigure 1: Process enhancements for BFP640,BFP650 and BFP690 transistors increase the min-imum collector-emitter breakdown voltage (from2.3 to 4.0 V VCEO) and reduce the transistors inter-nal parasitic capacitance CCB. This results in areduction in reverse transmission coefficient S12,yielding higher gain and improved stability.


3.5 GHz to 6 GHz, two-stage LNA design details

The LNA consists of two identicalBFP640 stages in cascade. All RF simula-tions and printed circuit board design stepstook place within Eagleware Corp.s(www.eagleware.com) Genesys version 8.0software design package.

Effort was made to minimize noise figureas well as the number of external matchingelements required. The circuit board is laidout in such a manner as to permit easy testingof either stage individually. Lumped elementmatching techniques are used exclusively tominimize required PC Board area.

StabilityIn general, for a linear two-port device

characterized by S-parameters, the two neces-sary and sufficient conditions to guaranteeunconditional stability (meaning no possibili-ty of oscillation when the input and output ofthe device are both terminated in any passivereal impedance) are:

(a) K > 1 and (b) || < 1where

K = 1|s11|2 |s22|2 +||22|s12 s21|

|| = |s11 s22 s12 s21|In the literature, one may encounter an

alternative form for these two conditions, as:

(a) K > 1 and (b) B1 > 0

where

B1 = 1+|s11|2 |s22|2 ||2

A single stage of the two-stage LNA wasmeasured for S-parameters from 125 MHz to2 GHz, and then from 2 GHz to 15 GHz. TheS-parameter files from each measurementwere imported into the Genesys package.

Genesys was employed to calculate andplot stability factor K and stability measureB1 in each case. See Figure 3 and Figure 4.

One can see K > 1 and B1 > 0, showingthat the necessary and sufficient conditionsfor unconditional stability have been met.Since both stages are of identical design andlayout, it is sufficient to check for uncondi-tional stability of either one of the two stages.

If the criteria for unconditional stability aresatisfied for a single stage, then an additionalidentical stage may be safely cascaded after thefirst stage, provided the two stages dont havean undesired feedback path between them.

In other words, unless the individual uncon-ditionally stable stages can talk to each other

Table 1: Typical performance of the complete two-stage 5 GHz to 6 GHz BFP640 LNA at 25 C.

Figure 2: Overview of Infineon Technologies silicon-germanium RF transistors.

Table 2: Overview of maximum ratings and packaging for SiGe RF transistors.

Device VCEO (V) IC MAX (mA) PDISS (mW) RthJS** Package

BFP620 2.3 80.0 185(1) 300 C/W SOT343

BFP620F 2.3 80.0 185(1) 280 C/W TSFP4

BFP640 4.0 50.0 200(2) 300 C/W SOT343

BFP650 4.0 150.0 500(3) 140 C/W SOT343

BFP690L7 4.0 350.0 TBD TBD TSLP7-1

**Thermal resistance, device junction to soldering point(1) Soldering point temperature = 95 C.(2) Soldering point temperature = 90 C.(3) Soldering point temperature = 75 C.

Parameters Frequency (MHz)5150 5470 5925

Gain (dB) 23.5 22.2 20.3Noise figure (dB) 1.3 1.4 1.5Input IP3 (dBm) +5.0 Input P1dB (dBm) -14.2 Input return loss (dB) 15.3 19.0 16.4Output return loss (dB) 10.9 14.7 17.0Supply current (mA) 16.3PCB area (mm2) 80.0Number of SMT components, 25including bias resistors, DC blocks, chip coils, and BFP640s

Conditions: Temperature = 25 C, Voltage = 3.3 V, n = 12 units, ZS = ZL = 50, network analyzer source power = -30 dBm


via leakage paths through shared DC supplylines or other PC board features, cascading indi-vidual unconditionally stable stages will result inan unconditionally stable multi-stage amplifier.

In making stability calculations usingmeasured S-parameters, one must bear inmind that the reverse transmission coeffi-cient (S12) of high-transition frequencydevices like the BFP640 becomes vanishing-ly small at lower frequencies. Therefore, thesignal being measured may well fall into thenoise floor of the network analyzer beingused. Its important that network analyzerdynamic range considerations are taken intoaccount when making the S-parameter mea-surements. Otherwise, the measured S-para-meter results may be suspect, and one maynot get a clean curve when plotting K andB1 particularly for frequencies below 1GHz. An excellent reference for the interest-ed reader is given in Agilent TechnologiesInc.s (www.Agilent.com) application note1363-1, Understanding and ImprovingNetwork Analyzer Dynamic Range.1.

LinearityThis LNA makes use of a trick to

enhance third-order intercept performance.In brief, a relatively large-value capacitor is

placed across the base-emitter and collector-emitter junctions to provide a low impedancepath at low frequencies. This low-frequencypath serves to bypass the low-frequency dif-ference product (f2-f1) resulting from a two-tone test. (See the schematic diagram in Figure6. C3, C8, C6 and C11 perform this function).

The rule of thumb states that there existsapproximately 10 dB difference between theamplifier compression point and the third-order intercept point. Use of this trick getsaround this general rule, and increases the dif-ference from the expected 10 dB to between15 dB and 20 dB. Employment of this tech-nique is why the LNAs input third-orderintercept point (IIP3) of +5.0 dBm is more

than 10 dB higher than the amplifiers typicalinput 1dB compression point (IP1dB) of -14dBm. For additional detail on how this capac-itor trick works, please refer to Infineonsapplication note AN060, A High IIP3 LowNoise Amplifier for 1900 MHz ApplicationsUsing the SiGe BFP620 Transistor.2

Noise figureThe new transistor is an excellent low-noise

device and offers noise figure performancecomparable to far more expensive GaAs metalsemiconductor field effect transistor (MES-FET) and GaAs pseudomorphic high electronmobility transistor (PHEMT) devices.

As one would expect with RF transistorshoused in standard, low-cost surface-mountpackaging, the gain of the BFP640 transistorchip is limited by the package parasitics asone moves above the 3 GHz range. Near 5GHz, the bias current for minimum noise fig-ure is about 5 mA.

A tradeoff of gain, noise figure and lineari-ty resulted in the DC operating point of 3 voltsVCE and 8 mA collector current being selected.Table 3 gives noise parameters for the transis-tor at the 3 volt, 8 mA bias point. Note theexcellent minimum noise figure values (FMIN)

and the modest, easy-to-handle optimumreflection coefficient magnitudes (OPT).

In designing the LNA for both low partscount and best possible noise figure, it wasdecided to avoid any external input imped-ance matching elements, if at all possible. Inaddition to the possibility of pulling the inputimpedance presented to the transistor furtheraway from its optimum impedance for noisefigure, any practical matching element willintroduce loss of some sort at the LNA inputand, therefore, degrade the amplifier noisefigure. This is especially true up at 5 GHz. Aplot of noise figure versus frequency for thetwo-stage cascade LNA is given in Figure 5.

Input/Output impedance matchRefer to the schematic diagram in Figure 6

on page 18.Lumped-element matching techniques are

used exclusively, to reduce required PC boardarea. The output impedance matching circuitconsists of L2 and L3 for the first stage, andL5 plus L6 for the second stage.

Due to the nonzero reverse transmissioncoefficient of the transistor (S12 0), the outputmatch favorably influences the input impedancematch, with better than 10 dB input and output

Figure 3: Stability factor K and stability measure B1 for a single LNA stage,generated from actual measured (not simulated) amplifier S-parameters, from125 MHz to 2 GHz. Note that K > 1 and B > 0.

Figure 4: Stability factor K and stability measure B1 for a single LNA stage,generated from actual measured (not simulated) amplifier S-parameters, from2 GHz to 15 GHz. Note that K > 1 and B > 0.

Table 3: BFP640 device noise parameters at VCE = 3.0 V, IC = 8 mA.

Frequency FMIN OPT OPT RN/50(GHz) (dB) (mag) (angle) (ohms)

0.9 0.42 0.22 21.00 0.12

1.8 0.68 0.08 2.00 0.11

2.4 0.74 0.08 50.00 0.11

3.0 0.84 0.06 141.00 0.09

4.0 0.91 0.11 -101.00 0.10

5.0 1.01 0.25 -61.00 0.14

6.0 1.20 0.22 -82.00 0.13


return loss values achieved across the band.As a result, no input impedance matching

elements are required only an input DCblock and a choke (L1 on first stage) tobring in base bias current is needed at theinput. The value of L1 and L4 were chosensuch that the chip coils operate just below theirself-resonant frequency (SRF), ensuring thatthese elements have minimal loading effectson the input of each stage. A bill of material(BOM) is presented in Figure 7. Note thatlow-cost, industry-standard 0402 case-sizechip components are used throughout.

Details on the printed circuit boardAs stated previously, the PC board used in

this applications note was simulated withinand generated from the Genesys softwarepackage. After simulations, CAD filesrequired for PCB fabrication, includingGerber 274X and Drill files, were createdwithin and output from Genesys. Photos ofthe PC board are provided in Figure 8, Figure9 and Figure 10. A cross-sectional diagram ofthe PCB is in Figure 11.

The PC board material used is standard low-cost FR4. Note that each stage of the LNA maybe tested individually; capacitor C2 (seeschematic) may be positioned to steer the RFfrom the output of the first stage to the SMAconnector on the bottom of the PCB, or, C2 maybe used to link the track from this same RF con-nector to the input of the second stage, to permit

testing of Stage 2 individually. The total PCBarea consumed for a single stage is approximate-ly 0.300 inch x 0.200 inch (7.6 mm x 5.1 mm),or approximately 40 mm2, giving about 80 mm2for the complete two-stage amplifier. The totalcomponent count, including all passives, and thetwo BFP640 transistors, is 25.

Future trendsSilicon-Germanium process enhancements

are ongoing. Existing B7HF SiGe processesare being further modified to reduce contactresistances and improve transit times - result-ing in even lower noise figure transistors. Thefirst Infineon product to be released in thisnew B7HFe process technology will be theforthcoming BFP740. Figure 12 below

includes a noise figure plot of an earlyBFP740 engineering sample in a single-stage5 GHz LNA application. The BFP740 showsan improvement of 0.2 dB to 0.3 dB in noisefigure over the existing BFP640 in the sameexact FR4/glass-epoxy PC board shown inthis article, with better than 10 dB input andoutput return loss over the full 5 to 6 GHz fre-quency range. This represents about a 20 per-cent reduction in noise figure as compared totodays mass-production BFP640 transistor.

ConclusionsThe BFP640 silicon-germanium RF tran-

sistor offers a high performance, power-effi-cient solution for a broad range of high-fre-quency low-noise amplifier (LNA) designs.

Figure 5: Noise figure at 25 C for the complete two-stage cascaded BFP640 LNA.

Figure 6: Schematic diagram for the complete two-stage 5 GHz to 6 GHz LNA.


The flexibility of this discrete RF deviceallows one part to fulfill several differentfunctions. For example, the BFP640 may beused as an LNA or a PA driver amplifier in 5GHz WLAN applications.

This article describes a high-performance,low cost, two-stage lumped-element discreteLNA design for the 5 GHz to 6 GHz frequen-cy range. The high gain and low noise figureof the LNA presented enhances receiver sen-sitivity in WLAN and other 5 GHz to 6 GHzsystems. Future enhancements to SiGe

process technology will reduce noise figurevalues even further and result in devices witheven higher performance potential than thosein mass-production today.

References1. Understanding and Improving Network

Analyzer Dynamic Range, Application Note1363-1, Agilent Technologies Inc. This appli-cations note explains how to minimize thenoise floor and maximize the dynamic range

of a network analyzer.2. A High IIP3 Low Noise Amplifier for

1900 MHz Applications Using the SiGeBFP620 Transistor, Applications NoteAN060, Silicon Discretes Group, InfineonTechnologies North America Corp. The sec-tion entitled Effect of adding additionalcharge-storage across the base-emitter junc-tion explains the capacitor trick used toenhance third-order intercept performance.

Figure 7: Bill of material (BOM) for the complete two-stage LNA.

Figure 8: Top view of 5 GHz LNA PC board. Figure 9: Bottom view of LNA PC board.

Figure 10: Close-in shot of PCB showing compo-nent placement.

ABOUT THE AUTHORGerard Wevers is a wireless applications

engineer in silicon discretes for InfineonTechnologies North America Corp.(www.infineon.com). He received hisB.S.E.E. degree from the University ofCalifornia, Davis, and his M.S.E.E. fromSanta Clara University. Weavers can bereached at [email protected].

Continued on page 22


Figure 11: Cross-section diagram of the LNA printed circuit board. The spac-ing between the top layer RF traces and internal ground plane is 0.010 inches(0.254 mm).

Figure 12: Noise figure plot for a single-stage 5 GHz LNA made with engi-neering prototypes of the next-generation BFP740 SiGe transistor. Note the0.2 dB to 0.3 dB reduction in noise figure as compared to an existing BFP640.

Appendix A: Data on 12, two-stage BFP640 LNA circuit boards, 640-052402 Rev C, taken randomly from a batch of assem-bled units. All data taken at room temperature (25 C).


Forward gain, wide span (30 kHz to 6 GHz), at 25 C. Input return loss, log mag, narrow span, 5 GHz to 6 GHz, at 25 C.

Input return loss, narrow span, Smith chart, 5 GHz to 6 GHz, Referenceplane = PCB input SMA connector, at 25 C.

Forward gain, narrow span, 5 GHz to 6 GHz, at 25 C.

Appendix B: Data plots for the two-stage BFP640 5 GHz to 6 GHz LNA. From one sample PC board.


Appendix B: Continied

Reverse isolation, narrow span, 5 GHz to 6 GHz, at 25 C. Output return loss, log mag, narrow span, 5 GHz to 6 GHz, at 25 C.

Output return loss, narrow span, Smith chart, 5 GHz to 6 GHz, Reference plane = PCB SMA output connector, at 25 C.

RF Design www.rfdesign.com 27

Input stimulus for two-tone third order intercept test. Two tones, 5469.5 MHz and 5470.5 MHz, -23 dBm power per tone, at 25 C.

Two-stage LNA output response to two-tone test. Input third order intercept = -23 + ( 53.3/2) = +3.7 dBm, at 25 C.


Appendix C: Temperature test data for one sample unit.

Temperature test data for a singleLNA stage. The gain change versustemperature is approximately -0.008dB/degree C from -40C to +85C, or atotal of 1 dB gain change when goingfrom cold to hot for a single stage. TheDC current shift over the full tempera-ture range is 1.2 mA, or 16 percent.There is a slight degradation in outputreturn loss when hot.

Temperature test data for the com-plete two-stage LNA. The gain changeversus temperature is approximately -0.014 dB/degree C, or 1.8 dB total gainchange form cold to hot. The DC shiftcurrent over the full temperaturerange is 2.0 mA, or 13 percent.

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