4th sem report

VISVESVARAYA TECHNOLOGICAL UNIVERSITYJnana Sangama, Belgaum - 580 014

A Project Report on“Design of High Speed Operational Amplifier

with different types of compensation techniques”

Submitted in Partial Fulfillment for the award of the Degree

MASTER OF TECHNOLOGYin

VLSI DESIGN AND TESTING

Submitted By

Mr. Abhishek C Math(USN:2BV13LDT02)

Under the guidance of

Dr. Rajashekar B. Shettar

DEPARTMENT OF ELECTRONICS AND COMMUNICATIONENGINEERING

B. V. BHOOMARADDI COLLEGE OFENGINEERING AND TECHNOLOGY HUBLI-31

2014-2015

B.V.BHOOMARADDI COLLEGE OFENGINEERING AND TECHNOLOGY HUBLI-31

CERTIFICATE

This is to certify that the Project report entitled “Design of HighSpeed Operational Amplifier with different types of compensationtechniques” is a bonafide work carried out by Mr. Abhishek C Mathbearing (USN:2BV13LDT02) as a part of VISVESVARAYA TECHNO-LOGICAL UNIVERSITY’S M.Tech in VLSI Design and Testing at B. V.Bhoomaraddi College of Engineering and Technology, Vidyanagar, Hubli forthe academic year 2014-2015.

Dr. Rajashekar B. Shettar Dr.Uma Mudenagudi Dr.Ashok ShettarGuide Head of the Department Principal

External VivaName of Examiners Signature with date

1) ..................

2)..................

DECLARATION

I Mr. Abhishek C Math, (USN:2BV13LDT02), student of 4thsemester M.Tech. in VLSI Design and Testing, B.V.Bhoomaraddi College ofEngineering and Technology, Hubli, hereby declare that under the supervisionof my guide Dr. Rajashekar B. Shettar, Department of Electronics andCommunication Engineering, B.V.Bhoomaraddi College of Engineering andTechnology, Hubli, have independently carried out the project entitled “ De-sign of High Speed Op Amp with different types of CompensationTechniques”, and submitted it in partial fulfillment for the award of Masterof Technology in VLSI Design and Testing by the Visvesvaraya TechnologicalUniversity,Belgaum, during the academic year 2014-2015.

Date:Place:HUBLI Mr.Abhishek C Math

3

ABSTRACT

This thesis presents the analysis and design of a high speed CMOS opamp with different types of compensation techniques which operates at 1.8Vpower supply using 130nm CMOS Technology. Here different types of com-pensation techniques are used for an op amp and compared the results.Theop amp designed is a two stage CMOS op amp. This op amp employs aMiller capacitor and is compensated with a Nulling resistor,Voltage bufferand Current buffer to remove the positive zero. The op amp is designed toexhibit a UGB of 1GHz and the corresponding Phase Margin of 600 with theCL = 1pF and DC gain of 55dB. The gain transfer function is derived foreach topology and approximate transfer function co-efficient are found thatallows accurate estimation of zeros and poles. This op amp is designed forhigh speed application.

ACKNOWLEDGMENTS

The sense of contentment and elation that accompanies the successfulcompletion of our project and its report would be incomplete without men-tioning the names of the people who helped us in accomplishing this.

I accord my sincere thanks our principal Dr. Ashok Shettar and Vice-Principal Prof.B.L.Desai for providing healthy environment in the college,which helped in concentrating on the task. I express a deep sense of gratitudeto our H. O. D. Dr. Uma Mudenagudi for providing the inspirationrequired for taking the project to its completion.

I express my deep sense of gratitude and earnest admiration for my guideDr. Rajashekar B. Shettar for their inspiring guidance and promisingsupport they gave during the course of completion.

I sincerely thank to our project coordinator Dr. Saroja Sidmal,forgreat support and encouragement

I sincerely thank Smartplay Pvt Technology,Bangalore for offeringthe Internship under the guidance of Dr. Ramesh. Karmungi and I alsothank Mr. Rakesh Sawant for the support and encouragement to pursuremy project work.

Last but not the least I like to thank all the staff members, teaching andnon - teaching staff for helping us during the course of the project.

I am deeply indebted to my family for their valuable and unfailing sup-port.

Mr. Abhishek C Math

Contents

1 Introduction 11.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Objective of the Project . . . . . . . . . . . . . . . . . . . . . 41.3 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Organization of the report . . . . . . . . . . . . . . . . . . . . 5

2 Literature Survey 62.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.2 Feedback circuit theory . . . . . . . . . . . . . . . . . . . . . . 62.3 Stability of Feedback Systems . . . . . . . . . . . . . . . . . . 82.4 Basic Frequency Compensation Techniques of Operational Am-

plifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.4.1 Parallel Compensation . . . . . . . . . . . . . . . . . . 112.4.2 Pole Splitting Single Miller Compensation (SMC) . . . 11

2.5 Other Multistage Operational Amplifier Compensation Tech-niques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.5.1 Nested Miller Compensation (NMC) and the Variants . 142.5.2 Single Miller FeedForward Compensation (SMFFC) . . 162.5.3 Nonstandard NMC Schemes . . . . . . . . . . . . . . . 172.5.4 No Capacitor Feed Forward (NCFF) . . . . . . . . . . 182.5.5 Negative Miller Capacitance Compensation (NMCC) . 19

3 Operational Amplifier Compensation Strategy 213.1 Origin of Right half Plane Zero . . . . . . . . . . . . . . . . . 223.2 Different types of Compensation Techniques . . . . . . . . . . 24

3.2.1 Nulling resistor . . . . . . . . . . . . . . . . . . . . . . 243.2.2 Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . 253.2.3 Current Buffer . . . . . . . . . . . . . . . . . . . . . . 25

iii

3.3 Advantages and Disadvantages with Current Buffer . . . . . . 263.4 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4 Two stage operational amplifier compensation techniques 284.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284.2 Miller Capacitance . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.1 Zero nulling resistor . . . . . . . . . . . . . . . . . . . . 334.2.2 Current buffer . . . . . . . . . . . . . . . . . . . . . . . 394.2.3 Voltage buffer . . . . . . . . . . . . . . . . . . . . . . . 47

5 Layout Design 495.1 What is layout design . . . . . . . . . . . . . . . . . . . . . . . 495.2 Variability and Mismatch . . . . . . . . . . . . . . . . . . . . . 51

5.2.1 Random Statistical Fluctuations . . . . . . . . . . . . . 515.2.2 Process Biases . . . . . . . . . . . . . . . . . . . . . . . 525.2.3 Systematic Variations . . . . . . . . . . . . . . . . . . . 52

5.3 Rules of MOS transistor matching . . . . . . . . . . . . . . . . 535.4 Layout Techniques . . . . . . . . . . . . . . . . . . . . . . . . 545.5 Multifinger Transistor . . . . . . . . . . . . . . . . . . . . . . 555.6 Symmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6 Simulation Results and Layout 646.1 Nulling Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.1.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 646.2 Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.2.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 656.3 Current Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.3.1 Step Response . . . . . . . . . . . . . . . . . . . . . . . 666.3.2 Settling Time . . . . . . . . . . . . . . . . . . . . . . . 676.3.3 Design Parameters . . . . . . . . . . . . . . . . . . . . 686.3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.4 Comparision . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7 Conclusion and Future scope 747.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747.2 Future Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Bibliography 76

APPENDIX A 79

List of Figures

1.1 Trends for transistor supply and threshold voltage scaling withadvancement in CMOS process technology [2] and [3]. . . . . . 2

1.2 Trends for transistor open-loop gain with CMOS process tech-nology progression [2] and [3]. . . . . . . . . . . . . . . . . . . 3

1.3 Trends for transistor transition frequency (fT) with CMOSprocess technology progression. . . . . . . . . . . . . . . . . . 4

2.1 General negative feedback . . . . . . . . . . . . . . . . . . . . 72.2 Basicl negative feedback . . . . . . . . . . . . . . . . . . . . . 92.3 Amplifier gain and phase versus frequency showing the phase

margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4 SMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.5 SMCNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.6 NMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.7 RNMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.8 MNMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.9 NGCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.10 SMFFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.11 NCFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Effect of positive zero and negative zero . . . . . . . . . . . . 223.2 Origin of positive zero . . . . . . . . . . . . . . . . . . . . . . 233.3 Nulling resistor . . . . . . . . . . . . . . . . . . . . . . . . . . 243.4 Voltage Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 253.5 Current Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 Block diagram showing general structure of a two-stage op-amp 294.2 Small signal model for nodal analysis of Miller compensation

of a two-stage op-amp. . . . . . . . . . . . . . . . . . . . . . . 30

vi

4.3 Pole-zero plot for a two-stage op-amp demonstrating pole split-ting due to the Miller capacitor . . . . . . . . . . . . . . . . . 31

4.4 Frequency response of the Miller compensation two-stage op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.5 A Miller compensated two-stage op-amp . . . . . . . . . . . . 334.6 Miller compensated op-amp with zero nulling resistor . . . . . 344.7 Small signal model of two stage op-amp with zero nulling resistor 354.8 Frequency response of the Miller compensated two-stage op-

amp with zero nulling resistor . . . . . . . . . . . . . . . . . . 364.9 A two-stage op-amp with a common-gate stage to feedback

the compensation current . . . . . . . . . . . . . . . . . . . . . 404.10 Small signal analytical model for common-gate stage indirect

compensated two-stage op-amp . . . . . . . . . . . . . . . . . 414.11 Frequency response of a two-stage op-amp with a common-

gate stage when z=UGB . . . . . . . . . . . . . . . . . . . . . 454.12 Pole-zero location of two stage op amp with current buffer

compensation technique . . . . . . . . . . . . . . . . . . . . . 464.13 Design plan of a two-stage op-amp with a common-gate stage 474.14 Op-amp with an NMOS Voltage Buffer. . . . . . . . . . . . . . 48

5.1 Various two-dimensional effects causing sizes of realized micro-circuit components to differ from sizes of layout masks. . . . . 53

5.2 Example Cell Template . . . . . . . . . . . . . . . . . . . . . . 555.3 Fingering Of Transistors . . . . . . . . . . . . . . . . . . . . . 565.4 Example Of Fingering A NAND Gate . . . . . . . . . . . . . . 575.5 Transistor Power Sharing Example . . . . . . . . . . . . . . . 585.6 Example Of Soft Connections . . . . . . . . . . . . . . . . . . 585.7 (a)Simple Folding Of A MOSFET,(b) Multiple Fingers . . . . 595.8 Differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . 595.9 Layout Of MO And M1 With Different Orientation . . . . . . 605.10 Layout With Gate-Aligned Devices . . . . . . . . . . . . . . . 605.11 Layout With Parallel-Gate Devices . . . . . . . . . . . . . . . 615.12 Interdigitized layout of a differential pair a) Differential pair b)

Horizontal expansion c) Interdigitized layout (Drain areas aredifferent. Common centroid.) d) Interdigitized layout (Drainareas are equal. Not common centroid.) . . . . . . . . . . . . . 61

5.13 Gradient of KP on a wafer . . . . . . . . . . . . . . . . . . . . 625.14 Common-centroid layout of a differential pair . . . . . . . . . 62

5.15 Common-centroid examples . . . . . . . . . . . . . . . . . . . 63

6.1 Two stage op amp with Nulling Resistor . . . . . . . . . . . . 656.2 AC response of the two stage op amp with the Nulling resistor 666.3 Two stage op amp with Voltage Buffer . . . . . . . . . . . . . 676.4 AC response of the two stage op amp with the Voltage buffer . 686.5 Two stage op amp with Current Buffer . . . . . . . . . . . . . 696.6 AC response of the two stage op amp with the Current buffer 706.7 Step Response of two stage op amp with Current buffer . . . . 706.8 Slew Rate of two stage op amp with Current buffer . . . . . . 716.9 Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 716.10 Layout of the two stage op amp with the Current buffer . . . . 73

List of Tables

3.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 Summary of Two stage op amp with nulling resistor . . . . . . 656.2 Summary of Two stage op amp with voltage buffer . . . . . . 666.3 Variation of settling time of op amp with different tolerance

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676.4 Design Parameters . . . . . . . . . . . . . . . . . . . . . . . . 686.5 Summary of Two stage op amp with current buffer . . . . . . 696.6 Comparison of different types of compensation technique of

two stage op amp . . . . . . . . . . . . . . . . . . . . . . . . . 72

ix

Chapter 1

Introduction

Operational Amplifiers are one of the indispensable blocks of modernintegrated systems and are used in wide varieties of circuit topologies likedata converters, filters, references, clock and data recovery circuits. How-ever, continued scaling in CMOS processes has continuously challenged theestablished paradigms for operational amplifier (op-amp) design. As the fea-ture size of CMOS devices keeps shrinking, enabling yet faster speeds, thesupply voltage is scaled down to enhance device reliability and to reducepower consumption. The expressions for a short channel MOSFET transi-tion frequency(fT ) and open loop gain (gmr0) are given as [1]

fT ∝VovL

(1.1)

gmr0 ∝L

Vov(1.2)

where Vov, L, gm are the overdrive voltage, channel length, transconduc-tance and output resistance respectively for a MOSFET

From Equations 1.1 and 1.2, it can be observed that downward scalingin gate length results in a larger (fT ), and hence faster transistors. But thehigher speed comes at the cost of a reduction in transistors open loop gain.Hence the amplifiers designed with scaled processes exhibit larger bandwidthsbut lower open loop gains. Also with device scaling the supply voltage hasalso been continually reduced. However, the threshold voltage of transistorsdoesnt scale well in order to keep transistor leakage under control. Thiswill eventually preclude gain enhancing techniques like cascoding (vertically

1

Design of High Speed Op Amp with different Compensation Techniques

stacking transistors to increase gain) of transistors and gain-enhancement byemploying amplifiers in cascode configuration [1]. Figure 1.1 displays thetrend in scaling of transistor supply voltage (VDD) and digital and analogthreshold voltages with process technology or production year. The trendshave been compiled by combining data from the 2006 ITRS report update[2] and the predictive sub-45nm device modeling [3].

Figure 1.1: Trends for transistor supply and threshold voltage scaling withadvancement in CMOS process technology [2] and [3].

From Figure 1.1, it can be observed that the NMOS transistor thresholdvoltage (VTHN) is not projected to scale while the VDD will scale downcontinually. Also the VDD for digital process is set to scale more than theanalog VDD, which will make seamless integration of analog circuits difficultin digital processes.

Figure 1.2 shows the reduction in open-loop gain with process scaling.The open loop gain value of around to value in 100s in AMIs 0.5µm processhas dropped to 10s in the sub-100 nm processes. Also with scaling, theprocess variations become more pronounced as indicated by the expressionfor the threshold-voltage mismatch σ ∝ 1

LWgiven by [2]

σ∆V TH ∝1

LW(1.3)

Department of Electronics & Communication Engineering, B.V.B.C.E.T., Hubli - 31. 2


Figure 1.2: Trends for transistor open-loop gain with CMOS process tech-nology progression [2] and [3].

This leads to significant random offsets in op-amps due to the devicemismatches.

Figure 1.3 shows the projected enhancement in the peak fT of the devicesin upcoming CMOS process technologies, which is a desirable progression.Now, for an N bit resolution ADC, the open loop DC gain (AOLDC) of theop-amp required is given as

1.1 Problem Statement

To design the high speed two stage operational amplifier with different typesof compensation techniques like nulling resistor, voltage buffer and currentbuffer liwith UGB of 1GHz and dc gain of 55dB and compare the results.The design is to be implemented using 130nm technology in MentorGraphicstool.

Tool: MentorGraphics Pyxis Schematic tool, Maxima



Figure 1.3: Trends for transistor transition frequency (fT) with CMOS pro-cess technology progression.

1.2 Objective of the Project

To design the low power, high speed two stage operation amplifier with dif-ferent types of compensation techniques in 130nm technology.Performance of an op amp depends on numerous electrical characteristicse.g., GBW,slew rate common mode range output swing offset etc. Two stageoperational amplifier are often used to achieve both high dc gain and largeoutput voltage swing. These op amps require frequency compensation. Acurrent buffer in series with miller capacitor is one of the possible solutions.It is very efficient both for PSRR and GBW and does not reduce the op ampoutput swing unlike the voltgae buffer approach. This approach also givesa trade off between power consumption and area of compensation circuitby reducing the required value of compensation capacitor which suited wellwhere the heavy capacitive load must be driven. Ability to use smaller Ccprovides a higher degree of freedom in trading noise performance with powerconsumption .

.



1.3 Methodology

Literature survey of the amplifier architectures is carried out after goingthrough various papers. All the devices used in the design were characterizedand the required parameters like threshold voltage Vth,VDS and VGS of atransistor were extracted. After under-standing the working of amplifier,basic circuits were simulated with ideal conditions and specifications. Laterwith these specifications, the circuits are designed in MentorGraphics andsimulated using Edlo tool. The schematic and symbol representation formajor units of amplifier namely differential amplifier, current mirror is doneand the behaviour of each unit is verified by AC analysis.

1.4 Organization of the report

Chapter 1 - Deals with the project definition, objective and specifications ofthe project.Chapter 2 - Gives the Literature Survey of different types of compensationtechniques.Chapter 3 - This chapter deals with Compensation strategy and origin of thepositive zeroChapter 4 - Deals with the design of the two stage op amp with the differenttypes of compensation techniques.Chapter 5 - Deals with the Layout design concepts.Chapter6 - This chapter deals with Result Analysis of different types of com-pensation techniques and compared there results.


Chapter 2

Literature Survey

2.1 Introduction

Feedback is a powerful technique that finds wide application in analog cir-cuits. The high gain from amplifiers ensures the closed loop transfer charac-teristics with negative feedback are independent of the Op Amp gain. How-ever, an adequate gain is a key requirement to utilize this technique.

2.2 Feedback circuit theory

Figure 2.1 shows a general negative feedback system [7], where H(s) and G(s)are called the feedforward and the feedback networks, respectively. Since theoutput of G(s) is equal to G(s)Y(s), the input to H(s), called the feedbackerror and output are given by

E(s) = X(s)−G(s)Y (s) (2.1)

Y (s) = H(s)[X(s)−G(s)Y (s)] (2.2)

Thus

Y (s)

X(s)=

H(s)

1 +G(s)H(s)(2.3)

The quantity H(s) is the open loop transfer function and Y(s)/X(s) is theclosed loop transfer function. H(s) represents the operational amplifier and

6


Figure 2.1: General negative feedback

G(s) is a frequency independent quantity. In other words, a fraction of the outsignal is sensed and compared with the input and generating an error term.In negative feedback system, the error term is minimized, thereby makingthe output of G(s) an accurate copy of the input and hence the output of thesystem is an accurate replica of the input [7]. Feedback circuits provide gaindesensitization, i.e. the closed loop gain is much less sensitive to the openloop gain [5]. This property can be quantified as following

Y

X=

A

1 + Aβ≈ 1

β(1− 1

Aβ) (2.4)

where A and β are the low frequency gain of H(s) and G(s) respectively,and the dc gain Aβ >> 1. It can be noted that the closed-loop gain isdetermined, to the first order by the feedback factor, β. More importantly,even if the open-loop gain, A, varies by a factor of 2, Y/X varies by a smallpercentage because 1/(Aβ) << 1. The quantity Aβ is called the loop gain.The loop gain plays an important role in feedback system. As seen fromEquation 2.4 that the higher Aβ is, the less sensitive Y/X will be to thevariation in A. From another perspective, the accuracy of the closed-loop gainimproves as the open loop gain or feedback factor are maximized. However,as the feedback factor is increased, the closed loop gain decreases Y/X≈1/β,so there is an inherent trade-off between precision and the closed loop gain.



Negative feedback also exhibit effects on the bandwidth of the amplifier.Certain configurations of a feedback amplifier extend the closed bandwidthof the amplifier beyond the open loop amplifier. Assuming the feedforwardamplifier in Figure 2.1 has a single transfer function as given below

H(s) =A0

1 + sω0

(2.5)

where A0 denotes the low frequency gain and ω0 is the 3-dB bandwidth.The transfer function of the closed loop system can then be expressed as

Y (s)

X(s)=

A0

1+βA0

1 + s(1+βA0)ω0

(2.6)

The numerator in Equation 2.6 is the closed loop low frequency gainequivalent Equation 2.4. The denominator provides the location of the poleat (1 + βA0)ω0 Comparing this to Equation 2.5 the 3-dB bandwidth hasincreased by a factor of (1+βA0). The extended bandwidth comes at the costof proportional reduction in the gain as the product of gain and bandwidthis a constant for such an operational amplifier. Another very importantproperty of negative feedback is the suppression of nonlinearity in analogcircuits [8]. Nonlinearity can be regarded as the variation of the small signalgain with the input dc level. Negative feedback keeps the overall closedloop gain nearly constant and almost independent of the amplifier open loopgain. Therefore negative feedback circuits reduce distortion resulting fromthe change in the slope of the amplifier transfer curve. Mathematical analysisof the effect of a feedback system on nonlinearity of a circuit is very complexand can be found in [3, 5].

2.3 Stability of Feedback Systems

Negative feedback finds diverse application in processing of analog signals.The properties of feedback described in section 2.2 allow precise operationsby suppressing variations of the open loop characteristics. However, feedbacksystems suffer from potential instability, that is, they may oscillate.

Considering the negative feedback system shown in Figure 2-2 the closedloop transfer function can be written as



Figure 2.2: Basicl negative feedback

Y (s)

X(s)=

H(s)

1 + βH(s)(2.7)

IfβH(s = jω1) = −1, then from observing Equation 2.6 the gain goesto infinity and the circuit starts to amplify its own noise until it eventuallybegins to oscillate. This condition can be expressed as

|βH(jω1)| = 1

6 βH(jω1) = 1800

which are called the Barkhausens Criteria. It can be observed that thetotal phase shift around the loop at ω1 is 3600 because the negative feedbackintroduces itself a 1800 of phase shift. The 3600 of phase shift is requiredfor oscillation as the noise has to shift by 1800 to be in phase with thesignal to add. The other condition on loop gain being unity or greater isrequired to enable the growth of the oscillation amplitude. The conditionnecessary and sufficient for negative feedback stability is that all the poles ofthe feedback system are have a negative and real part. This from Laplacescriteria translates to the poles being on the left half side of the plane. It maybe difficult to analyze the stability of a complex system from looking at theclosed loop poles of the system, since finding the zeros of the denominator1+



βA(s) may be complicated. It would be therefore much useful if the closedloop stability could be predicted from observing the open loop response ofthe amplifier.The concept of phase margin for an open loop amplifier is good indicatorof the stability of the closed loop system. From the Nyquist criterion If|A(jω)| > 1 at the frequency where ph A(jω) = 1800, then the amplifieris unstable. Figure 2-3 shows the loop gain magnitude |A(jω)| is unity atfrequency ω0. At this frequency the phase of A(jω) has not reached −1800

for the case shown, and using the Nyquist criterion state we conclude thatthis feedback loop is stable.//

Figure 2.3: Amplifier gain and phase versus frequency showing the phasemargin

As |A(jω)| is made closer to unity at the frequency where ph A(jω) =−1800, the amplifier has a smaller margin of stability, and this can be speci-fied in two ways [9]. The most common is the phase margin, which is definedas follows: Phase margin = 1800 + (ph A(jω) at frequency where |A(jω)| =1). The phase margin is indicated in Figure 2-3 and must be greater than 00

for stability. [3]



2.4 Basic Frequency Compensation Techniques

of Operational Amplifier

The single stage amplifiers are inherently stable and typically have excellentfrequency response assuming the gain bandwidth is ten times higher thanthe single pole. However, single stage amplifiers suffer from low dc gain andis even less for submicron CMOS transistors. In general, Op Amps requireat least two gain stages which introduce multiple poles in the frequency re-sponse. The poles contribute to the negative phase shift and may cause 6 FAto reach −1800 before the unity gain frequency. Therefore due to insufficientphase margin the circuit would oscillate. Thus the amplifier circuit needs tobe modified to increase the phase margin and stabilize the closed loop circuit.This process is called gcompensationh. By intuition, two different approachesmay be taken to stabilize the loop. The more straightforward approach wayis make the gain drop faster in order for the phase shift to be less than −1800

at the unity gain frequency. This approach achieves stability by reducing thebandwidth of the amplifier and the most popular pole splitting method usesthis procedure. Another compensation method pushes the phase crossoverfrequency out by decreasing the total phase shift. In this particular case thetotal number of poles needs to be reduced while still maintaining the dc gain.This is achieved by introducing zeros into the open and close loop transferfunction to cancel the poles, or using feedforward paths to improve the phasemargin without narrow-banding the bandwidth as much as the pole splittingdoes.

2.4.1 Parallel Compensation

Parallel compensation is a classical way to compensate the Op Amp. Acapacitor is connected in parallel to the output resistance of a gain stage ofthe operational amplifier to modify the pole. It is not commonly used in theintegrated circuit due to the large capacitance value required to compensatethe Op amp, which considerable die area.

2.4.2 Pole Splitting Single Miller Compensation (SMC)

Early in 1967, Widlar designed the LM101/741 [18] op amp which employedthe pole splitting frequency compensation method. This method was first



used in Bipolar architecture and widely imitated in later CMOS op ampdesigns. In 1974, Solomon reported a tutorial study on the monolithic op amp[2] and discussed the pole splitting technique. By putting a compensationcapacitor between the input and output nodes of the second inverting stageof the op amp, the dominant pole is created due to Miller [15] feedback. Thismethod maintains a high midband gain for the op amp since the capacitordoes not affect the dc response of the amplifier. Fig. 2.3 shows the standardSMC topology.

Figure 2.4: SMC

As the transistor gain of the second stage increases, the dominant polede- creases and the nondominant pole increases. In this way the two poles arebeing split apart and stabilize the feedback amplifiers by greatly narrowingthe bandwidth. This simple pole splitting method also introduces a righthalf plane zero which causes negative phase shift, as a result, the stabilityis made a little poorer. The zero comes from the direct feedthrough of theinput to the output through the Miller capacitor. To eliminate the RHP zerodue to the feedthrough and increase the phase margin of the op amp, leadcompensation which adds a nulling resistor in series with the compensationcapacitor (SMCNR) to increase the impedance of the feedthrough path isreported [4, 15]. Leung and Mok investigated the effect of the nulling resistorto the positions of the poles as well as that of the zero and pointed out the pole



splitting would break down if the resistor becomes too big. When the resistorgets very large, there is no pole splitting since the compensation capacitor isactually open circuit. Fig. 2.4 shows the popular SMCNR structure.

Figure 2.5: SMCNR

2.5 Other Multistage Operational Amplifier

Compensation Techniques

Many gain boosting schemes have been reported [5] to improve the gain.In general, these gain enhancing designs require more complicated circuitstructure and a larger power supply voltage, but generate smaller outputswing. As a result, multiple stage amplifiers might be more suitable forlow power, low voltage, high density analog circuit designs. The frequencyresponse of the multistage amplifier is not as good as that of the single stageand this amplifier has a higher probability of oscillation in feedback circuits.One popular way to predict the closed loop stability is by measuring thephase margin of the open loop gain response. PM must be greater than 00

for no oscillation to occur. A good performing amplifier will need a PM ofabout 450 to 600. Otherwise, the amplifier may exhibit ringing in the timedomain and peaking in the frequency domain [15].



2.5.1 Nested Miller Compensation (NMC) and the Vari-ants

Multistage amplifiers have more poles and zeros than do single stage ampli-fiers. The frequency response and time response are far more complicatedthan those of the single stage op amps. As a result, all multistage amplifierssuffer closed loop stability problems. Single Miller compensation is used forthe simple two-stage amplifier; while the extended version of the SMC com-pensation, nested Miller compensation (NMC) [15] is applied to amplifierswith three or more stages. Because of the rapid bandwidth reduction, opamps with more than four stages are rarely investigated. NMC exploits thenested structure of feedback capacitors to cause the pole splitting compensa-tion. There are some drawbacks related to the NMC approach. The total ofN-1 nested compensation capacitors must be placed between the dominantnode and the other nodes to split the individual poles from the dominantoutput pole to stabilize an N stage op amp.Fig. 2.5 shows the structure ofa three stage NMC op amp. The nesting topology of the compensation ca-pacitor reduces the bandwidth substantially [5]. The specific configurationrequires the compound noninverting gain stages to connect to the invertingoutput stage in order to secure negative feedback for the nested compensa-tion loops. The necessity to drive the compensation capacitors along withthe capacitive load requires the output stage to have a high transconductanceto attain wide bandwidth and high slew rate. Consequently, elevated powerconsumption is unavoidable especially for large load capacitor.

To address the bandwidth degradation problem, the variations of theNMC are developed. NMC using nulling resistor (NMCNR) [4, 15], reversednested Miller compensation (RNMC) [19], multipath NMC (MNMC) [5],hybrid NMC (HNMC) [5], nested Gm-C compensation (NGCC) have beenpresented. RNMC improves the bandwidth over NMC by the reversed com-pensation topology compared to NMC as shown in Fig. 2.6. The RNMCtechnique sets the second gain stage negative and the output stage positive.The Miller capacitor loop is around the second stage without connection tothe considerable output capacitive load. HNMC combines the NMC and theRNMC topological properties in a multistage (above three) op amp. In thiscircumstance, the circuit could consist of only inverting amplifier except forthe input stage. The difference between NMC and MNMC is the added feed-forward amplifier stage -Af1 connected between the input of the first stageand the input of the last stage of the multistage op amp as shown in Fig.



Figure 2.6: NMC

2.7.The feedforward stage added can produce a LHP zero to counteract thesecond nondominant pole to broaden the bandwidth. The increased circuitcomplexity and power consumption should be considered. Moreover, the polezero doublets may seriously degrade the settling time of the amplifier.

The difference between NGCC and MNMC is that NGCC replicates thefeed- forward Gm (N-1) times for an N stage op amp recursively as shown inFig. 2.8 . Compared to MNC, NGCC has simpler stability conditions dueto the much simpler transfer function which makes the op amp design morefacile.

The basic idea of most of these variations of the NMC schemes is notto drop the overall bandwidth of the multistage amplifiers by the pole zerocancellation in the passband caused by the feedforward path of the multipathtopology. All of those compensation techniques mentioned above use Millercapacitors whose sizes are related to the load capacitor value. The requiredsizes of the compensation capacitors would escalate with larger capacitiveloads which make these techniques not suitable for low area need. The ex-perimental results of the varied versions of NMC showed that the bandwidthdoes not get improved significantly for considerable capacitive loads [19].



Figure 2.7: RNMC

2.5.2 Single Miller FeedForward Compensation (SMFFC)

Many compensation techniques mentioned above are not suitable for largeload capacitors. The demand for lower power consumption, lower chip inte-gration area, capability for driving large capacitive loads, and stable high gainbandwidth of amplifiers calls for improved frequency compensation patterns.The topologies using a single Miller capacitor in three stage amplifiers couldgreatly reduce the needed sizes of the compensation capacitors compared toNMC related schemes and result in amplifiers with smaller chip area. Thepresented SMFFC and the modified SMC with the additional feedforwardpath from the output of the first stage to the output load stage are designedfor a particular three stage amplifier specifically in the case of large capaci-tive loads. The topology of the SMFFC op amp is represented in Fig. 2.9.Instead of using pole zero cancellation, SMC with one forward path adoptsthe separate pole approach [12] for compensation in the situation of largecapacitive loads.SMFFC employs two forward paths and provide a LHP zeroto compensate the first nondominant pole to alleviate the bandwidth reduc-tion and improve the phase margin. The strictly rational selection of gainsamong the three stages is the key point for this SMFFC scheme. For the gaindistribution like Av1 >> Av2 >= Av3, the second and third poles of theamplifier would be placed at higher frequencies that lead to a coarse single



Figure 2.8: MNMC

pole system for an easier frequency compensation strategy. The appropriateselection of the moderate gain of the second stage will then decrease the com-pensation capacitor size. Unfortunately, this method does not truly resolvethe compressed gain bandwidth issue due to the super high gain of the firststage and the nature of the pole separation. Gain enhanced feedforward pathcompensation (GFPC) [10] is much like the modified SMC version with onefeedforward path, but for two stage amplifiers.

2.5.3 Nonstandard NMC Schemes

The nonstandard NMC topologies have been investigated to deal with thedrawbacks with the NMC and MNMC in order to be able to drive largecapacitive loads. The reported strategies include damping factor control fre-quency compensation (DFCFC) [3], embedded RC compensation (ERC) [2],active feedback frequency compensation (AFFC) [31], and dual loop parallelcompensation (DLPC) [32, 33]. The ERC duplicates the RC compensationprocess N-2 times for an N stage op amp. ERC compensation circuits donot load the output stage as NGCC circuit do. The noninverting gain stagesare not necessary in ERC as in NMC or the standard variations of NMC.ERC topology extends the bandwidth via the zero pole cancellation throughthe embedded compensation network without connection to the output load.



Figure 2.9: NGCC

Usually ERC uses a low gain, high conductance output stage to have thesimilar load- ing isolation benefit as the buffer output stage of the Widlar ar-chitecture.DFCFC can substantially improve the bandwidth of a three stageamplifier with good frequency and transient responses when driving largecapacitive loads. But it is not so effective for small capacitive load applica-tions. Some other compensation methods turn out to be more suitable thanDFCFC when driving a small capacitive load.

2.5.4 No Capacitor Feed Forward (NCFF)

One feedforward compensation scheme for multistage operational transcon-ductance amplifiers with no Miller capacitors is proposed by Thandri andSilva- Martinez [3]. This NCFF method applies the feedforward path asshown in Fig. 2.10 to create LHP zeros. By using the positive phase shift ofLHP zeros to cancel the negative phase shift of the poles, a high gain, highbandwidth amplifier with a good phase margin is developed. Thandri doesmention some design considerations of the NCFF in the paper. For example,the feedforward and second stage must place the nondominant poles after theoverall unity gain frequency of the amplifier to alleviate phase deduction;the pole zero cancellation should happen at high frequencies to achieve bettertime domain response. Some other constraints of the NCFF scheme not



Figure 2.10: SMFFC

directly specified in the paper should also be recognized.The NCFF is notsuit- able for big capacitive loads as a result of the main design considerationmentioned. The transient response might be degraded severely by the pole-zero doublets. A good performing amplifier should have both good frequencyresponse and transient response. The complexity of the presence of extrapoles and zeros can cause the design of the NCFF scheme to be very difficultand the undesired low frequency pole-zero doublets may lengthen the settlingtime of the amplifier or even make the closed loop unstable.

2.5.5 Negative Miller Capacitance Compensation (NMCC)

The negative Miller capacitance compensates high speed CMOS op amps thatconsists of an operational transconductance amplifier (OTA) and a buffer.The buffer with a dc gain of A is used to detach the OTA from the load.The OTA is compensated with a capacitor Cc connected between the inputand output of the buffer. Assuming the op amp drives a load with a parallelcombination of a resistor RL and a capacitor CL. the effective capacitanceseen at the input of the buffer is Cin = Cc(1-A) and Cout = CL+Cc(1-1/A) at the output of the buffer. Since the gain of the buffer is positive andsmaller than one, the reflected Miller capacitor Cc(1- 1/A) at the output willbe negative. The total effective output capacitance is reduced to be smaller



Figure 2.11: NCFF

than the original load capacitance due to the negative Miller capacitance.NMCC can be applied to drive a large capacitive load. The experimentalresults show that the NMCC design shifts the first nondominant pole to ahigher frequency while keeping the position of the dominant pole almost thesame. This NMCC scheme could increase both the bandwidth and phasemargin. Comer et al. [3] proposed a CMOS amplifier bandwidth extensionmethod by utilizing a negative capacitance circuit. Negative capacitance canbe generated by active circuitry using the Miller effect. The limitations ofcurrent IC technologies restrain the use of inductors and only small capaci-tors are available. With the innovative negative capacitor idea, compensationpractice could shape the frequency response with more freedom.


Chapter 3

Operational AmplifierCompensation Strategy

The two stage Operational Transconductance Amplifier(OTA) is a widelyused analog building block.Indeed,it identifies a very simple and robist topol-ogy which provides good values for most of its electrical parameters such asdc gain, output swing, linearity, CMRR, etc. To avoid closed loop instabil-ity, frequency compensation is a necessary in op amp design. For two stageCMOS op amp, the simplest compensation technique is to connect a capac-itor across the high gain stage.This results in the pole splitting phenomenawhich improves the closed loop stability significantly.However , due to feed-forward path through the miller capacitor, a right half plane (RHP) zero idalso created.

An uncompensated right half plane zero drastically reduces the maximumachievable GBW, since it makes a negative phase contribution to the openloop gain at a relatively high frequency. In order to compensate the right halfplane zero, an appropriate design approach is essential.Such a zero can benullified if the compensation capacitor is connected in conjunctin with eithera nullifying resistor or a common gate current buffer.After compensation ofright half plane zero, the maximum gain bandwidth is limited by second pole.

21


3.1 Origin of Right half Plane Zero

To understand what a positive zero means, we have to compare the effect onthe phase of a positive zero, with that of a negative zero which is shown inFigure 3.1. There is no need to have a second-order system for this purpose.A first-order system can be taken as well. The Bode diagrams are sketchedfor a first-order system with one single pole and one single zero. In thesecond case the zero is positive. Both have obviously the same amplitude.Consequently, amplitudes are not affected by signs.They have a very different phase characteristic, however. In the first Bodediagram the phase returns to zero for high frequencies. For the second dia-gram however, for a positive zero, the phase goes to 1800. This is like havinga second pole, rather than a zero! This completely ruins our phase margin!!!We have tried to limit the phase contribution of the non-dominant pole toabout 200 by carefully locating this non-dominant pole beyond the GBW. Apositive zero now shows up, which brings in another 900. This will ruin thephase margin. Moreover, the larger we make the compensation capacitanceCc, the more this zero shifts to lower frequencies. Large values of Cc aretherefore not allowed.

Figure 3.1: Effect of positive zero and negative zero

In order to understand how we can abolish the positive zero, we have to



try to understand what its origin is, which adds another 900 phase shift. Thisis a result of the feedforward through the compensation capacitance. Indeed,the compensation capacitance is bidirectional after all, as most capacitances.This means that feedback current and feedforward current flow at the sametime.The feedback current is the Miller effect current from output to input asshown in Figure 3.2. It flows between two nodes which are opposite in phase.The feedforward current is only easy to see when we leave out the amplifieritself. We now notice a feedforward current through Cc which causes a smalloutput signal which is in phase with the input. This is the current whichcauses the zero. It is a positive zero because it provides an output signalwhich is of opposite phase compared with the amplified output signal. Toabolish this positive zero, we have to make that compensation capacitanceunidirectional. In other words, we have to put a transistor in series, whichcuts the feedforward path.

Figure 3.2: Origin of positive zero

Various techniques for the compensation of the right half plane zero intwo stage CMOS op amp have been proposed and as well adopted. A com-pensation technique was proposed which uses nulling resistor in series withthe compensation capacitor. In an another solution a voltage buffer is intro-ducted in compensation branch which breaks the forward path. Both current



and voltage buffers can be adopted for compensation of the right half planezero due to their advantages over nulling resistor as it is more sensitive toprocess and temperature variation.

3.2 Different types of Compensation Tech-

niques

The three different types of compensation techniques are1.Nulling resistor2.Voltage buffer3.Current buffer

3.2.1 Nulling resistor

The most popular compensation technique is that based on the nulling resis-tor, since it can be implementated using only an MOS transistor biased inthe triode region. In this approach the left half plane zero introduced by thenulling resistor Rc in Figure 3.3

fz =1

2π

gm5

(gm5Rc− 1)Cc(3.1)

Figure 3.3: Nulling resistor

It is not so easy, however, to match a resistor to a gm value. Especiallyif the resistor is realized by means of a MOST in the linear region, then thematching is more difficult. There is a simple solution to this problem, how-ever. We increase the size of the resistor. This zero now turns into a negativezero. In other words the minus sign in the expression of the zero compen-sates the minus sign in the gain expression. This negative zero is positionedbetween the negative poles and can therefore be used to compensate one ofthem.



3.2.2 Voltage Buffer

The adoption of an ideal voltage buffer (i.e., with zero output resistance) tocompensate the right half plane zero gives the same second pole as in resistortechnique and hence the same UGB. Usually the simple common drain inFigure 3.4 is employed and connected between nodes. Taking into account forthe finite output resistance of the buffer which is about equal to 1/gm9, thecompensation branch introduces a left half plane zero at fz = gm9/2πCc.The approach based on nulling resistor and voltage buffer give the samecompensation capacitor and hence the same GBW. However, a voltage bufferin the compensation branch greatly reduces the output swing preventing itsuse in many practical cases.

Figure 3.4: Voltage Buffer

3.2.3 Current Buffer

The compensation based on current buffer as shown in Figure 3.5 is veryefficient both for GBW and the PSRR performance. It also does not havethe drawback of the voltage buffer which reduces the output swing.In this design approach value of Cc is much smaller. The ability to usesmaller provides a hig her degree of freedom in trading noise performance



with power consumption.For this purpose, the common gate in Figure 3.5can be used.

Figure 3.5: Current Buffer

3.3 Advantages and Disadvantages with Cur-

rent Buffer

Advantages:1. Good GBW.2. High PSRR.3. Improved slew rate.4. Area efficient(low Cc).5. Power and area trade off.6. Does not reduce output swing like voltage buffer.

Disadvantages:1. Increased offset.2. Additonal biasing current is required.



3.4 Specification

The Specification of the two stage Op Amp with compensation techniques isgiven in Table 3.1:

Table 3.1: SpecificationParameter Target

Supply Voltage 1.8VVin,cm 1.2V

DC Gain > 55dBUGB > 1GHzPM 60deg

Settling Time < 3nsCL 1pF

Technology 130nm


Chapter 4

Two stage operational amplifiercompensation techniques

4.1 Introduction

Two stage op-amps have been the dominant amplifier topologies used inanalog system design due their simple frequency compensation and relaxedstability criterions. The two-stage op-amps have conventionally been com-pensated using Miller compensation or Direct Compensation technique. Fig-ure 4.1 the shows block diagram of a twostage op-amp. The op-amp consistsof a diff-amp as the input stage. The second (gain) stage is biased by theoutput of the diff-amp which is followed by an output buffer. The optionaloutput buffer is used to provide a current gain when driving a large capacitiveor resistive load [3].

4.2 Miller Capacitance

Before compensation, the poles of the two-stage cascade are given as,p1 =1

R1C1and p2 = 1

R2C2, where Rk,Ck are the resistances and capacitances

respectively at nodes is employed to achieve pole splitting. In this technique,the compensation capacitor (Cc) is connected between the output of the firstand second stages. The compensation capacitor splits the input and outputpoles apart thus obtaining the dominant and non-dominant poles which arespaced far away from each other [18],[6]. However, Miller compensation alsointroduces a right-half-plane (RHP) zero due to the feed-forward current

28


Figure 4.1: Block diagram showing general structure of a two-stage op-amp

from the output of the first stage to the op-amps output. Figure 4.2 showsthe small signal model for twostage opamp used for nodal analysis.

The small signal transfer function for a Miller compensation two-stageopamp is given as,

V out

V s= gm1R1gm2R2

(1− sz1

)

(1− sp1)

(1− sp2

)(4.1)

The RHP zero is located at

z1 =gm2

Cc(4.2)

The dominant pole is located at

p1 =1

gm2R2R1Cc(4.3)

and the non dominant pole is located at

p2 =gm2Cc

CcC1 + C1C2 + CcC2≈ gm2

C1 + C2(4.4)

The open-loop gain of the op-amp is given asAv = gm1R1gm2R2, while theunity gain frequency (or gain-bandwidth) is given as UGB = gm1

2πCc



Figure 4.2: Small signal model for nodal analysis of Miller compensation ofa two-stage op-amp.

The pole splitting for the two-stage op-amp due to Miller compensationis illustrated

Figure 4-4 shows the frequency response of the Miller compensated two-stage opamp. Since the phase contribution due to the RHP zero is givenas − tan−1 f

fz1it degrades phase margin of the op-amp from 900 and leads

to instability when the second pole moves closer to the unity-gain frequency(UGB). Hence, not only the RHP zero flattens out the magnitude responseby cancelling the dominant pole roll-off, which is required to stabilize theop-amp, it also decreases the phase margin which makes the op-amp stabi-lization difficult.

Upon closer analysis of the origin of the RHP zero, the compensationcurrent (ic), flowing across the compensation capacitor (Cc) from outputnode to node-1, is given as ic= sCc(vout v1) = sCcvout sCcv1.The feed-forward component of this current,iff = sCcv1, flows from node-1 to theoutput, and the feed-back component, ifb = sCcvout, flows from the outputto node-1. The feed-forward current, iff, depends upon voltage v1, and sodoes the current at the output(=(gm2- sCc)v1).When the total current atthe output equals zero (i.e. frequency corresponding to z1 = gm2

Cc) , a RHP

zero appears in the transfer function. This RHP zero can be eliminated by



Figure 4.3: Pole-zero plot for a two-stage op-amp demonstrating pole split-ting due to the Miller capacitor

blocking the feed-forward compensation current, while allowing the feed-backcomponent of the compensation current to achieve pole splitting [8].



Figure 4.4: Frequency response of the Miller compensation two-stage op-amp

Several methods have been suggested in [7] and [6] to cancel the RHPzero in the two-stage op-amp and are described in the following sub-sections.A Miller compensated two-stage op-amp has been implemented with schematicas shown in Figure 4.5. The high speed op-amps have been designed to drivea typical load of 1pF. The op amp is designed in the 130nm technology inMentorGraphics.

The following sub-sections discuss methods widely used to eliminatethe detrimental effects of the RHP zero on the phase margin in the Millercompensated op-amps.



Figure 4.5: A Miller compensated two-stage op-amp

4.2.1 Zero nulling resistor

A common method to cancel the RHP zero is to use a zero nulling resistorin series with the compensation capacitance, as shown in Figure 4.6.

Small signal model of OTA

The below Figure shows the small signal model of the two stage OTA withthe nulling resistor.The circuit has the following nodal equations.

gm1V in+V 1

R1+ sC1V 1 + (

sCc

1 + sCcRz(V 1− V out)) = 0 (4.5)

gm2V 1 +V 0

R2+ sC2V out+ (

sCc

1 + sCcRz(V out− V 1)) = 0 (4.6)

These equations can be solved to give

V out

V in=a[1− s((Cc/gm2)−RzCc)]

1 + bs+ cs2 + ds3

(4.7)

where



Figure 4.6: Miller compensated op-amp with zero nulling resistor

a = gm1R1gm2R2

b = (C2 + Cc)R2 + (C1 + Cc)R1 + gm2R1R2Cc+RzCc

c = [R1R2(C1C2 + CcC1 + CcC2) +RzCc(R1C1 +R2C2)]

d = R1R1RzC1C2Cc

If Rz is assumed to be less than R1 or R2 and the poles are widely spaced,then the roots of the above transfer function can be approximated as

p1 =−1

(1 + gm2R2)R1Cc≈ −1

gm2R2R1Cc(4.8)

p2 =−gm2Cc

C1C2 + CcC1 + CcC2≈ −gm2

C2(4.9)

p3 =−1

RzC1(4.10)

and

z1 =1

Cc(1/gm1−Rz)(4.11)



Figure 4.7: Small signal model of two stage op-amp with zero nulling resistor

For Rz=1/gm2, the zero is pushed to infinity and for Rz¿1/gm2, the zeroappears in the left half plane (LHP). Thus for Rz=2/gm2, the RHP zero isconverted to an LHP zero of the same frequency location as that of the RHPzero. A LHP zero helps in improving the phase margin of the opamp andenhances stability.

A third pole is introduced at p3 which is far away from the second pole,p2, as C1 << C2 and Rz = 1/gm2 [6]. The location of the zero may varydepending upon the process variations in the resistor Rz, but this schemeis effective enough to keep the RHP zero from degrading the phase margin.The resistor Rz can be implemented using a transistor in triode region, andcan be made to track the value of 1/gm2 and cancel the RHP zero. Howeverthe biasing of this triode transistor may require additional power [4].

The small signal frequency response for this circuit is shown in Figure4.8. Here we can observe the improvement in phase margin (PM) from 750

to 890 by using the zero nulling resistor.

Maximum amd Minium Rz

In order to be effective, we have to position this zero close to the GBW, forexample at 10 times the GBW where the nondominant poles are. This yieldsa new expression for Rz, which is now related to gm1 instead of gm2. We



Figure 4.8: Frequency response of the Miller compensated two-stage op-ampwith zero nulling resistor

simply position Rz between both the values obtained, with preference to becloser to 1/10gm1.

Let us assume that z=10UGBWe know that

z1 =1

Cc(1/gm1−Rz)(4.12)

10UGB =1

Cc(1/gm1−Rz)(4.13)

By solving the above equation we get

1

gm2< Rz <

1

10gm1(4.14)

Optimum Design for High speed Miller OTA

The goal is to find out what maximum GBW can be reached within a certainCMOS technology. Also, we want to find the shortest way to design thisOTA. First of all, a number of design choices have to be made. They have allbeen previously used. We list them again and introduce design parameters



α, β and γ. The maximum GBW can now easily be described as a fractionγ of the non-dominant pole. Also, note that CL can be described in terms ofthe width of the output transistor. Obviously, the larger the CL, the morecurrent we will need to drive it, and the larger the transistor width becomes.We know

p2 =gm2Cc

C1CL+ CLCc+ CcCL(4.15)

Therefore

p2 =gm2

2πCL

1C1Cc

+ 1(4.16)

AssumeCL = αCc

Cc = βC1 = βCgs2

p2 = γGBW

GBW =p2

γ=

gm2

2πCLγ

11β

+ 1

GBW =2µCox(V gs− V t)

2πKL2

1

αβγ( 1β

+ 1)

therefore

GBW ∝ (V gs− V t)2

L2

From the above equation we can see that the maximum GBW does notdepend on the load capacitance.Actually, increasing the load capacitance increases the width of the outputtransistor and its current. The speed of the output transistor mainly dependson its length.The speed of a MOST is better represented by parameter fT. This is why wenow try to substitute the transistor parameters VGS-VT and L by parameterfT.

Design Procedure

The design procedure in a broader sense involves the following sequence ofsteps. Firstly selecting a specific topology, secondly determining the DCcurrents, thirdly calculating the W/L ratios of each transistor, at the end



deciding the passive component values used in the circuit.

The design procedure assumes that the DC gain(Av), unity-gain band-width (GB), Input common-mode range[Vin(min) and Vin(max)], Load ca-pacitance(CL), slew rate(SR), Settling Time(Ts), Output voltage swing[Vout(max)and Vout(min)] and Power dissipation(Pdiss) are given.

1.The smallest device length that will keep the channel modulation pa-rameter constant and give good matching for current mirrors has been chosen.2. From the desired phase margin, the minimum value for Cc is chosen ,thatis for a 600 phase margin. We have used the following relationship. Thisassumes that z > 10GB.

Cc > 0.22CL

3. The minimum value for the tail current (I5) from the largest of the twovalues is determined.

I5 = SR.Cc

4. Design of S3 from the maximum input voltage specification.

S3 =2I3

K3V DD − V in(max)− [V T3(max) + V T1(min)]2> 1

5. The pole and zero due to Cgs3 and Cgs4 will not be dominant by assumingpole p3 to be greater than 10GB.

gm3

2Cgs3> 10GB

6. Design for S1(S2) to achieve desired GB

gm1 = GBCc > S1 = S2 =gm2

K2I57. Design of S5 from the minimum input voltage.First we have calculated

VDS(Sat) and then we can find S5



S5 =2I5

K5[V DD(Sat)]2

8. Find S6 and I6 by letting the second pole (p2) be equal to 2.2 times GB.

Let Vsg4=Vsg6, which gives S6 = S4(gm6gm4

)

Knowing gm6 and S6 allows us to solve for I6 as I6 = gm62

2K6S6

9. Alternate;y, I6 can be calculated by solving for S6 using

S6 =gm6

K6V ds6(Sat)

And then using the previous relationship to find I6. The proper mirrorbetween M3 and M4 is no longer guranted.

10. Design of S7 to achieve the desired current ratios between I5 and I6.

S7 =I5

I6S6

11.The Rz is calculated as

z1 =gm6

Cc(1− gm6Rz)≈ − gm6

CL+ C1

Therefore

Rz =Cc+ CL+ C1

gm6Cc

4.2.2 Current buffer

A common-gate stage can also be used to block the feedforward current fromnode- 1 to the output node-2 [4]. Figure 4.9 shows a two-stage op-amp whichis indirect compensated using a common-gate stage. The transistor MCGacts as a common-gate amplifier which blocks the feed-forward compensa-tion current and allows the feedback compensation current to flow indirectly



from the output to the internal node-1. Such topologies are analyzed in thenext section, and they significantly improve the performance of the opampsdesigned. As the compensation current is fed back indirectly from the node-2(i.e. output node) to the node-1 in order to achieve pole splitting (and hencedominant pole compensation), the class of compensation technique is calledIndirect Feedback Frequency Compensation or simply indirect compensation.An analysis of the common-gate stage indirect compensated op-amp topologyis provided in the next section

Figure 4.9: A two-stage op-amp with a common-gate stage to feedback thecompensation current

Small Signal Model of two stage OTA with current buffer

In order to develop an insight into indirect feedback compensation, the op-amp topology indirectly compensated with common-gate stage is analyzed.The small signal model for the common-gate stage op-amp topology is shownin Figure 4.10

The model used for exact analysis has three nodes and hence three de-pendent variables, v1,vA and vout. Also in the model Vs=Vp-vin. A T-typesmall signal model is used to represent the common-gate device MCG [6].Here, the transconductance and output resistance of the common-gate de-vice (MCG) are denoted as gmc and roc respectively. Also RA and CA are



Figure 4.10: Small signal analytical model for common-gate stage indirectcompensated two-stage op-amp

the resistance and capacitance at the low impedance node-A. On applyingnodal analysis on the model shown in Figure 4.10, we obtain the followingset of equations

− gm1vs+v1

R1+ v1sC1− gmcva+

(v1− vA)

roc= 0 (4.17)

gm2v1 +vout

R2+ voutsC2 + sCc(vout− vA) = 0 (4.18)

(vA− v1)

roc+ gmcvA+ vAsCA+

vA

RA+ sCc(vA− vout) = 0 (4.19)

On simultaneously solving the above equations, we obtain the followingsmall signal transfer function

vout

vs= −Av(

b0 + b1s

a0 + a1s+ a2s2 + a3s3) (4.20)

The third order transfer function given by Equation 4.20 consists of areal LHP zero and three poles. The exact values of the transfer functioncoefficients are



Av = gm1R1gm2R2 (4.21)

b0 = (1 + gmcRA)roc+RA (4.22)

b1 = RA[roc(Cc+ CA) + gmcroc− Cc/gm2] (4.23)

a0 = (1 + gmcRA)roc+RA+R1 (4.24)

a1 = gm2R2gmcR1rocCcRA+gm2R2R1CcRA+gmcRAroc(R1C1+R2(C2+Cc))

+R1RA(Cc+CA)+RA(R1C1+R2C2)+R1R2(C2+Cc)+roc(R2Cc+RA(Cc+CA))

a2 = (gmcRA+1)R2C1R1roc(C2+Cc)+R2rocRACC(C2+CA)+R1R2CcRACA

+R2C2RA(R1)C1+Cc+CA)+rocCA)+R1C1RA(roc(Cc+CA)+R2C2).

a3 = R1C1R2rocRA(C2CA+ C2Cc+ CcCA) (4.25)

Applying yhe approximations gmkRk >> 1, C2 ≈ CL ;Cc,C2 >>C1,CA, we obtain the following modified transfer function coefficients,

b0 ≈ gmcRAroc

b1 ≈ RAroc(Cc+ CA)

a0 ≈ (gmcRA+ 1)roc

a1 ≈ gm2R2R1rocCc(gmcRA+ 1)

a2 ≈ (gmcRA+1)R2C1R1roc(C2+Cc)+R2C2RA[roc(Cc+CA)+R1(Cc+CA+C1)]

a3 ≈ R1C1R2rocRA(C2Ca+ C2Cc+ CcCA)

Using the numerator expression, we obtain the location of the zero to beat

z1 ≈ −b0

b1

= − gmc

Cc+ CA(4.26)



which is evidently an LHP zero.With the assumption that |p1| >> |p2|, |p3|,the dominant real pole is given as

p1 = −a0

a1

= − 1

gm2R2R1Cc(4.27)

Now for s >> p1, the non-dominant poles p2 and p3 are real and spacedapart when (a2

a1)2 >> 4a3

a1, see APPENDIX or

(a2)2 >> 4a3a1

The above condition is satisfied when

gmc >>4gm2Cc(C2||Cc+ CA)

C1(C2 + Cc)

This implies that the gm of the common-gate device (MCG) in Figure 4.9should be large. When the condition given by above Equation is satisfied,the non-dominant poles are given as

p2 ≈ −a1

a2

= − gm2Cc

C1(C2 + Cc)(4.28)

and

p3 ≈ −a2

a3

= − gmc

CA+ (C2||Cc)− C2/C1

R1||roc(C2 + Cc||Cc)(4.29)

The unity gain frequency of the op amp is given as

UGB =gm1

2πCc(4.30)

The second pole of Current buffer compensation is located at −gm2CcCLC1

while the second pole for Miller compensation was located at − gm2C1+CL

.Bycomparing the two expressions, we can observe that the second pole, p2, hasmoved further away from the dominant pole by a factor of approximatelyCc/C1.This factor of Cc/C1 comes to around 10’s in TSMC 130nm Tech-nology.Also the LHP zero adds to the phase response in the vicinity of UGBand enhance the phase margin.

This implies that we can achieve pole splitting with a much lower valueof compensation capacitor (Cc) and lower value of second stage transconduc-tance (gm2). Lower value of gm2 translates into low power design as the bias



current in second stage can be much lower. Alternatively, we can set highervalue of unity-gain frequency (fun) for the op-amp without affecting stabilityand hence achieving higher bandwidth and speed. Moreover, the load capac-itor can be allowed to be much larger for a given phase margin [9], [10]. Thehigher value of |p2| can be explained by the fact that the first stages output(i.e. node-1) is not loaded by the compensation capacitor [6]. In short, incan be trivially concluded that indirect feedback compensation can lead tothe design of op-amps with significantly lower power, higher speed and lowerlayout area.

The third pole (p3) doesnt move to lower frequency and interact withthe second pole (p2) as long as gmc is large and R1,C1 are smaller in value.

Looking at the case when the z=UGB and non-dominant poles are closeand form a conjugate pole pair when

gmc <4gm2Cc(C2||Cc+ CA)

C1(C2 + Cc)(4.31)

The real part of the of the conjugate pole pair(p2,3) is given as

Re(p2,3) = −√a1

a3

= −

√gm2gmc

C1[C2 + (1 + C2/Cc)CA]≈

√gm2gmc

C1C2(4.32)

and the damping factor ξ is given as

ξ =a2

2√a1a3

≈ 1

2Cc

√C1C2

gm2(4.33)

Also, we can observe that,

|Re(p2,3)| = gm2

CL

√gmcCL

gm2C1>gm2

CL(4.34)

which again re-affirms the fact that the values of 1/gmc and C1 shouldbe small in order to move p2,3 away from p1 as farther as possible.

The below Figure shows the Frequency response of the two stage op ampwhen z=UGB.



Figure 4.11: Frequency response of a two-stage op-amp with a common-gatestage when z=UGB

Design Plan

The Design procedure of two stage OTA with current buffer is same as withthe nulling resistor, the only condition is that here we are making

z = UGB

We are placing the zero exactly on the UGB so that zero adds the extraphase margin and gm1 = gmc. Here the non dominant poles are complexconjugate. The below Figure 4.12 shows the Design plan two stage op ampwith current buffer. The Figure 4.13 shows the pole-zero location of currentbuffer compensation technique.

The gm1 is calculated through the thermal noise spectral density. Theprocedure starts with the thermal noise requirement for the Op Amp. Ne-glecting the flicker noise requirement, which contributes to the low frequencynoise spectrum, the input referred noise voltage can be expressed as shownin Equation 4.35.

Sn(f) = 24̇kT2

3

1

gm1, 2[1 +

gm3, 4

gm1, 2] (4.35)

To minimize noise, we assume gm3,4 ¡ gm1,2 (which can be easily met)



Figure 4.12: Pole-zero location of two stage op amp with current buffercompensation technique

and calculate the transconductance gain of transistors M1,2 from Equation4.36

gm1, 2 =16

3

kT

Sn(f)(4.36)

Input referred noise is sometimes not a critical performance specification.In those cases, a more relaxed input referred noise voltage can be calculatedto obtain the input pair gm1,2. This requirement comes from comparingthe thermal noise of the capacitor at the output over the bandwidth of theamplifier. This gives the following requirement

vno

UGB=

√kT/C

UGB(4.37)

The input referred noise can then by a factor of 4-5 larger than thevalue of expression in Equation 4.37. Therefore approximatelySn(f) ≈(4-

5)√

kT/CUGB

.The larger the noise specification, the smaller the transconductance

of the input pair is required.



Figure 4.13: Design plan of a two-stage op-amp with a common-gate stage

4.2.3 Voltage buffer

A source follower can be used to block the feedforward compensation currentand allow the feedback compensation current to flow from the output tothe node-1. Figure 4.13 shows an op-amp topology with an NMOS sourcefollower. Notice the way the compensation current is fed back from theoutput to the node-1 in these op-amps. These topologies eliminates theRHP zero although at the cost of additional power and transistors. Also dueto the use of a source follower, there exists a fixed DC voltage drop, equal toVGS (or VSG for the PMOS buffer case) in the feedback signal path. Thisvoltage drop reduces the output swing, as a high output swing may triodethe source follower device and break down the compensation. The locationof the first pole remains the same as in the case of Miller compensation, andthe second pole also remains relatively unchanged atp2 ≈ −gm2

C2[6] The design

procedure for voltage follower is same as the nulling resistor.



Figure 4.14: Op-amp with an NMOS Voltage Buffer.


Chapter 5

Layout Design

Today, layout design is carried out in an environment that is ever chang-ing. The software tools and approaches, computing platforms, the companiesproviding these tools, the customers we serve, the applications that are be-ing implemented, and the market pressures we face are all changing year byyear. These changes make this industry an interesting one in which to beinvolved.[19] However, lets not forget that the fundamental concepts behindproducing quality layout are based on physical and electrical properties thatnever change

5.1 What is layout design

We define layout design as follows: The process of creating an accurate phys-ical representation of an engineering drawing (netlist) that conforms to con-straints imposed by the manufacturing process, the design flow, and the per-formance requirements shown to be feasible by simulation. Lets look at thisdefinition in greater detail as there are numerous implications buried within.

A process: First and foremost, layout design is a process with manysteps that should be followed in a logical order for optimal results. For ex-ample, the process of layout design may include setting up a database orsuite of tools with the appropriate layers; defining the oorplan of each cell orchip; and/or running verification checks in the proper order.

49


Creation: Design and creation are usually synonymous, and layout de-sign is no exception. Implementing one schematic in two different technolo-gies usually results in layouts that look quite different, thus demonstratingthe creative nature of the trade. In the same way, a schematic that will beused in two different regions of the chip may result in two different architec-tures, adapted to their geographical location.

Accuracy: Although layout design is a creative process, we must not for-get that the first requirement of the final layout must be that it is equivalenton a transistor- by-transistor basis to the engineering drawing. Redesigningthe configuration of transistors to improve the circuit is not the role of thelayout designer unless you plan to take over (or already have taken over) thecircuit design task as well.

Physical representation: CMOS ICs are made using an extremelycomplicated process that in the end results in tiny transistors and wires be-ing constructed and connected on a silicon substrate. Layout design is theart of drawing these transistors and wires as they look like in silicon; thus,the layout can be thought of as the physical representation of the circuit.Engineering drawing: This may sound a bit old-fashioned, but it is ac- cu-rate.

Transistor-level or gate-level schematics : have historically been theprimary drawing and in many companies they remain so. Fancier method-ologies these days result in some layout designers receiving a large text-basedfile called a netlist. However, in order for humans to understand a netlist,it is usually accompanied by a block-level schematic or drawing. Engineers(or equivalents) are the main providers of the drawings, but as the indus- trychanges this may change as well.

Conform: By conforming, we mean meeting the requirements of and notnecessarily the smallest or best design possible. There are many trade-off tobe made in the process of design: reliability, manufacturability, exibility,and (perhaps most importantly) time to market, to name a few. Of course,there are minimum requirements that have to be met, but to achieve the op-timal design at the expense of the project schedule is not practical in todaysmarketplace. Constraints imposed by the manufacturing process: Theseconstraints include layout design rules such as the smallest width a metal



track can be, but also many other manufacturability or reliability guidelinesthat will improve the overall quality of the layout. For example, in the case ofa metal track, a wider line may improve the manufacturability of the designand thus should be used where space permits.

Constraints imposed by the design flow: These constraints includeguidelines established to enable all other tools that are to be used in the de-sign ow to be able to eficiently use the completed layout. For example, somerouters like to have connections to cells on a regular pitch, while others donot care. Another example is the methodology to add text to layout so thatthe text can be used later for identification purposes. Constraints imposedby the performance requirements shown to be feasible by simulation: Anengineer completing a circuit design without detailed knowledge of how thecircuit will be implemented in layout is required to make some assumptions.For example, the engineer designing the circuit will not know the exact areaof the block without implementing the circuit in layout and so must make aneducated estimate based on the information available. The total area figuremay be important to know so that the maximum line length within the blockis also known. This normally cannot be avoided, and the trick is to try tocommunicate these assumptions and thus constrain the layout accordingly.In our example the total area estimate used by the circuit designer shouldalso be used by the layout designer as a target area, and differences from thisestimate on the low or high side should be fed back to the circuit designerfor re simulation.

5.2 Variability and Mismatch

When integrated circuits are manufactured, a variety of effects cause theeffective sizes and electrical properties of the components to differ from thoseintended by the designer. We may categorize these effects as being eithersystematic variations, process variations, or random variations.

5.2.1 Random Statistical Fluctuations

All components exhibit microscopic irregularities, or fluctuations. In the caseof a polysilicon resistor, the edges of the poly exhibit microscopic irregulari-



ties that give them a slightly ragged appearance. Some of these irregularitiesstem from the granularity of the polysilicon, while others result from im-perfections in the photoresist. The granularity of the polysilicon also causesvariations in poly thickness and resistivity.[19] Other types of devices exhibitdifferent types of fluctuations, but all of these fall into one of two categories:

fuctuations that occur only along the edges of the device and fuctuationsthat occur throughout the device. The former are called peripheral fuctu-ations because they scale with device periphery, while the latter are calledareal fluctuations because they scale with device area. The nature of thesescaling relationships can be deduced from statistical arguments.

5.2.2 Process Biases

The dimensions of geometries fabricated in silicon never exactly match thosein the layout database because the geometries shrink or expand during pho-tolithography, etching, diffusion, and implantation. The difference betweenthe drawn width of a geometry and its actual measured width constitutesthe process bias. Process biases can introduce major systematic mismatchesin poorly designed components.

5.2.3 Systematic Variations

When lithographic techniques are used, a variety of two-dimensional effectscan cause the effective sizes of the components to differ from the sizes of theglass layout masks. Some examples of these effects are illustrated in Fig. 5.1For example, Fig. 5.1(a) shows how an effective well area will typically belarger than its mask due to the lateral diffusion that occurs not just during ionimplantation but also during later high-temperature steps, such as annealing.Another effect, known as overetching, occurs when layers such as polysiliconor metal are being etched. Figure 5.1(b), for example, shows overetching thatoccurs under the SiO2 protective layer at the polysilicon edges and causesthe polysilicon layer to be smaller than the corresponding mask layout. Athird effect is shown in Fig. 5.1(c), where an -channel transistor is shownas we look along the channel from the drain to the source. The width ofthe transistor is defined by the width of the active region (as opposed to thewidth of the polysilicon line), and this width is determined by the separationof the isolation oxide between transistors (i.e. the field-oxide in a LOCOSprocess). The p+ field implant under the field-oxide causes the effective



substrate doping to be greater at the sides of the transistors than elsewhere.This increased doping raises the effective transistor threshold voltage near thesides of the transistors and therefore decreases the channel- charge densityat the edges. The result is that the effective width of the transistor is lessthan the width drawn on the layout mask.[20]

Figure 5.1: Various two-dimensional effects causing sizes of realized micro-circuit components to differ from sizes of layout masks.

5.3 Rules of MOS transistor matching

1. Place transistors in close proximity.2. Orient transistors in the same direction.3. Keep the layout of the transistors as compact as possible.4. Whenever possible use Common centroid layouts.5. Place transistors segments in the areas of low stress gradients.6. Place transistors well away from the power devices.7. For current matching keep overdrive voltage large.8. For voltage matching keep overdrive voltage smaller.



5.4 Layout Techniques

The following is a list of guidelines specifically for a cell-level design environ-ment[21].1. Use a predefined template for PMOS and NMOS transistor placement.The architecture of a cell should be defined beforehand, and this tem- plateshould encapsulate the basic oorplan of a group of cells. Figure 5.2 showsan example of a cell template Use transistor fingering for large and criticaltransistors. A cell template similar to Figure 5.2 defines the maximum widthof a transistor by the cell height. How do we lay out a transistor that exceedsthis height? The solution is to finger the transistor into multiple transistorsthat are connected in parallel.

Figure 5.3 shows three equivalent layout designs of a transistor that is100mm wide.2. There is an advantage with an even number of fingers: the active capaci-tance is less, because the drain region is surrounded with gate poly instead offield. Another reason to use fingering is to optimize the resistance of the gatepoly along the width of the transistor. Since the gate poly is driven from oneend and gate poly is resistive, there may be reason to have a guideline thatstates the maximum width of a single finger. Fingering is the only way tomeet this guideline for large transistors. Fingering multiple transistors thatare connected in series is trickier. Figure 5.4 shows an example of fingeringa two-input NAND gate. Fingering the PMOS devices is straightforward;however, fingering the series NMOS devices is more difficult because the or-der of connectivity of the devices must be maintained.

3. Share power supply nodes to save area. Sharing nodes whenever pos-sible is a concept that is easy to understand. Power supply nodes are mosteasily shared because they are very common and easy to connect. Very sig-nificant area savings can be achieved. The main reason that area is saved isthat both sides of a row of contacts are used and there is no need to space twoactive regions apart from each other. Figure 5.5 illustrates this technique.Note that power nodes can be shared between transistors of different widthswith a slight overhead of inserting a poly to active space at the end of thesmaller transistor.

4. Determine minimum number of contacts for source and drain connec-tions. One simple rule might be to as many as you can using the minimum



design rule between two contacts. This guideline is most re- liable and max-imizes the performance of the transistor. The downside of this approach isthat the routability over the transistor is limited. If increased routability isrequired and accounted for in the circuit design, fewer than the maximumnumber of contacts may be optimal for the overall layout design. This ap-proach must be considered carefully and accounted for in the circuit designprocess.

Figure 5.2: Example Cell Template

5.5 Multifinger Transistor

Wide transistors are usually ”folded” so as to reduce both the S/D junctionarea and the gate resistance. A simple folded structure such as that inFig.5.7 (a) may prove inadequate for very wide devices necessitating the useof multiple ”fingers”[Fig.5.7 (b)]. As a rule of thumb, the width of eachfinger is chosen such that the resistance of the finger is less than the inversetransconductance associated with the finger .In low-noise applications, thegate resistance must be one-fifth to one-tenth of .



Figure 5.3: Fingering Of Transistors

5.6 Symmetry

Symmetry must be applied to both the devices of interest and their sur-rounding environment. Symmetries in fully differential circuits introduce in-put referred offsets, thus limiting the minimum signal level that can be de-tected. While some mismatch is inevitable inadequate attention to symme-try in the layout may result in large offsets. Symmetry also suppresses theef- fect of common-mode noise and even-order nonlinearity. Let us considerthe differential pair of Fig.5.8 as the starting point. If, as depicted in Fig.5.9, the two transistors are laid out with different orientations, the match- inggreatly suffers because many steps in lithography and wafer processing be-have differently along different axes. Thus, one of the configurations in

Figure 5.10 and Figure 5.11 provides a more better solution.When laying out any device the key is symmetry, especially when laying

out fully-differential components. For matched devices, use interdigitized orcommon centroid layout techniques. A matched device is one where twotransistors need to have exactly the same geometries. Examples includecurrent mirrors and differential pairs. An interdigitized layout is shown inFigure 5.12. Notice that the two transistors have been split into smallersize devices and interleaved. This layout minimizes the effects of processvariations on the parameters of the transistors. The idea behind splitting



Figure 5.4: Example Of Fingering A NAND Gate

a transistor up is to average the process parameter gradient over the areaof the matched devices. For example, the process variation of KP and ofthe transconductance parameter on the wafer is characterized by a globalvariation and a local variation.[20] Global variations appear as gradients on

the wafer as in Figure 5.13. However, local variations describe the randomchange in the parameter from one point on the chip to another nearby point.By using layout techniques such as interdigitized and common-centroid, theprocess variation can hopefully be averaged out among the matched devices.When laying out wider matched transistors the common-centroid layout maybe a better choice. This layout technique is illustrated in Figure 5.14 andFigure 5.15 for the case of 8 matched M1 and M2 transistors of a differentialpair.



Figure 5.5: Transistor Power Sharing Example

Figure 5.6: Example Of Soft Connections



Figure 5.7: (a)Simple Folding Of A MOSFET,(b) Multiple Fingers

Figure 5.8: Differential pair



Figure 5.9: Layout Of MO And M1 With Different Orientation

Figure 5.10: Layout With Gate-Aligned Devices



Figure 5.11: Layout With Parallel-Gate Devices

Figure 5.12: Interdigitized layout of a differential pair a) Differential pairb) Horizontal expansion c) Interdigitized layout (Drain areas are different.Common centroid.) d) Interdigitized layout (Drain areas are equal. Notcommon centroid.)



Figure 5.13: Gradient of KP on a wafer

Figure 5.14: Common-centroid layout of a differential pair



Figure 5.15: Common-centroid examples


Chapter 6

Simulation Results and Layout

This section expands on the simulation results obtained from the differenttypes of the compensation techniques for two stage op amp.The amplifieris to be powered from 1.8V power supply. The Unity Gain Bandwidth tar-geted was 1GHz and the corresponding Phase Margin was 600.Based on theproposed compensation technique a CMOS op amp has been designed andsimulated in a TSMC 130nm technology.

6.1 Nulling Resistor

In Figure 6.1 shows the schematic of the Two stage op amp with the nullingresistor.The summary of the result is reported in the Table 6.1.

The AC response of the two stage op amp is shown in the below Figure 6.2.The dc gain achieved is 61dB and the UGB is 235MHz and the correspondingPhase Margin is 60.150 with the power dissipation of 1.94mW.

6.1.1 Summary

Simulation result is obtained using the MentorGraphics Eldo Schematic shownin below table.

6.2 Voltage Buffer

In Figure 6.3 shows the schematic of the Two stage op amp with the nullingresistor.The summary of the result is reported in the Table 6.2

64


Figure 6.1: Two stage op amp with Nulling Resistor

Table 6.1: Summary of Two stage op amp with nulling resistorParameter Nulling resistor

DC Gain 61dBUGB 235MHzPM 60.15degCc 1.2pF

Pdiss 1.94mW

The AC response of the two stage op amp is shown in the below Figure 6.4.The dc gain achieved is 54dB and the UGB is 478MHz and the correspondingPhase Margin is 60.90 with the power dissipation of 2.22mW.

6.2.1 Summary




Figure 6.2: AC response of the two stage op amp with the Nulling resistor

Table 6.2: Summary of Two stage op amp with voltage bufferParameter Voltage Buffer

DC Gain 54dBUGB 478MHzPM 60.9degCc 0.7pF

Pdiss 2.22mW

6.3 Current Buffer

In Figure 6.5 shows the schematic of the Two stage op amp with currentbuffer.The summary of the result is reported in the Table 6.3.

The AC response of the two stage op amp is shown in the below Figure 6.6.The dc gain achieved is 59.8dB and the UGB is 1GHz and the correspondingPhase Margin is 61.20 with the power dissipation of 2.66mW.

6.3.1 Step Response

In Figure 6.6, a step from ground to VDD is applied at the input with unityfeedback configuration.As we measured,The amplifier slew rate is 707V/us



Figure 6.3: Two stage op amp with Voltage Buffer

as shown in Figure 6.7.

6.3.2 Settling Time

The Unity gain follower configuration of two stage op amp with currentbuffer is also use for settling time and peak over shoot measurement.Thisis the length of time for the output voltage of an op amp to approach andremain within a certain tolerance of its final value. This is usually specifiedfor a full scale input step. Op amp is baised as shown in Figure 6.5.Figure6.7 shows the settling time for different tolerance value.

The below Table shows the settling time with the different tolerancevalues.

Table 6.3: Variation of settling time of op amp with different tolerance valuesTolerance(%) Settling time(ns)

0 201 17.952 3.43 3.2



Figure 6.4: AC response of the two stage op amp with the Voltage buffer

6.3.3 Design Parameters

Table 6.4 lists the relevant transconductance and parasitic values used duringcalculation and the achieved values during simulation and compares the polelocations.

Table 6.4: Design ParametersParameter Designed Simulated

gm1,2 1.428mA/V 1.8087mA/Vgmc 1.428mA/V 1.676mA/Vgm5 4.356mA/V 6.53mA/VP1 740kHz 783.84kHz

P2,3 2GHz 2.66GHz

6.3.4 Summary




Figure 6.5: Two stage op amp with Current Buffer

Table 6.5: Summary of Two stage op amp with current bufferParameter Current Buffer

DC Gain 59.8dBUGB 1GHzPM 61.12degCc 0.4pF

Pdiss 2.66mWSettling Time 3.4ns

Slew Ratw 707V/us

6.4 Comparision

The below table shows the comparison of the different types of compensationtechniques of two stage op amp.



Figure 6.6: AC response of the two stage op amp with the Current buffer

Figure 6.7: Step Response of two stage op amp with Current buffer



Figure 6.8: Slew Rate of two stage op amp with Current buffer

Figure 6.9: Settling Time



Table 6.6: Comparison of different types of compensation technique of twostage op amp

Parameter Nulling Resistor Voltage Buffer Current bufferUGB 235MHz 478.84MHz 1GHz

DC Gain 61dB 54.4dB 59.8dBPM 60.15 deg 60.9 deg 61.12degCc 1.2pF 0.7pF 0.4pF

Pdiss 1.94mW 2.22mW 2.66mW

6.5 Layout

This prototype design of the indirect feedback frequency compensation is im-plemented in TSMC 130nm technology. In analog design, matching is veryimportant. Particularly, Op Amps need high matching to achieve low inputreferred offset and high noise rejection. The matching between transistors ismainly dependent on1. Size of transistors2. Shape of transistors3. Orientation of transistors

The below Figure shows the Layout of a Two stage op amp with thecurrent buffer compensation technique.Both the schematic and Layout ismatched perfectly.



Figure 6.10: Layout of the two stage op amp with the Current buffer


Chapter 7

Conclusion and Future scope

7.1 Conclusion

In this thesis, compensation methods for Op Amps are investigated alongwith their pros and cons in order for a designer to choose the appropriatescheme for a particular application. This thesis further explores a creativeindirect feedback compensation method which overcomes the major draw-back of bandwidth narrowing by the widely used polesplitting method. Itcan improve the phase margin as well as extend the bandwidth of the OpAmp. The indirect feedback method can be easily applied to the existingpopular two gain stage Op Amp architectures with very little alteration.The mathematical derivation and circuit simulation demonstrate the ad-vanced properties and improved performance of this feedforward compen-sation technique.The three compensated OTA is compared with gain, UGB,Power dissipation,Phase Margin.

The indirect feedback technique discussed in this thesis is a practical andsuperior compensation scheme for Op Amps, and results in amplifiers withmuch higher speeds and smaller areas.The two stage op amp with currentbuffer compensation achieved is 1GHz UGB and corresponding phase marginof 61.120 while driving a capacitive load of 1pF and DC gain of 59.8dB.Wecan observe that Cc of current buffer is reduced to 0.4pF when comparedto Cc of nulling resistor of 1.2pF. Current buffer compensated OTA thereis improvement in the gain, UGB, PM and area requirement is also lesscompared to nulling resistor compensated OTA.

74


7.2 Future Scope

As a part of future research the compensation method developed for the twostage amplifier can be extended to realize a three stage and multi-stage am-plifiers. A formal derivation and design procedure for multi stage amplifieremploying can be developed using the indirect feedback frequency compen-sation technique.


Bibliography

[1] X. H. Fan, C. Mishra, and E. Sanchez-Sinencio, ”Single miller capacitorfrequency compensation technique for low-power multistage amplifiers”IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 584-592, 2005.

[2] P. R. Gray, and R. G. Meyer,, ”Analysis and design of analog integratedcircuits,”’ ,3rd ed., New York: Wiley, 1993.

[3] G. Palmisano, and G. Palumbo, ”A compensation strategy for two-stageCMOS opamps based on current buffer” IEEE Transactions on Circuitsand Systems I-Fundamental Theory and Applications, vol. 44, no. 3, pp.257-262, Mar, 1997.

[4] B. K. Ahuja, An Improved Frequency Compensation Technique forCMOS Operational-Amplifiers” IEEE Journal of Solid-State Circuits,vol. 18, no. 6, pp. 629-633, 1983

[5] K. N. Leung, and P. K. T. Mok,”Analysis of multistage amplifier-frequency compensation” IEEE Transactions on Circuits and SystemsI-Fundamental Theory and Applications, vol. 48, no. 9, pp. 1041-1056,Sep, 2001.

[6] H. Lee, and P. K. T. Mok, Active-feedback frequency-compensation tech-nique for low-power multistage amplifiers” IEEE Journal of Solid-StateCircuits, vol. 38, no. 3, pp. 511-520, 2003.

[7] D.A.Johns and K.Martin, ”Analog Integrated Circuit Design”, NewYork:John Wiley and Sond,Inc.,1997.

[8] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., ”Design approach forfastsettling two-stage amplifiers employing current-buffer Miller compen-


sation” Analog Integrated Circuits and Signal Processing, vol. 59, no.2, pp. 151-159, 2009.

[9] H. Mahattanakul, and J. Chutichatuporn, ”Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme” IEEETransactions on Circuits and Systems I-Regular Papers, vol. 52, no. 8,pp. 1508-1514, 2005.

[10] R. J. Reay, and G. T. A. Kovacs,, ”An Unconditionally Stable 2-StageCMOS Amplifier” IEEE Journal of Solid-State Circuits, vol. 30, no. 5,pp. 591-594, 1995.

[11] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., ”Design approach forfastsettling two-stage amplifiers employing current-buffer Miller compen-sation” Analog Integrated Circuits and Signal Processing, vol. 59, no.2, pp. 151-159, 2009.

[12] A. Pugliese, F. Amoroso, G. Cappuccino et al., ”Settling time optimisa-tion for two-stage CMOS amplifiers with current-buffer Miller compen-sation” Electronics Letters, vol. 43, no. 23, pp. 1257-1258, 2007.

[13] M. Loikkanen, and J. Kostamovaara, ”Improving capacitive drive capa-bility of two-stage op amps with current buffer” Proceedings of the 2005European Conference on Circuit Theory and Design, Vol 1, pp. 99-102,2005.

[14] Mahattanakul, J., ”Design Procedure for Two-Stage CMOS OperationalAmplifiers Employing Current Buffer” IEEE Transaction on Circuitsand Systems II- Express Briefs, vol. 52, no. 11, Nov 2005.

[15] Saxena, V. and Baker, R. J., ”Indirect Compensation Technique for Low-Voltage Op-Amps” Proceedings of the 3rd Annual Austin Conference onIntegrated Systems and Circuits (ACISC), May 7-9, 2008.

[16] Behzad Razavi ” Design of analog cmos integrated circuits” McGraw-Hill, 2001.

[17] Phillip E. Allen and Douglas R. Holberg ” CMOS analog circuit Design”McGraw-Hill, 2001.



[18] Baker, R.J., ”CMOS: Circuit Design, Layout, and Simulation” 2nd Ed.,Wiley Inter science, 2005.

[19] Dan Clein, ”CMOS IC LAYOUT Concepts, Methodologies, and Tool”2nd Ed., Wiley Inter science, 2005.

[20] Alan Hastings, ”The Art of Analog Layout (Sencond Edition)” 2007.IEEE Journal of Solid-State Circuits, vol. SC-14, Issue 6, Dec.1979,pp.1111-1114. 1996.

[21] Pelgrom, M. J. M., Duinmaiger, A. C. J., andWelbers, A. P. G, ”Match-ing Properties of MOS Transistors” 2007. IEEE J. Solid-State Circuits,Vol. SC-24, Oct. 1989, pp. 1433-1439.


APPENDIX ARoots of quadratic Equation

A second-order polynomial often appears in the denominator or numerator ofa transfer function, and the zeros of this polynomial are the poles or zeros ofthe transfer function. In this appendix, the relationships between the zeros ofa quadratic and its coefficients are explored for a few specific cases of interest.Also, the conditions under which a dominant root exists are derived.

Consider the roots of the quadratic equation

as2 + bs+ c = 0 (7.1)

the two roots of this equation, r1 andr2 are given by the quadratic formula:

r1,2 =−b±

√b2 − 4ac

2a(7.2)

where it is understood that the square root of a positive quantity is pos-itive. Factoring b out of the square root and rearranging gives

r1,2 = − b

2a(1±

√1− 4ac

b2) (7.3)

r1,2 = − b

2a(1±

√D) (7.4)

The quantity under the square root in (7.3) has been replaced by D in(7.4), where

D = 1− 4ac

b2(7.5)

Now, consider the locations of the roots if coefficients a, b, and c all havethe same sign. In this case, both roots are in the left half-plane (LHP), aswill be shown next. First, note that if all the coefficients have the same sign,then

b

2a> 0 (7.6)

4ac

b2> 0 (7.7)

Let us divide the above equation(7.7) into two different regions.First,if


0 <4ac

b2< 1 (7.8)

then D will be positive and less than one.Therefor√D < 1, so 1 +

√D and

1 −√D are both positive.As a result, the roots are both negative and real,

because − b2a< 0.

Now consider the other region for (7.7),which is

4ac

b2> 1 (7.9)

In this case, D¡0; therefore√D is imaginary. The roots are complex

conjugate with a real part of −b/2a, which is negative.So the roots are againin the LHP.LHP. Therefore, when coefficients a, b, and c all have the samesign, both roots are in the LHP. Next, consider the locations of the roots ifcoefficients a and b have have the same sign and c has a different sign. In thiscase, one real root is in the right half-plane (RHP) and the other is in theLHP. To prove this, first note from (7.5) that D ¿ 1 here because 4ac/b2 < 0.Therefore both roots are real and

√D > 1, so

1 +√D > 0 (7.10)

and1 +√D < 0 (7.11)

Substituiting into (7.2), one root will be positive and the other negative(the sign of −b/2a is negative here).

Finally, let us consider the conditions under which LHP roots are realand widely spaced. From (7.2), real LHP roots are widely spaced if

− b

2a(1 +

√D) << − b

2a(1−

√D) (7.12)

or1 +√D >> 1−

√D (7.13)

Substituting the expression for D in (1.5) into (1.9) and simplifying leadsto an equivalent condition for widely spaced roots, which is

44ac

b2<< 1 (7.14)

under this condition , one root is



r2 = − b

2a(1 +

√D) ≈ − b

2a(1 + 1) = − b

a(7.15)

The other root is

r1 = − b

2a(1−

√D)

r1 = − b

2a(1−

√1− 4ac

b2)

r1 = − b

2a(1− (1− 4ac

2b2))

r1 = −cb

(7.16)

where the approximation

√1− x ≈ 1− x

2

for |x| << 1has been used. Here,|r1| << |r2| because |r1| ≈ c

b<< b

a≈ |r2|.If there

roots are poles,r1 corresponds to the dominant pole, and r2 gives the non-dominant pole.


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