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Abstract- The number of voltage levels available in pwm volt-

age source inverters can be increased by using a split-wound

coupled inductor within each inverter-leg and using inter-

leaved pwm switching of the upper and lower switches. The

magnetizing inductance of the symmetrical split wound in-

ductor filter the high frequency pwm voltage differences be-

tween the upper and lower switches. The same inductor

presents a 3-level pwm voltage at the inverter output termi-

nals, with the winding leakage inductance being located in se-

ries with the low frequency output current. Dead-time pwm

signal delays can be reduced as dc-rail short circuits are not

possible: the quality and voltage range of the pwm output isimproved as a result. Since the inductor windings are techni-

cally exposed to high frequency pwm ac voltages with no dc

components, device voltage drops help to reduce the build up

of winding dc currents. Theoretical analysis and a sample de-

sign case is presented to illustrate how to design suitable in-

ductors for the various topologies. Simulation and

experimental results are used to illustrate the operation of the

proposed inverter structures.

I. INTRODUCTION

The standard 2-switch 2-level and 4-switch 3-level in-

verters, Fig. 1(a),(b), are the preferred topologies in many

low power single phase systems such as: fractional horse-

power ac drives; lighting equipment; alternative energy

systems etc. As the performance factors, power level and

fundamental operating frequencies are increased, the in-

ductor size and switching frequencies become restrictive

design factors: high energy storage requirements increase

the inductor size; maximum switching frequencies are lim-

ited by power losses; gate drive restrictions; pwm dead-

times, etc. As a result, the high frequency current ripple at

the inverter output may not be as low as required and can

cause problems such as excessive heating in motor drives;

emi/rfi; larger than desired output filters (large filter induc-

tors are expensive, increase losses, and have a large funda-

mental voltage drop).

Parallel connected inverter modules, that either use cur-

rent ripple cancellation or alternatively multi-level pwm

output voltages [1]-[9], are widely used techniques for in-

creasing the effective pwm and current ripple frequency

above the device switching frequency. This often results in

lower device losses, smaller inductors, a lowering of the

current ripple magnitude and a faster inverter transient re-

sponse. Parallel connected modules often use interleaved

pwm and ac filter inductors connected between the mod-

ules to achieve high frequency current ripple cancellation

and a lower output current ripple. There are many current

balancing issues [4-8] and, since the various inductors can-not be guaranteed to have the same characteristics, har-

monic current cancellation may not be optimal. Inverters

with increased pwm levels have been proposed in motor

drives [9] and interleaved pwm used in parallel connected

inverters [10,11], boost converters [12,13], buck convert-

ers [14,15] and an asymmetrical bridge [16]. Coupled in-

ductors [17] and interleaved pwm techniques [18] are also

used in many situations. PWM signal dead-times are used

to avoid shorting the dc supply and many papers have been

written to provide compensation for their undesirable fea-

tures [19-22].

The proposed inverter topology differs from many ofthese schemes because, rather than adding more switch

modules and ac inductors, coupled inductors are included

inside the standard modules using interleaved pwm of the

upper and lower switches in an inverter-leg. Multi-level

pwm output voltages are obtained with a pwm frequency

higher than the switching frequency. The resultant topolo-

gies use smaller ac filter inductors; faster transient re-

sponse; fewer switches; do not experience critical dc

supply shorts; improve the quality of the pwm waveforms

by eliminating the need for switch deadtimes; immune to

circulating currents.

II. PROPOSED TOPOLOGY USING COUPLE INDUCTORS

This section places the proposed topologies in context

with existing topologies and describes how coupled induc-

tors can be used to produce multi-level pwm voltages.

One technique used in high power motor drives for pro-

ducing multi-level pwm waveforms with an increased pwm

frequency is to stack modules in series and using separate

isolated dc voltage sources for each module, Fig. 1(c). This

technique is suited for high power systems and often uses

harmonic cancellation ac input transformers. The 4-switch

inverter leg is considered a suitable technique in high volt-

age and high power applications because the switches areexposed to half the dc rail voltage and 3-level pwm voltag-

es are produced at the output of each inverter leg, Fig. 1(d).

An often used technique for parallel connected inverters is

to connect the inverter output terminals using ac inductors

and use interleaved pwm for current ripple cancellation:

the effective size of the ac filter inductors can also be re-

duced as a result, Fig. 1(e). An alternative scheme uses in-

terphase inductors, or chokes, and interleaved pwm

switching to produce multi-level pwm voltages at the out-

put terminals, Fig. 1(f). This technique is especially useful

if the load is inductive, eg. motors and high speed genera-

tors. The interphase inductors are very small is size due to

their relatively low magnetic flux magnitude. AC filter in-ductors maybe required to filter the output, but their size is

Single Phase Multi-Level PWM Inverter

Topologies using Coupled InductorsJ. Salmon, A. Knight, J. Ewanchuk

University of Alberta, Edmonton, Canada

978-1-4244-1668-4/08/$25.00 2008 IEEE

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Fig. 6. Interleaved pwm control of the proposed inverter leg.

(a)

Sa

va

(b) (c) (d) (e)

+vdc

0

Fig. 4. Switching states of the proposed inverter leg: (a) basic switching

cell, (b) SaU, SbLon: va= vdc/2,(c) SaU,SaLoff: va= vdc/2, (d) SaUoff, SaLon: va= 0, (e) SaUon, SaLoff: va= vdc,

va

0

0

va

L 2

(a) (b)

icmL

(c)

vaUL

vdc

0

Fig. 5. Equivalent circuits of the proposed inverter leg: (a) transformer

equivalent model, (b) input model, (c) circuit model between the switches

0

Lt

2

vdc

ia

2

iaU=12ia+ icm

iaL= -12ia+ icm

iaU iaL

vaU

va

ia

vaLva va

va

ia

ia

2

icm

vdc

vaL+ vaU

ia

vaU

vaL

va

t

vcUvcLvref

v

dc

2

v

dc

0

v

dc

0

v

dc

0

(b)

Fig. 7. Experimental waveforms of the split-wound coupled inductor andinverter leg: (a) expanded waveforms, (b) 60 Hz fundamental cycle.

(c)

Current-amp

volts

2

V

div

vaU

0

0

0

ia

(a)

vaL

vaUL

icm

iaL

iaU

time - mS

time - mS

va

Cu

rrent-Am

p

Voltag

e-VoltsiaU iaL

ia

SaL

leakage inductance is low.The inductor voltage vaULillus-

trates that the pwm cycle inductor voltage is symmetrical

with no dc component. This feature and exists over the

complete output voltage range, hence no dc currents or

core saturation are produced by the interleaved pwm con-

trol scheme.

There is always a concern that dc and circulating currents

are produced in parallel connected inverters. Ideally the

parallel circuit paths have identical voltage drops, and the

natural variations in the device operating conditions can

cause unbalanced currents. The device voltage drops in the

proposed topology produce a nett -ve voltage drop across

the inductor (= 1 switch and 1 diode voltage drop on aver-

age) that act against dc current drifts or circulating cur-

rents. Experimental testing illustrated that variations in the

switch turn off-times can produce a positive inductor volt-

age drop, and hence produce a dc current. However, prac-

tically this is easily overcome by introducing a small

difference between the switching of the upper and lowerswitches to provide a small nett -ve inductor winding volt-

age drop, hence guarantee no dc current build up. It should

be noted that the inductor windings have a natural dc cur-

rent component determined by the ac output current, see

iaU,iaLin Fig. 7.

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IV. RIPPLE CURRENT ANDINDUCTOR SIZE

Analysis is presented using a per-unit system to allow in-

ductor sizes to be chosen based upon the current ripple:

, , , (1)

A test condition is used to compare the various inverter

topologies: Vs= 120, fs= 60Hz, Is,pk= 10A, Imax= 5%

pk-pk, Vdc= 1.5 Vs, switching frequency, fc= 10kHz

A. AC Supply Filter Inductors

The maximum high frequency pk-pk current ripple for

the ac inductor Ls isImaxand can be sized relative to the

60Hz pk-pk value of the ac supply current Ippusing Ris, Rf,

Rv.

, , , (2)

Hence for the test condition: Ris = 20, Rv = 1.06, Rf= 166.7

Fore the standard 2-switch inverter-leg, Imax occurs

when the inverter output terminal has a 50% duty ratio with

the voltage switching between +Vdc and -Vdc, Fig. 1(a).

The supply inductor Lssees a pwm voltage that is a sym-

metrical square-wave at the carrier frequency fc and mag-

nitude Vdc:

, (3)

(1),(2),(3) can be used to link with Imax. Similar anal-

ysis can be conducted for each of the topologies shown inFigs. 1(a),(b) & 2(a),(b), with the results given in Table I.

TABLEI: DESIGNPARAMETERS FOR THE ACFILTERINDUCTORLS

Hence suitable inductors to meet the test conditions are:

(i) 2-switch inverter-leg:

With Lbase= 45mH, Ls = 9mH. This inductor will have a

20% fundamental voltage drop at the rated current.

(ii) 4-switch standard H-bridge: =0.05 p.u.

With Lbase = 45mH, Ls = 2.25mH. This inductor will

have a 5% fundamental voltage drop at the rated current.

(iii) 2-switch coupled inductor:

Identical to the 4-switch H bridge: Ls= 2.25mH, with a5% fundamental voltage drop at rated current.

(iv) 4-switch coupled inductor:

With Lbase= 45mH, Ls = 0.57 mH. This inductor will

have a 1.3% fundamental voltage drop at rated current, and

is four times smaller than required for the standard 4-

switch.

B. Inverter-Leg Coupled Inductor

2-switch: The maximum pk-pk high frequency current rip-

ple occurs when the inductor L tsees a pwm symmetrical

square-wave voltage of magnitude2Vdc and frequency fc

4-switch coupled: Similarly, the coupled inductor Lthas a

maximum current ripple when it sees a pwm symmetrical

square-wave voltage of magnitudeVdc and frequency fc.Design parameters for the inductors are given in Table II:

TABLEII: DESIGNPARAMETERS FOR THECOUPLEDINDUCTORLt

A recommended minimum value for Ritshould be 4, to

avoid excessive discontinuous winding currents: 8 or high-

er significantly lowers the high frequency current ripple.

The H-bridge under the test conditions: Rit=4, Rv=1.06,

Rf=166.7: p.u.= 1.8mH ( )

These tables allow the designer to pick a suitable induct-

ance, in terms of mH, given a desired current ripple. When

compared with the standard topologies, the coupled induc-

tors reduces the ac filter inductor by a factor of 4. The high

frequency ripple in the ac filter inductor is twice the carrier

frequency for the two switch: four times for the H-bridge,

but the inductor losses are drastically reduced as the current

ripple magnitude is much smaller.

In general, the standard 2-switch inverter has a very largerelative current ripple, but when using the coupled induc-

tors, produces a ripple current magnitude equal to the

standard H-bridge. The 4-switch H-bridge with a coupled

inductor produces a current ripple magnitude comparable

to using two 4-switch H-bridges and a standard ac filter in-

ductor. Inverters using the coupled inductors produce the

same performance as standard inverters using twice the

power electronics; and lower the size of the ac inductors

and their fundamental voltage drop. This increases the fun-

damental load voltage and lowers the load current. This has

the effect of lowering the losses in the semiconductors and

inductors.

2-switch

split rail

4-switch

H-bridge

2-switch

Coupled L

4-switch

Coupled L

Imax

Ls Lspu

Lb= Pbase Vs Iba se= Lba se

Vs2

2fsPba se--------------------------=

Ris

Ipp

Ima x----------------= Rf

fc

fs----= Rv

Vdc

2Vs

--------------=

dc dc

max

s c c s

V V1I

L 2f 2f L pp c s

is

dc

2I f LR

V

Lspu

Lspu

2---

Ris Rv

Rf---------------

8---

Ris Rv

Rf---------------

8---

Ris Rv

Rf---------------

32------

Ris Rv

Rf---------------

50Rv

RfLspu

---------------25

2------

Rv

RfLspu

---------------25

2------

Rv

RfLspu

--------------- 3.1Rv

RfLspu

---------------

Lspu

1.5720 1.06

166.7---------------------- 0.1p.u.= =

Lspu

0.39220 1.06

166.7----------------------=

Lspu

0.39220 1.06

166.7---------------------- 0.05p.u.= =

2-switch

split dc rail

4-switch

H-bridge

Lt,pu

It,max

(%)

Lspu

0.120 1.06

166.7---------------------- 0.0127p.u.= =

Rit Rv

Rf--------------

2---

Rit Rv

Rf--------------

100Rv

RfLtpu

--------------- 50Rv

RfLtpu

---------------

t,puL 0.04 Rit

pp

It max--------------------=

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TABLEIII: INDUCTORDESIGNS USINGLOWPERMEABILITYCORES

Ls1= Standard H-bridge ac inductor

Ls2=ac inductor for the proposed H-bridge

Ls3= expt. ac inductor used for the proposed H-bridge

Lta,b= H-bridge coupled inductors (1: It,max= 1.5A, 2:It,max, 4A,2:It,max= 6A).

Lt1a,b Lt2a,b Lt3a,b Ls1 Ls2

Magnetic Core E306-26 E225-26 EE168A EE450 2*E225

Lmin(mH) 3.25 1.28 0.83 2.48 0.66

Lmean(mH) 4.85 1.84 1.23 3.78 0.96

Nturns 150 86 84 97 44

Wire AWG 16 16 16 16 16

Imax (A) 1.5 A 4A 6A 1A 0.95A

Irms (A) 6.12 6.12 6.12 6.12 7.07

Imag,pk 5.00 5.0 5.0 10 10

AFe(cm2) 5.6 3.6 2.4 12.2 7.2

MPL (cm) 18.5 11.5 10.4 22.9 11.5

Rw(ohms) 0.306 0.129 0.104 0.291 0.088

Mu0 75 75 75 75 75

Saturation (%) 49.6 46.7 49.5 51 47.6

Epeak

(mJ) 40.7 16 10.3 124 33.0

Bac(Tesla) 0.03 0.081 0.123 0.011 0.01

Bmax(Tesla) 0.315 0.35 0.408 0.306 0.283

WtFe(g) 728.0 285.6 172.2 1960 571.2

WtCu(g) 275.3 116.1 93.0 261.9 79.1

WtTotal(g) 1003 402 265 2222 650

PFe(W) 2.15 6.89 9.73 0.57 0.27

PCu(W) 11.4 4.81 3.85 14.57 4.40

Ptot(W) 13.5 11.79 13.58 15.15 4.67

V. INDUCTORDESIGNSTUDY

Inductor design parameters are compared here for a sin-

gle phase 4-switch H-bridge inverter using the following

design criteria: Vs= 120V, fs= 60Hz, Is= 7A, with fc=

20kHz. and Vdc= 200. Designs are considered for several

maximum current ripple magnitudes: It,max=1.5, 4, 6 A.

The coupled inductor required for each winding current

ripple can be compared with each other and the ac supply

filter inductor, Ls. Several design guidelines were used:

(1) Low permeability cores with a distributed airgap were

considered for all the ac inductors due to their slow satura-

tion characteristics. The maximum permissible core satura-

tion was set at 50%.

(2) High permeability ferrite cores with an airgap were not

considered as all inductors can be exposed to surge currents

and have significant dc flux and energy storage.

(3) The wire size was chosen to suit the rms current with no

attempt to minimize the Cu losses.

(4) The maximum ac flux (Bac) and manufacturer data was

used to estimate the core losses.

Note that the design for the ac filter inductors (Ls1and

Ls2) were chosen to give the same current ripple in both

bridge types; standard H-bridge and the proposed H-

bridge. For the experimental waveforms, a 1 mH inductor

was used for both cases (Ls3in Fig. 8.), to compare the ef-

fect on the ac current ripple of using the proposed H-bridgerather than the standard H-bridge. A typical design table for

the various inductors is given in Table III and all the induc-

tors used in experimental testing shown in Fig. 8.

For winding ripple current cases 4A and 1.5A, the total

weight of the inductors used was less than the weight of the

ac filter inductor required for the standard H-bridge:

Standard H bridge: WtTotal= 2222 g

Proposed H-bridge (Itmax=6A): WtTotal= 650+2*265=1170g

Proposed H-bridge (Itmax=4A): WtTotal= 650+2*402=1604g

Proposed H-bridge (Itmax=1.5A): WtTotal= 650+2*1002=2652g

If the winding ripple current is made too small, e.g. It-

max=1.5A, the total inductor weight required can be in-

creased above that required for the standard inverters; if too

large, Itmax=6A, excessive losses can make the inductor

too hot. These results illustrate that the proposed topology

can half the number of switches and also be used to lower

the combined inductor weight. This weight reduction is

limited by the winding dc magnetizing current component,

and the inductor core losses. Magnetic cores with lower

core loses should be considered than used here The main

benefit of the proposed approach is to allow multi-levelpwm switching using half the power electronics and when

using an inductive load such as a motor.

Fig. 8. Experimental inductors

L

t1a

L

t2a

L

s3

L

t1b

L

t2b

VI. EXPERIMENTALWAVEFORMS

The experimental waveforms presented in this section

used a general purpose laboratory test inverter, using the

following inductors (see Fig. 8) and load parameters:

Standard H-bridge: ac filter inductor = Ls1Proposed H-bridge: ac filter inductor = L

s3couple inductor = Lta,b1, Lta,b2

Vs= 120V. Is= 7A, fs= 60 Hz, Vdc= 200V, fc= 20kHz.

L

s1

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Cu

rren

t-Am

p

Cu

rren

t-Am

p

Voltage

-Volts

Voltage

-Volts

Fig. 9. Differences between 3-level and 5-level pwm voltages: (a) Standard H-bridge, (b) H-bridge using the proposed coupled inductors

(a) (b)

time - mS time - mS

Cu

rrent-Amp

Cu

rrent-Amp

Fig. 10. Winding current comparisons between using different coupled inductor sizes: (a) Lta,b= Lt2a,b, (b) Lta,b= Lt1a,b

(a) (b)

time - mS time - mS

Cu

rrent-Am

p

Cu

rrent-Am

p

Voltage

-Volts

Fig. 11. Inverter-leg waveforms illustrating 3-level pwm output voltages

and a raised cosine winding current waveshape: Lta,b= Lt1a,b

time - mS time - mS

The same standard laminated iron ac filter inductor was

used in all cases (Ls3= 1mH, Fig. 8) to allow comparison

of the ac load current ripple magnitude. The interleaved

pwm signals were generated using a TI TMS320F2812

dsp.

The proposed 4-switch H-bridge produces 5-level pwm

load voltage waveforms and a load current ripple 25% low-er than the standard 4-switch H-bridge, Fig. 9.

The magnitude of the couple inductor winding current

ripple does not affect the load current ripple or the quality

of the pwm output voltage waveforms, Figs. 9,10. The cou-

pled inductor winding currents have a magnetizing current,

icm, with a dc component equal to half the peak ac output

current (Figs. 10,12) and a high frequency current ripple

determined by the inductor size. The 3-level inverter-leg

output voltage waveform is shown in Fig. 11 with the mid-

dle voltage level sitting at one half the dc rail voltage. Thecoupled inductor magnetizing current and its ripple is

shown in Fig. 12 relative to the ac load current. Since this

dc component is about one half the peak current, its physi-

cal size is reduced.

Fig. 12. Coupled winding dc magnetizing current, icm, compared with the

ac load current ia: Lta,b= Lt1a,b

ia

vab vab

ia

iaUiaL

icm

iaUiaL

icm

iaU iaL

ia

va ia

icm

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VII. CONCLUSIONS

The use of a coupled split-wound inductor is described

to allow interleaved pwm switching of the upper and lower

switches in an inverter leg. This increases the number of

pwm output voltage levels and doubles the pwm frequen-

cy. The main benefits of this topology are:

(1) Multi-level pwm (3-level increased to 5-level) using

half the power electronics of alternative schemes

(2) Lowering of the load high frequency current ripple in

the ac output current, which can lower the losses in the ac

filter inductor or an ac motor; the latter has potential ben-

efits in terms of increasing the motor power ratings and ef-

ficiency of the machine. These features have great

potential in high speed machine drives. The multi-level

output voltage waveforms also places less stress on the

motor windings and help to alleviate motor winding dv/dt

stresses.

(3) The ac filter inductor can be reduced in size. The fun-

damental voltage drop across the inductor is also reduced

as a result and more fundamental voltage reaches the load.

.(4) The switch control deadtimes can be eliminated,

helping to improve the quality of the pwm voltage gener-

ation and increasing the maximum potential output volt-

age.

(5) The coupled inductor provides excellent protection

against dc-rail shoot-through conditions.

ACKNOWLEDGEMENTSThe authors wish to acknowledge the financial support

provided by the National Science and Engineering Re-

search Council of Canada and the University of Alberta.

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