Good morning to one and all present here. Myself sriram and my batchmates nirmal and Praveen are here

to present a project on adiabatic mux, demux, priority encoder and priority decoder using adiabatic logic.

Our project guide is Mrs. Poongzhuali.

I will first explain in short of what we have done in this project. This project presents an adiabatic logic based 81 mux, 18 demux, 42 priority encoder and 24 priority decoder and compares its performance

with standard adiabatic logic styles such as ECRL, PFAL and 2n2n2p.

When compared the proposed logic is found to be efficient than the standard adiabatic logic styles.

Efficiency is estimated based on Total power dissipation, Area and Transistor count. Simulation is carried

out using NI-Multisim software.

First of all, why do we need to go for low power vlsi design techniques?

The growing market of portable (e.g., cellular phones, gaming consoles, etc.), battery-powered electronic

systems demands microelectronic circuits design with ultra low power dissipation. As the integration, size,

and complexity of the chips continue to increase, the difficulty in providing adequate cooling might either

add significant cost or limit the functionality of the computing systems which make use of those integrated

circuits.

The mobile device consumer demands more features and extended battery life at a lower cost. Due to

limited power supplied by batteries the circuits involved in these devices must be designed to

consume less power. Also large power dissipating device requires expensive noise cooling machinery

which increases cost and reduces reliability.

An integrated low power methodology requires optimization at all design abstraction layers such as:

1. System: Partitioning, Power down

2. Algorithm: Complexity, Concurrency, Regularity

3. Architecture: Parallelism, Pipelining, Redundancy, Data Encoding

4. Circuit Logic: Logic Styles, Energy Recovery, Transistor Sizing

5. Technology: Threshold Reduction, Multithreshold Devices.

In these layers we have opted for Energy Recovery in Circuit Logic layer.

Now we will see about adiabatic logic which uses Energy Recovery technique.

Adiabatic Logic is the term given to low-power electronic circuits that implement reversible

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logic. The term comes from the fact that an adiabatic process is one in which the total heat or energy

in the system remains constant.

This logic reduces the power by giving stored energy back to supply, therefore called as reversible logic.

CMOS technology, though fairly efficient when compared to other similar technologies,

dissipate energy as heat, mostly when switching. In order to solve this problem, there are two

fundamental rules CMOS adiabatic circuits must follow, the reasons for which are explained below.

1. The first is never to turn on a transistor when there is a voltage difference between the drain and source.

2. The second says never to turn off a transistor that has current flowing through it.

If the above rules are met during four-phase power clock then considerable energy saving can be done.

Now we will see how the CMOS charging process works and compare it with adiabatic charging.

A load capacitance CL, representing the input capacitance of the next logic stage and any

parasitic capacitances, is connected to the DC supply voltage Vdd through a pull-up block composed

of pFET's and to ground through a pull-down block of nFET's.

Energy stored in capacitor is half Cl vdd2

Because energy is conserved, the other half must be dissipated by the pFET's in the pull-up network

Thus, from an energy conservation perspective, the conventional case represents a maximum of

wastefulness

Now considering the case of adiabatic charging Assume a constant current source that delivers the charge CLVdd over a time period T, the

dissipation through channel resistance R is then

Ediss = P.T = I2RT = (CLVdd/T)2R.T

= (RCL/T)CLV 2

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2

dd

Reversible logic uses the fact that a single clock cycle is much longer then RC and thus attempts to

spread the charging of the gate over the whole cycle and thus reduces the energy dissipated.

Equation (4) shows that it is possible to charge and discharge a capacitance through a resistance

while dissipating less than CLVdd of energy.

It also suggests that it is possible to reduce the dissipation to an arbitrary degree by increasing the

switching time to ever-larger values. This is called as adiabatic charging. For T>2RC:

Energy dissipation of Adiabatic circuit < Energy dissipation of Conventional CMOS

Now we will see how energy is recovered in circuits using adiabatic logic. The adiabatic amplifier is a simple buffer circuit that uses adiabatic charging to drive

capacitive load. The T gate is built from an nFET and a pFET connected in parallel. To tie the T -gate

with minimal on-resistance, the gate of the pFET is grounded and the gate of the nFET is tied to Vdd .

Input is set to a valid value

Amplifier is energized by applying VA, a slow voltage ramp 0 to Vdd

If ramp is slow when compared to RC one of the load capacitance will be adiabatically charged

through T gates.

Output signal is now valid and can be used as input to other circuits.

Amplifier is denergized by ramping voltage on VA back to zero.

Signal energy stored on load flows back into power supply connected to VA

Therfore energy is recycle

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Adiabatic Logic circuits are operated with an oscillating power-supply, the so- called power-clock.

We will now see the four phases involved in the power clock.

In the evaluate (E) interval, the outputs are evaluated from the stable input signals. During the hold (H) interval, outputs are kept stable for supplying the subsequent gate with a

stable input signal.

Energy is recovered in the interval called recover (R). For symmetry reasons a wait (W) interval is inserted, as symmetric signals are easier and

more efficient to be generated.

The power clock can be trapezoidal or sinusoidal supply voltage.

Sinusoidal waveforms represent a reasonable approximation to the required four- phases.

However, the sinusoid deviates from the ideal waveform substantially in the Idle and Hold

phases.

I will now explain the devices which are implemented in the project using adiabatic logic technique

MULTIPLEXER:

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line.[1] A multiplexer of 2n inputs has n select lines,

which are used to select which input line to send to the output.[2]

An electronic multiplexer makes it possible for several signals to share one device or resource, for

example one A/D converter or one communication line, instead of having one device per input signal.

The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing

the input pins and the short parallel side containing the output pin and An electronic multiplexer can be

considered as a multiple-input, single-output switch

DEMULTIPLEXER:

Conversely, a demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input

.

PRIORITY ENCODER:

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A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the original number starting

from zero of the most significant input bit. They are often used to control interrupt requests by acting on

the highest priority request.

If two or more inputs are given at the same time, the input having the highest priority will

take precedence.[1] An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are to

the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output since it is

superseded by higher-priority input. The output V indicates if the input is valid.

PRIORITY DECODER:

Decoder is a combinational circuit which does the reverse operation of encoder, undoing the encoding so

that the original information can be retrieved. It converts binary info from n input lines to a max of 2n

unique output lines.

There are various standard adiabatic logic styles of which we are using ECRL, PFAL and 2n2n2p

in this project for comparison. I will explain those standard logic styles one by one.

First ECRL:

The gate consists of two cross-coupled PMOS devices that are used to store the information.

The logic function is constructed via two NMOS devices. Cascaded gates are operated by a four-

phase power-clock signal. Input signals for the ECRL gate in Fig.

3.6 are shifted by 90 with respect to the applied power-clock signal.

Now for instance it is assumed, that input in is at logic one and the dual input in is at zero.

Then the NMOS device N1 will conduct and connect out to ground, while N2 is disabled. As soon as

the power-clock ramped from 0 to VDD reaches the threshold voltage Vth,p of the PMOS device,

P2 will be turned on. Thus the output signal out will follow the power-clock .

Now the gate voltage of device P1 is equal to the supply voltage, the gate-to- source

voltage is zero, thus this device stays disabled. As soon as reaches the maximum level VDD the

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input signals are ramped down, as the preceding gate recovers the energy at this time. The PMOS

devices will take care of storing the information while both NMOS devices are disabled.

Then the power-clock is descending from VDD to 0. While is above Vth,p charge from the

output out is restored to . A certain fraction of energy

1/2 CoutV 2 th,p remains on the according output capacitance that is dissipated or reused in

the next cycle, according to the succeeding input signals.

SECOND 2N2N2P:

This adiabatic logic family was derived from ECRL in order to reduce the coupling

effect. Figure 5 shows the general schematic.

The primary advantage of 2N-2N2P over ECRL is that the cross-coupled nMOSFETs

switches result in non-floating outputs for large part of the recovery phase.

Size is comparable to conventional circuits, complexity and timing are similar to that of other

practical adiabatic computing circuits.

Third PFAL:

Two n-trees realize the logic functions. This logic family also generates both positive and

negative outputs. The two major differences with respect to ECRL are that the latch is made by two

pMOSFETs and two nMOSFETs, rather than by only two

pMOSFETs as in ECRL, and that the functional blocks are in parallel with the transmission

pMOSFETs.

Thus the equivalent resistance is smaller when the capacitance needs to be charged.

During the recovery phase, the loaded capacitance gives back energy to the power supply and

the supplied energy decreases.

I will now explain the idea behind the proposed logic.

the circuit diagram of an inverter portrays the proposed logic having addition of two extra

MOS transistors one PMOS above and one NMOS below. The usage of these additional transistors

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results in the reduction of power of the circuit.

It follows the conventional CMOS logic, driven by a single power supply PCLK. The pull-up

end has the extra PMOS connected to it, while the pull-down end has the extra NMOS. In the

evaluation phase of the power supply PCLK, it swings up and is followed by the output and in its

recovery phase, it swings down and the voltage stored

at the load capacitor is transferred back to the supply PCLK. In this way, the energy is recovered

from the output node.

Now we will see the circuit design of combinational gates in series and parallel structure.

For nMOS pull down network the AND expressions may be implemented in series and OR experessions

in parallel.

For pMOS pull up configuration we must compute the complementary expression using the switches that

turn on with inverse polarity. By De-morgans Law this is equivalent to interchanging AND and OR

expressions. Hence the transistors that appear in series in the pull-down network must appear in parallel

in pull-up network and vice-versa. Putting the networks together yields the connection diagram.

The proposed circuit for 81 Multiplexer consists of 3 selection inputs which selects appropriate input

signal and sends it through output. It also consists of a pullup transistor connected to PCLK and pull

down transistor connected to ground.

Same for demux

The tabular column shows the simulated results of the circuits for comparison. Comparison is done

based on transistor count, area and total power dissipation.

(Explain with example that proposed is better than others)

By seeing the simulation results we can conclude that the proposed logic is found to be superior over other standard adiabatic logic styles. Future work of this project involves implementing these circuits using Asynchrobatic logic which

is combination of two other logics and found to be more efficient in low power VLSI design.

It is a novel low-power design style that combines the energy saving benefits of asynchronous logic

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and adiabatic logic to produce systems whose power dissipation is reduced in several different ways.

The term Asynchrobatic is a new word that can be used to describe these types of systems, and

is derived from the concatenation and shortening of Asynchronous, Adiabatic Logic. The substantial challenge include merging the clock-powered adiabatic logic and asynchronous logic

which operates without synchronous clocks (uses a handshaking protocol to facilitate inter-stage

communication)

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