40G Signal Tap (sniffer) – Yearly Project Part 1 – 10G Signal Tap

Midterm presentation

Intel: Lan Access DivisionTechnion: High Speed Digital

Systems LabBy: Leonid Yuhananov &

Asaad MalshySupervised by: Dr. David Bar-On

1. Goal2. High Level Specifications:

Project definition. HL Block diagram.

3. Detailed Block View: Transceiver channel. Processing block. Logic Analyzer Logic Analyzer Interface (LAI).

4. Plan Gantt chart. Deliverables:

Semester 10G. Yearly 40G.

5. Demo - TBD

10G Tap agenda

We want to tap onto 40G traffic and present it in a useful way.

Tap: Listen to the Link.◦ Sniff the data transmitting on the line.

Present: View data on Logic analyzer.◦ Parse the data into Ethernet II frames.

Useful: Easy to read and good for debug.◦ Only the frames we are interested in will be presented.

Goal“Tracing 40Gbit Ethernet on a logic analyzer”

1. Goal2. High Level Specifications:

Project definition. HL Block diagram.

3. Detailed Block View: Transceiver channel. Processing block. Logic Analyzer Logic Analyzer Interface (LAI).

4. Plan Gantt chart. Deliverables:

Semester 10G. Yearly 40G.

5. Demo - TBD

10G Tap agenda

In the Ingress direction:◦ 2 10g optical lines in differential operation mode.

In the egress direction:◦ 34x2 156.25Mbps channels to logic analyzer.

Display:◦ Output will be displayed on the logic analyzer in

Ethernet II frame structure.

Project Definition

High Level Block Diagram

SFP+ (optical Module): Converts the optical signal to an electrical one. Transceiver channel:

◦ Physical Transceiver Channel: converts high speed serial data to lower speed parallel.◦ In charge of decoding and data rate conversion and alignment.

Processing block: the unit that processes the data and generates the trigger due to our requirements.

LAI: Prepares the parallel data for external LA interfacing.

1. Goal2. High Level Specifications:

Project definition. HL Block diagram.

3. Detailed Block Definitions: Transceiver channel. Processing block. Logic Analyzer Logic Analyzer Interface (LAI).

4. Plan Gantt chart. Deliverables:

Semester 10G. Yearly 40G.

5. Demo - TBD

10G Tap agenda

Receiver PMA:◦ CDR– generates the transceiver clocks used to clock the receiver PMA and PCS blocks.◦ Deserializer-Converts the high speed serial data to lower speed parallel bus.

10G BASE-R PHY:◦ RX Gearbox: Is responsible for translating the 40-bit wide data from the receiver

channel into 66-bit wide data to the PCS.◦ 10G BASE-R PCS: It is responsible for functions such as 66B/64B decoding,

descrambling, thus resulting in 8 one byte words + 8bits control word totaling 72 bits in the appropriate data rate.

Transceiver Channel:

Programming Flow:1. blocks going into our processing blocks and pass

through a series of filters.2. Using the control words, the data structure in

the frames is determined.3. The data words enter a FIFO queue.4. When the required pattern is detected, a trigger

is generated.5. Both the data and the trigger are ready for the

DDR output which is later read by the LA.

Processing Block High Level:

Block Diagram:

The data that enters to the block from the PHY isn’t aligned.

Goal : Align data that comes from PHY

The 66B/64B protocol Start control word indicates start of packet. While between the Ethernet frames there are inter-frame idles *. Terminate control word indicates end of packets

*There is minimum of 12 Idles between each Terminate and Start

The output of processing block: The start control word indicates the beginning of packet. The start word is always aligned to the “top” word.

Processing Block and aligner:

RTL Block Diagram:

Start D Idle D Idle D T StartD D Idle D Idle D Idle DD D Idle D Idle D Idle DD T Idle D Idle D Idle DD Idle Idle D Idle D Idle DD Idle Start D Idle D Idle DD Idle D D Idle D Idle DD Idle D T Start D Idle D

CLK

Start D Start D Start D I1 StartD D D D D T Idle DD D D T D I7 Idle DD T D I5 D I6 Idle DD Idle D I4 D I5 Idle DD Idle D I3 D I4 Idle DD Idle D I2 D I3 Idle DD Idle D I1 D I2 Idle D

Start

D

D

D

D

D

D

D

D Start

D D

D D

T D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle T

Idle Idle

Start Idle

D Idle

D Idle

D Idle

D Idle

D Idle

D Idle

D Idle

D Start

D D

T D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle D

Start T

D Idle

D Idle

D Idle

D Idle

D Idle

D Idle

D Idle

D Start

T D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle D

Idle D

Start T

D Idle

D Idle

D Idle

D Idle

D Idle

D Idle

D Idle

Aligner Buffer

Data In

Aligned Data

Aligner demo

The operation of alignment requires a lot of information on our incoming data, and this information is provided by an array of blocks.

Detector – Receives all data and provides 3 signals for each of the 8 words indicating Start/Terminate/Idle for each word.

Start locator – checks if there is a Start at the input frame, and returns place of Start and a “start exists” bit.

Terminate locator – checks if there is a Terminate at input frame, returns place of Terminate and a “terminate exists” bit.

The Aligner – if Start frame exists then it pushes bytes beginning with the Start (included) to FIFO. If Terminate exists then it pushes idles after Terminate (included) to FIFO, Idle* if there was a loss of idles.

Idle Padding Block – Generates Idle* until all idles lost are returned (counted internally).

FIFO – our output FIFO Trigger Generator - search for certain pattern and if

matched provides a Trigger signal to the LA. Trigger Pattern Block – provides the pattern wanted by

user.

Other Processing Blocks:

A logic analyzer is an electronic instrument which displays signals in a digital circuit. A logic analyzer may convert the captured data into timing diagrams, protocol decodes, state machine traces.

TLA7000 Series 6,528 Logic Analyzer Channels 500 ps (2 GHz) – serial data 312.5 ps (3.2 GHz) – signal integrity 625 ps (1.6 GHz) MIPI

Logic Analyzer

The double data rate is our output to the outer world (Logic Analyzer).

Since we want to utilize less LA pins using higher speeds, a double data rate is required.

Should be considered as a serializer, from 2 or more lines of a certain data rate, to a single line of double or more data rate.

The operation is based on a high speed DeMux, with a round around counter for its select bits.

DDR – Double Data Rate

1. Goal2. High Level Specifications:

Project definition. HL Block diagram.

3. Detailed Block Definitions: Transceiver channel. Processing block. Logic Analyzer Logic Analyzer Interface (LAI).

4. Plan Gantt chart. Deliverables:

Semester 10G. Yearly 40G.

5. Demo - TBD

10G Tap agenda

Gantt

Creating a basic data path using Altera. Designing the micro-architecture of our final

solution. Design of each block on logical level. Integration.

Next

Thank you all

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