3d_integration_publishable_faun.pdf

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Frank Niklaus, December 8, 2008

3D Platforms for

IC Integrated MEMSFrank Niklaus, Gran Stemme

Email: [email protected]

Mobile: +46 76 216 73 49

KTH - Royal Institute of TechnologySchool of Electrical EngineeringMicrosystem Technology Group

Stockholm, Sweden

Faun AB, Swedenwww.fauninfrared.com


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Research Topic: MEMS

Total Staff: 24

16 Ph.D. Students

6 Senior Ph.D.

Microsystem Technology at KTH Stockholm, Sweden

KTH Semiconductor Laboratory in Kista

1200 m2 clean room area

MEMS process technologies up to 8 inch wafers

Bio & MedMEMS

RF

MEMS

IC Integrated

MEMS


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Outline

What is heterogeneous wafer-level 3D integration?

Heterogeneous 3D integration of MEMS and ICs

3D IC integrated MEMS platforms with via-last approach.

3D IC integrated MEMS platforms with via-first approach.

IC compatible wafer-level MEMS packaging


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Heterogeneous Wafer-Level 3D Integration (More than Moore)

Heterogeneous integration is generally defined as the integration of two or

more compounds.

Heterogeneous wafer-level 3D integration can be defined as stacking and

interconnecting wafers, typically prepared with diverse technologies and / or

materials.

WafersSequentially

align, bond,thin andinterconnect

Processor/Logic

Memory

I/Os, A/Ds, sensors

and/or MEMS

I/Os, A/Ds, sensorsand/or MEMS

3-D ChipStack

3-D ChipStack

Image source: RPI, USA


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Heterogeneous 3D Integration of MEMS and ICs

New MEMS designs, funct ionalit iesNew MEMS designs, funct ionalit ies

and material combinations.and material combinations.

High perform ance MEMS materialsHigh perform ance MEMS materials

on standard foundry I Cs.on standard foundry I Cs.

Very high integration densities forsmaller and cheaper components.

CMOS I C

MEMSAdvan tages :

D isadvan tages :

May not be economic if IC and MEMS partsare very different in size.

Severe penalty in yield accumulation when stacking

several layers (not typical for MEMS).

Image source: KTH-MST


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Via Last:

Heterogeneous 3D Integration Concepts

Via First:

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

El. Contacts/Vias

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

El. Contacts

Device Layer 1

Wafer 1

Device Layer 2

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

(a) El. via deposition prior to bonding. (b) Wafer bonding incl. via formation.

(a) Wafer preparation. (b) Wafer bonding and device release. (c) Via hole etching and via deposition.

Image source: Modified from RPI, USA


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Outline

What is heterogeneous wafer-level 3D MEMS integration?






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Heterogeneous 3D Integration Using Via-Last Approach

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

El. Contacts

Device Layer 1

Wafer 1

Device Layer 2

Device Layer 1

Wafer 1

Device Layer 2

(a) Wafer preparation. (b) Wafer bonding and device release. (c) Via hole etching and via deposition.

Advantages:

Extreme reduction of via and device

dimensions (sub m) at high yield possible.

No wafer-to-wafer alignment during

bonding needed (cost efficient).

Post-bond processing identical to surface

micromachining.

Disadvantages:

MEMS devices must be processed

after bonding.

Only face-to-face bonding practical.



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Wafer Bonding for Via-Last Approach

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

Direct wafer bonding:

=> R&D mainly focused on 3D ICs (i.e. Ziptronix).

Some R&D on IC integrated MEMS

(Fraunhofer, some universities).

Wafer surface treatment and planarization

needed.

Sensitive to particles.

Adhesive wafer bonding:

=> Extensive R&D for 3D IC integrated

MEMS ongoing (e.g. KTH, Faun).



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Proprietary 3D IC Integrated MEMS Platform at KTH

IC Wafer

SOI Wafer

(a)

IC Wafer

SOI Wafer

(b)

IC Wafer

(c)

IC Contact Pads

Mono-Crystalline Si

Polymer Adhesive

IC Wafer

SOI Wafer

(a)

IC Wafer

SOI Wafer

(b)

IC Wafer

(c)

IC Contact Pads

Mono-Crystalline Si

Polymer Adhesive

IC Wafer

(d)

IC Wafer

(e)

IC Wafer

(f)

Via Holes Vias IC-Integrated MEMS

IC Wafer

(d)

IC Wafer

(e)

IC Wafer

(f)



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Mono-Si MEMS can be integrated on any foundry ASIC.

Polymer adhesive can be used as sacrificial layer for dry

release etch.

Easy migration from one ASIC technology node to the next

without changing the MEMS process. MEMS foundry compatible.

No wafer-to-wafer bond alignment required.

No wafer surface planarization required.

Works practically with any wafer material.

Low-cost, easy to use and high yield process.

3D IC Integrated MEMS Platform Features


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Examples of 3D Integrated MEMS

Micro-mirror Arrays

IR Bolometer Arrays

RF MEMS devices


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Spatial Light Modulators (SLMs)

Mono-crystalline silicon micro-mirrors on ICs (FP6-Q2M)

Goal: Improvement of mechanical and surface mirror properties 3D MEMS-IC integration using adhesive wafer bonding

Applications

DUV lithography using tilting mirrors

Wavefront correction using piston mirrors

KTH-MST and Fraunhofer IPMS


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Micro-mirror arrays for DUV lithography (Tilting mirrors) For Mask-writing systems.

UV illumination.

Step-and-Repeat lithography.

Analogue tilt actuation in 16 steps(gray-tones) possible.

1 million mirror array.

(mirror size 16 x 16 m2). Single mirror actuation possible with

underlying CMOS.

Spatial Light Modulators (SLMs)

Source: Zimmer, Fraunhofer IPMS


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Torsional Micromirrors

Haasl, 2002

Distance

Holders

Addressing

Electrode

MirrorMembrane Torsional Hinges

Posts

(Vias)



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Si Mirror Integration: SOI and IC wafer

Thermistor Material (e.g.Si)

SiN

Al

SiO2MoSi

Ti

Au

SOI Wafer

CMOS IC


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Glue

Si Mirror Integration: Dispense Glue

CMOS IC

SOI Wafer


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Glue

Si Mirror Integration: Adhesive Wafer Bonding

CMOS IC

SOI Wafer


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Glue

Si Mirror Integration: Sacrificial Wafer Thinning

CMOS IC


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Glue

Si Mirror Integration: Removal of SiO2 Etch-Stop

CMOS IC


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Glue

Si Mirror Integration: Via Formation

CMOS IC


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Glue

Si Mirror Integration: Mirror Formation

CMOS IC


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Si Mirror Integration: Mirror Release

CMOS IC


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Torsional Mono-Si Micromirror Arrays


Image source: MST NEWS 2008


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SLMs for Adaptive Optics in Astronomy and Microscopy

Wave-front correction using piston mirrors


Lapisa KTH-MST, Gehner, Fraunhofer, 2008


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Mono-crystalline silicon mirrors for AO



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Mono-crystalline silicon mirror arrays



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Mono-crystalline silicon mirror arrays



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http://sirtf.caltech.edu

Infrared Imaging

Uncooled Infrared Bolometer Arrays


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Operation of Bolometer Arrays

Buttler, 1995


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Proprietary 3D IC Integration of IR Detectors at KTH / Faun

IC Wafer

SOI Wafer

(a)

IC Wafer

SOI Wafer

(b)

IC Wafer

(c)

IC Contact Pads

Mono-Crystalline Si

Polymer Adhesive

IC Wafer

SOI Wafer

(a)

IC Wafer

SOI Wafer

(b)

IC Wafer

(c)

IC Contact Pads

Mono-Crystalline Si

Polymer Adhesive

IC Wafer

(d)

IC Wafer

(e)

IC Wafer

(f)


IC Wafer

(d)

IC Wafer

(e)

IC Wafer

(f)


Epitaxially grown Si/SiGe material with high TCR and low 1/f noise.

Monolithic integration on IC not possible.

=> 3D MEMS IC integration


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Si-Based Bolometer on Fan-Out-Board

16x 16 I R Bo lom e te r A r ray


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RF MEMS: Radar Beam Steering with MEMS Tuneable Metamaterials

Image source: Sterner, KTH

Col labora t ion

App l i ca t i ons

car radar

77GHz

high-capacity

comm. links

Col labora t ion

App l i ca t i ons

car radar

77GHz

high-capacity

comm. links

Frequency, GHz

Reflectionpha

se

180

0

-180

Frequency, GHz

Reflectionpha

se

180

0

-180

Tuned gradient


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RF Metamaterial Design of Fabrication Process

glass substrate500 um

gold, 1 um

BCB, 5-10 um

glass,100 um

gold, 1 um

SiN isolation0.2 m

gold, 0.5 um

gold, 0.5 um

silicon, 1 um

air gap 1.5 um 3-electrodetuneable capacitor

for extended tuning range



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RF Metamaterial Fabricated Device Array

Arrayof20052elements

Etch hole

Gapof~1.5m

Springs


RF MEMS PZT S i h


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RF-MEMS PZT Switch

Structural layer:Monocrystalline Silicon / SiN

Actuator:

Lead zirconate titanate (PZT)

Transmission line(gold)

Image source: Saharil, KTH

Ph t i MEMS I t ti f G A IC


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0.7 mGaAsFilm

4-inchSilicon

Wafer

Photonic MEMS: Integration of GaAs on ICs

Adh i W f B di i K


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Gluing two (wafer) surfaces together

Adhesive Wafer Bonding is Key

Semiconductor Wafer

Semiconductor Wafer

Glue

Working Principles of Adhesives


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Contact between two solidsurfaces.

Contact between a solidsurface and a liquid.

Working Principles of Adhesives

Polymer Adhesives


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Polymer Adhesives

Polymers can transform from a liquid into

a solid state by:1. Drying (solvents or water evaporate)

2. Heating and cooling (thermoplastic polymers)3. Curing (chemical reaction forming larger molecules,

thermosetting polymers) e.g. mixing of two components heating UV-light illumination

Suitable Polymer Adhesives


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Suitable Polymer Adhesives

Thermosetting polymers BCB (Dow Chemical), chemically stable,


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Deposition of Thin Polymer Layers

Alternative polymer deposition techniques are:

spraying, evaporation, screen printing, stamping, electro

deposition, lamination, etc.

Standard technology

Wide thickness range of

coatings (0.1 m to 50 m) Very uniform coatings

Wafer

LiquidPolymer

Spin Coating

Adhesive Wafer Bonding Process


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Adhesive wafer bonding in commercial bond equipment.

Bend Pin

Wafer 1

Wafer 2

Bond Fixture

VacuumBond Chamber

Clamps

Spacers



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Adhesive wafer bonding in commercial bond equipment.

Bend PinTop Chuck

Force

HOT

Wafer 1

Wafer 2Wafer 2

Bond Fixture

VacuumBond Chamber

HOT

Important Bonding Parameters


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Important Bonding Parameters

Polymer adhesive (no outgassing and no dryingadhesives).

Bonding pressure.

Reflow time during bonding.

Wafer thickness.

Atmosphere in the bond chamber.

Level of polymerisation (cross-linking) before bonding (forthermosetting polymers).

Relation between wafer topography features and polymerthickness.

Influence of Wafer Topography on Void Formation


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Influence of Wafer Topography on Void Formation

H.D. Rowland et al. 2005


Cross-Linking and Viscosity of BCB Dependent on Time and Temperature


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g y p p

Image source: Dow

Keyed Alignment in Adhesive Bonding


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Keyed Alignment in Adhesive Bonding

Image source: Lee, Niklaus 2006

Outline


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Outline






Heterogeneous 3D Integration Using Via-First Approach


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Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

El. Contacts/Vias

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

(a) El. via deposition prior to bonding. (b) Wafer bonding incl. via formation.

Advantages:

Simple process with via formation

during bonding (cost efficient).

Complete device preparation priorto bonding possible.

Face-to-face and face-to-back

wafer bonding possible.

Disadvantages:

Need for wafer-to-wafer alignment.

Limitation in via-size reduction and

potential yield issues.

Possible air-gap between wafers.

Heterogeneous 3D Integration Using Via First Approach


Wafer Bonding for Via-First Approach


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Wafer Bonding for Via First Approach

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

El. Contacts/Vias

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

Metal via bonding and parallel

adhesive or direct bonding:=> R&D mainly focused on 3D-ICs

E.g. parallel metal and adhesive bond (RPI)

and parallel metal and direct bond (Ziptronix).

=> R&D for IC integrated MEMS not known.

High requirements on surface planarity.

Sensitive to particles.

Metal via bonding with optional

adhesive support structures:

=> Extensive R&D for 3D IC integrated

MEMS ongoing (e.g. IBM Zrich, universities).

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2

El. Contacts/Vias

Device Layer 1

Wafer 1

Device Layer 2

Wafer 2


IBMs Millipede Data Storage


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p g

Arrays of membrane tips that can create pits with a side length ofabout 10 nm using heating of the polymer surface.

4000 tips on a 6.4 mm x 6.4 mm area can store the data of 25 DVD.

Vettinger, 2002

Manufacturing of the Millipede Read-Write Head


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g p

Vettinger, 2002

Transferred Read-Write Cantilevers


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Frank Niklaus, December 8, 2008Vettinger, 2002

Outline


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Room-Temperature Wafer-Level Hermetic Sealing of Cavities


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(a) (c)

(b)

(a) (c)

(b)

Overlap bondingarea (black lines)

Sealing ring onwafer 2

Sealing ringson wafer 1

Overlap bondingarea (black lines)

Sealing ring onwafer 2

Sealing ringson wafer 1

a. Wafer 2

Wafer 1

SealSealing Ringsdefining a cavity

Wafer 1

Sealed cavities

Cold welding atoverlapping areas

Wafer 2

Wafer 1

Sealed cavities

Cold welding atoverlapping areas

Wafer 2

1 .

2 .

Decharat, 2007

Localized Adhesive Wafer Bonding Process


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Polymer depositionSilicon Wafer

Photoresist

Polymer Adhesive

Silicon Wafer

Silicon Wafer

Top Wafer

Adhesive wafer bonding

Lithographic patterning

of the polymer (using

photoresist mask anddry etching)

Localized Adhesive Wafer Bonding


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Silicon Wafer

Glass Wafer

Oberhammer, 2001

Top View

Wafer-level Packaging of MEMS


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Frank Niklaus, December 8, 2008Oberhammer, 2003

Wafer-Level Fabrication of Cavities for MEMS Packaging


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Potentially cheaper

than chip packaging.

Protects devicesduring dicing.

Packages need tobe hermetic (gas-tight).

Polymers are permeable

to moisture.

Casco Nobel, 1992

Polymer Molecules

H2O

Wafer-Level Hermetic Sealing of Cavities


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Wafer 1

Wafer 2 (Capping Wafer)Adhesive

Wafer 1

Sealed Cavity

Wafer 1

Diffusion Barrier(e.g. Silicon Nitride or Metal)

(1)

(2)

(3)

Fabrication ofcavities

Dicing and etching

of top wafer

Deposition of adiffusion barriermaterial

Hermetically Sealed Cavity


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PECVD SiN as

aditional diffusionbarrier material hasbeen tested

He leak tests showsignificantly less Heabsorbtion of sealedcavities as

compared to nonsealed cavities

Oberhammer, 2002

Summary


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Adhesive and direct wafer bonding techniques are being used

for integrating MEMS and ICs.

Via-first and via-last platforms are being used with focus

currently on arrayed MEMS such as micro-mirror, IR

bolometer and AFM tip arrays.

Heterogeneous integration should also be attractive for IC

integrated inertia sensor, pressure sensors and microphones.


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Thank You For

Your Attention !

3d_integration_publishable_faun.pdf

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