3d stacking of silicon chips -...
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3D Stacking of Silicon Chips
Ft. Collins, March 5th, 2010
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
page 1
Werner WeberSenior PrincipalInfineon Technologies AG
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Outline
Introduction - trend in the semiconductor industry
3D Technologies
The European e-CUBES project
Application Scenarios
– DRAM
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
page 2
– Power
– Integrated Camera
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Increasing Cost Require Large Volumes or Entities
to keep Development and Invest Affordable
8
10
12
14
10,000
1,000
100
Typical Wafer Fab
Technology R&D
Product R&D
Cost Trends in Million $US
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Werner Weber5 March 2010
page 3Source: Credit Suisse CSFB, SCE Weekly, 10/27/04Semiconductor Business News 01/07/03 IC Insights, McClean Report 2002
0
2
4
6
1995 2000 2005 2010 20151995 2000 2005 2010
100
10
1
0.1
Litho Tool per piece
Mask Set for Logic Product
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Log (Monthly semiconductor revenues in Billion US $)
8.8
9.2
9.6
10.0
Annual growth rate: +16%
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Werner Weber5 March 2010
page 4
7.2
7.6
8.0
8.4
86 88 90 92 94 96 98 00 02 04 06 08
Revenue in US$
Trend line in the 90's
Present trend line
09
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A maturing Industry?
…… consolidation and concentration !!!????
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Werner Weber5 March 2010
page 5
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55%
60%
65%
70%
Decreasing Capacities with Latest Technologies
% capacities from top 2 leading edge nodes*
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Werner Weber5 March 2010
page 6
1998 2004
30%
35%
40%
45%
50%
Source: SIA, SICAS *in Wafer starts per month
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Scalability Limits for Several Technologies −Only Memory and
High-performance Logic Strictly follow ITRS Roadmap
IGBT
Bipolar-Analog
5,0
3,0
2,0
1,5
1,0
0,65
Min
imum
Fea
ture
Siz
e [µ
m]
(hal
f pitc
h di
men
sion
s)
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Werner Weber5 March 2010
page 7
Analog BiCMOS
1995 2000 2005 2010 2015
DMOS
RF BIPOLARRF BiCMOS
5V CMOS
CMOS logicDRAM
ITRSRoadmap
0,650,5
0,350,25
0,18
0,130,100,07
0,035
Min
imum
Fea
ture
Siz
e [µ
m]
(hal
f pitc
h di
men
sion
s)
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Observations
Increasing cost for development of newest technology generations and products
reduced growth rates
Reduced fraction of products in newest technology generations
Reduced miniaturization speed in special technologies such as Analog, Sensors, Power, High-voltage, Bipolar, Embedded NVM
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Analog, Sensors, Power, High-voltage, Bipolar, Embedded NVM (e.g. Shrink of Embedded Flash from 130 to 90 nm may provide only few percent cost reduction)
Due to reduced speed of productivity improvement: reduced importance of shrink scenarios that follow Moore's Law
However: An increasing number of niches provide swe et spots (foundry, equipment, fabless etc.)
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Trend
Moore‘s Law is no longer the only industry driver due to architectural and physical constraints
More-than-Moore is a new hype
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page 9
… but what means More-Than-Moore?
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Eniac Initiative in More than Moore
Beyond Silicon Design Platform Heterogeneous Integration Infrastructure, Access and Education Materials and Equipment
Heterogeneous Integration
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page 10
Materials and Equipment
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Heterogeneous Integration:The Integration of Si-Chips into Smart Modules
Yesterday Mostly PCB Some MCM
Tomorrow Lots of smart solutions
depending on applicationrequirements
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Werner Weber5 March 2010
page 11
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Outline
Introduction - trend in the semiconductor industry
3D Technologies
The European e-CUBES project
Application Scenarios
– DRAM
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
page 12
– Power
– Integrated Camera
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Examples for Heterogeneous Integration
Finepitch interchip vias
Coarsepitch interchip vias
Capacitive /inductive interchip communication
Traditional bond wires on chipstacks
µ-Flip Chip
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Werner Weber5 March 2010
page 13
µ-Flip Chip
MID
Stack of small PCBs
Bare die on PCB
… all of these are 3D integration
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Top Si
Al Cu
Cu3Sn
Cu6Sn5
Cu Sn
FIB of a 3 layer stack
Three-Layer Stack of Chips
Si
10 µm
Al
W
Cu
Cu 3 Sn
Cu
Oxide
1.2 µm
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Werner Weber5 March 2010
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Middle Si10µm
Al
Bottom Si
Cu3Sn
Cu
Cu
Cu3Sn
Cu
Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion BondingP. Ramm, A. Klumpp, R. Merkel, J. Weber, R. WielandInvited PaperJapanese Journal of Applied Physics Vol. 43, No. 7A (2004), p. L829-830
2 µm
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ASET‘s Coarse-pitch Process
Backside etch diameter 40 µm
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Werner Weber5 March 2010
page 15
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TransceiverChannel Array
N.Miura (ISSCC’05 #14.5)195Gb/s Inductive-Coupling Transceiver2.5/mm2/Tb/s, 6mW/Gb/s, Wired Clock
Inductive Communication
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Werner Weber5 March 2010
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This Work
Bottom Chip
Upper Chip15µµµµm
Channel Array
50µµµµm Inductor
Tx
Rx
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Baw Filter Package – Enabler for Stacking Technology
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Stacking of Memory Chips using wire bonds
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µ FC Technology Status
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MID-Version (Molded Interconnect Device)
Mitsui
3D substrate / flexible geometry
Limits in pad/conductor layout
Designrules ?
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Package on Package
OPC – One Package Computer
Assembly Controller TC1796A
LP 27x27mm² , bottom
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Microcontroller
Flash SRAM
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OPC – One Package Computer / Details
Packaging of the Controller
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PCB embedded Chips
50µm embedded chipTarget:
Simplification of packaging process by combination of logic and power interconnects in one process
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Thin chip
Via to chip Via to substrate
Adhesive Substrate core
Cu line
Development of an integration technology for increased number of pins
Simplification of value chain and reduction of cost
Cooperation with AT&S (PCB manufacturer)
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Outline
Introduction - trend in the semiconductor industry
3D Technologies
The European e-CUBES project
Application Scenarios
– DRAM
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
page 24
– Power
– Integrated Camera
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e-CUBES
3-D-Integrated Micro/Nano Modules for Easily Adapted Applications
21 partners from 11 European countries
total budget is € 20.8 Mio, requested grant € 12 Mio
Project kicked off Feb 1st, 2006, ran for three years until July31st
this project dealt with wireless sensor networks…
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this project dealt with wireless sensor networks…
… and 3D integration technologies
It implemented 3 different demonstrators (aeronautic, health and fitness, automotive)
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3D Integration Technologies
IZM-M:
Through Silicon Via
IMEC/IZM-B:
Thin Chip Integration
3D-PLUS:
Stacking of Packages
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Bottom-Chip
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TPMS ChipstackTPMS ChipstackTPMS ChipstackTPMS Chipstack
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Source: SINTEF
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D3 Progressive System Demonstrator with
Energy Harvesting Power Supply
3D Double Stack Integration3D Double Stack Integration3D Double Stack Integration3D Double Stack Integration3D Integration on Sensor level3D Integration on Sensor level3D Integration on Sensor level3D Integration on Sensor level
3D Integration on ASIC level3D Integration on ASIC level3D Integration on ASIC level3D Integration on ASIC level 3D Integration on System level3D Integration on System level3D Integration on System level3D Integration on System level
10 mm
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Energy Harvesting MEMS (WP 3.2)
Cap./thin film bat. a
ppr. 9
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..finished stacks
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Molded Interconnect Device
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e-BRAINS is the successor to e-CUBES
Best-Reliable Ambient Intelligent Nanosensor Systems by Heterogeneous
Integration
again 21 partners
total budget is € approx. 15 Mio, requested grant € 10 Mio
Project will kicked off June 1st, 2010, will run for three years
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this project deals with small geometry applications …
… using heterogeneous integration
It implemented 5 different demonstrators
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BRAINS sensorsyste
m
Best reliability & perform
ance
e-BRAINS benefits from e-CUBES:novel 3D-enabled nano sensing applications
CUBES
European
3D Technology Platform
Nano Sensors Smart ommunicationEnergy Management
Low-T TSV technology (TSV-SWACF) 3D
Low-Cost 3D-WLP(TCI/UCTS) 3D
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page 32
e-B
RAINS sensorsyste
m
Best reliability & perform
ance
e-C
UBES
European
3D Technology Platform
3DHigh-Performance Interposer (PAECE)
3D
3DChip Stacking 3D-SIP (WDoD)
Layer Transfer Bonding (LTfB) 3D
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Technology Platforms and Applications in e-BRAINS
Heterogeneous integration
Smart Biosensor Grain(MAGNA)
Air Quality System (SIE)
Active Medical Implant(Sorin/ELA)
Infrared Imager(Sensonor)
Applications
Smart Ultra-Sound Imaging Probe
(VERMON)
TSV-SLID/ SWACF
Layer Transfer
PAECE & Liquid Fill
WDoDThrough
Polymer Via;
TCI/ UTCSThin Chip
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page 33
integration technologies
High-performance
Communication and antennae
(IFAT, EPFL)
Technology Components
SWACFLow-T IMC or
SWACF Bonding (IZM, Tyndall)
Transfer Bonding (SINT)
Liquid FillHigh-Perform.Interposer & 1step wiring(Siemens)
Polymer Via; Wireless Die on
Die(3DPlus)
Thin Chip Integration(IMEC, IZM,
IFX)
General technological inputs to applicationsHeterogeneous integration technology inputs to applicationsHeterogeneous integration technology inputs to general technologies
Nano structuresFunctionalized for sensing
(EPFL/SIE/Tyndall/SINT/IQE)For optical field manipulation
(SINT/SIE)
High-efficient
Energy Management
(IFAT, DICE)
Reliability (Infineon, TUC, SIE, IZM)
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Outline
Introduction - trend in the semiconductor industry
3D Technologies
The European e-CUBES project
Application Scenarios
– DRAM
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
page 34
– Power
– Integrated Camera
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SDRAM Data Rate Roadmap: Approx. 26% Annual Growth Rate
600
1000
2000
800
Per
Pin
Dat
a R
ate
[Mb/
s]Why 3D stacking of DRAMs?
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1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009100
200
400
600
Per
Pin
Dat
a R
ate
[Mb/
s]
Year of Market Introduction
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3D stacked DRAMs for power saving
Example for Termination Scheme in Application:
Transaction Slot 1 Slot 2
Write to Slot 1 RTT_WR=120 Ω RTT_Nom=20 ΩWrite to Slot 2 RTT_Nom=20 Ω RTT_WR=120 Ω
TerminatingReceiving
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Controller
TL TL
TerminatingDRAM
TLDIMM
ReceivingDRAM
TLDIMM
Write to Slot 1:
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Example Memory
Support functions run permanently on all memory devices today (about 1W/device) Command decoders Synchronization circuits On-die termination
Increased power consumption with increased clock speed
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Werner Weber5 March 2010
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By increased integration level support functions need to run only on ‘master’ chip
major power saving
Recent result from 3D conferences and studies of marketing institutes some more delay for introduction of TSV in DRAMs (Elpida/Samsung)
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recent announcements
Elpida and Samsung are doing 3D today (Stacked Chips, Wirebonding, PoP); to enter markets with TSV solution in 2011
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Werner Weber5 March 2010
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Activities at NXP … just an example
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
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Conventional Complex Discrete Package concept Embedded Discrete
Qual tests ongoing:
− PC acc. To MSL1 level− TMCL: -65/+150 °C, 1000 cycles. − PPOT: 96 hrs, Rh = 100%, 1atm, 121 °C.
− HTS: 1000 hrs, 175 °C
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Trend (exploitation strategy)
Do Coarse-pitch Via first and get immediate benefit from chip area saving
… continue on with small-size vias and get benefit from redesigned large logic chips (should be started only when decent manufacturing experience on coarse-pitch via is available)
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Existing Product: Toshiba Camera Module
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Toshiba HEK3 VGA sensor
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3D stacked image sensors for size reduction
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Toshiba’s small size camera system with Through Si-Vias for mobile phones
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Final Conclusions
The world is getting more complicated
– In the chip industry
– and in the sub-trend of system integration
New system integration solutions provide solutions for specific application – no standardization seen
– More special solutions?
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– More special solutions?
– How about platforms?
Changes in the value chain
– PCB can lose due to alternative solutions such as MID or chip stacks ?
– PCB can gain by migrating into the chip packaging area such as mounting bare dies ?
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Never stop thinking.
Copyright © Infineon Technologies 2005. All rights reserved.
Werner Weber5 March 2010
page 44