3_cmosfabrication(1)
TRANSCRIPT
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CMOS & BiCMOS Fabrication
ByCh. Praveen Kumar
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Complementary MOS fabrication Types
• CMOS Technology depends on using both N-Type and P-Type devices on the same chip.
• The two main technologies to do this task are:– P-Well
• The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.
– N-Well• The substrate is P-Type. The N-channel device is
built directly on the substrate, while the P-channel device is built into a N-type well within the parent P-Type substrate.
• The Berkeley n-well process as an example, in order to look more closely at typical fabrication steps.
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Complementary MOS fabrication Types
• Two more advanced technologies to do this task are:• Becoming more popular for sub-micron
geometries where device performance and density must be pushed beyond the limits of the conventional p & n-well CMOS processes.
– Twin Tub• Both an N-Well and a P-Well are
manufactured on a lightly doped N-type substrate.
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N-Well CMOS Fabrication Process
Wafer:
A bare Si wafer is chosen
The type will be n or p depending upon the technology
Anurup Mitra CMOS Fabrication
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Oxidation of Wafer
The wafer is oxidised at a high temperature
This must be patterned to define the n-well
Anurup Mitra CMOS Fabrication
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PR deposition
The photoresist is deposited throughout the wafer
The PR has to be patterned to allow formation of the well
Anurup Mitra CMOS Fabrication
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n-well Mask
The PR is exposed through the n-well mask
The softened PR is is removed to expose the oxide
Anurup Mitra CMOS Fabrication
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Oxide Etch
The oxide is etched with HF acid where unprotected by PR
The wafer is now exposed to the n-well area
Anurup Mitra CMOS Fabrication
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PR removal
The remaining PR is removed via piranha etch
The well is ready to be formed
Anurup Mitra CMOS Fabrication
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n-well Formation
The di usionff process can make the the n-well
Ion implantation can also form the same
Anurup Mitra CMOS Fabrication
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Gate Formation
The gates are made up of polysilicon over thinox
CVD is used to grow the poly (heavily doped) layer
Anurup Mitra CMOS Fabrication
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Diffusion Pattern
Again, a protective oxide is grown and PR deposited
PR is patterned according to the di usion maskff
Anurup Mitra CMOS Fabrication
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n-Di usion Regionsff
The n+ di usion regions are formedff
Polysilicon blocks the channel area
Anurup Mitra CMOS Fabrication
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Self-Aligned Process
This is a self-aligned process
S/D are automatically formed adjacent to the gate
Anurup Mitra CMOS Fabrication
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p-Di usionff
The p-di usion mask is used nextff
This completes creation of all active regions
Anurup Mitra CMOS Fabrication
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Metal Formation
Al is sputtered over the entire area filling contact cuts too
Metal is patterned with the metal mask
Anurup Mitra CMOS Fabrication
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P-Well Process
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Twin-Tub (Twin-Well) CMOS Process
• This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently.
• Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top.
• This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics.
• In the conventional p & n-well CMOS process, the doping density of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics. The twin-tub process avoids this problem.
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Twin-Tub (Twin-Well) CMOS Process
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Latch-Up in CMOS Circuits• A problem which is inherent in the p-well and n-well CMOS processes is
due to the relatively large number of junctions which are formed in these
structures , the consequent presence of parasitic transistors and diodes.
• Latch-Up is a condition in which the parasitic components give rise to the
establishment of low resistance conducting paths between VDD and VSS
with disastrous results.
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Remedies for the Latch-up problem
• Reduce the well and substrate resistances, producing lower voltage drops
– Higher substrate doping level reduces Rsub– Reduce Rwell by making low resistance
contact to GND– Guard rings around p- and/or n-well, with
frequent contacts to the rings, reduces the parasitic resistances.
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BiCMOS Technology
• Combines Bipolar and CMOS transistors in a single integrated circuit
• By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with speed-power-density performance previously unattainable with either technology individually.
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Characteristics of CMOS Technology
• Lower static power dissipation• Higher noise margins• Higher packing density – lower manufacturing cost per device• High yield with large integrated complex functions
• High input impedance (low drive current)• Scalable threshold voltage• High delay sensitivity to load (fan-out limitations)• Low output drive current (issue when driving large capacitive loads)• Low transconductance, where transconductance, gm Vin
• Bi-directional capability (drain & source are interchangeable)• A near ideal switching device
Advantages of CMOS over bipolar
Other CMOS Advantages
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Characteristics of Bipolar Technology
• Higher switching speed• Higher current drive per unit area, higher gain• Generally better noise performance and better high frequency
characteristics• Better analogue capability• Improved I/O speed (particularly significant with the growing importance of
package limitations in high speed systems).
• high power dissipation• lower input impedance (high drive current)• low voltage swing logic• low packing density• low delay sensitivity to load• high gm (gm Vin)
• high unity gain band width (ft) at low currents• essentially unidirectional
Advantages of Bipolar over CMOS
Other Bipolar Advantages
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Combine advantages in BiCMOS Technology
• It follows that BiCMOS technology goes some way towards combining the
virtues
of both CMOS and Bipolar technologies
• Resulting benefits of BiCMOS technology over solely CMOS or solely
bipolar :
• Improved speed over purely-CMOS technology
• Lower power dissipation than purely-bipolar technology (simplifying
packaging and board requirements)
• high performance analogue
• Latch up immunity
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BiCMOS Fabrication
• Theoretically there should be little difficulty in extending CMOS fab processes to include
bipolar as well as MOS transistors.
• In fact, a problem of p-well and n-well CMOS processing is that parasitic bipolar transistors
are inadvertently formed as part of the outcome of fabrication (CMOS latchup).
• Production of npn bipolar transistors with good performance characteristics can be achieved,
e.g., by extending the standard n-well CMOS processing to include further masks to add two
additional layers; the n+ sub collector and p+ base layers.
• The npn transistor is formed an n-well & the additional p+ base region is located in the well to
form the p-base region of the transistor. The second additional layer, the buried n+ sub
collector (BCCD) is added to reduce the n-well (collector) resistance & thus improve the
quality of the bipolar transistor.
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Arrangement of BiCMOS npn transistor (orbit 2um CMOS) for reference
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Thank You