ICM 2003, Dec. 9-1 1, Cairo, Egypt.

ABSTRACT Cascode compensation increases the speed of two stage amplifiers compared to conventional Miller compensation. The cost is an increase of pole zero complexity such that traditional open loop analysis will not lead to intuitive design equations. This paper introduces a systematic design .approach of cascode compensated two stage OTAs. The parametric transfer function, settling error and thermal noise equations were first extracted from the small signal equivalent circuit of the OTA, then a set of poles and zeros which best suited settling requjrements was asserted into the non-linear equations relating pole zero and circuit parameters, through which circuit parameters were calculated. Using the system level results Spice simulation of the OTA was performed in a 0.35pm CMOS process. The simulated OTA achieved a DC-gain of lOOdB with a I20MHz bandwidth and a 62" phase margin from a 3V power supply. ,The measured dissipated power was 2.01 mW with a settling time of 7 nSec.

1. INTRODUCTION One of the major blocks in switched capacitor circuits

is the Operational Transconductance Amplifier (OTA) with topologies highly dependent on the desired performance. In some applications such as the first stage of pipelined ADCs the requirement of simultaneous high DC-gain and fast settling time, necessitates the use of a two stage OTA with cascode compensation. While the standard Miller compensation performs pole splitting via a capacitor between the outputs of first and

SYSTEMATIC STEPS IN DESIGN-OF A CMOS TWO- STAGE CASCODE-COMPENSATED OTA

Sayyed Mahdi Kashmiri, Hiva Hedayati, and Omid Shoaei * Electrical Engineering Dept. of Iran Univ. of Science and Technology, Tehran, Iran

*IC-Design Lab., ECE Dept., Univ. of Tehran, Tehran, I.R. Iran, http://www.eng.ut.ac.ir/lCLabl

E-mails: sm-keshmiri@yahoo.com, hedayati-hiva@hotmail.com

second OTA stages, the cascode compensation creates a dominant pole and two complex poles by a capacitor between amplifier output and first stage cascode node [I]. It has been proved that cascode compensated OTAs achieve higher bandwidths [ I ,2] and better settling characteristics [3] to their Miller compensated counterparts, but the complexity of third order transfer function and lack of direct relationship between circuit parameters, step response and settling time, creates a complexLdesign appioach.

To plan a systematic design procedure, in this paper we tried to introduce the parametric equations of cascode compensated OTA transfer function, parametric pole zero equations, step response and settling behavior in sections Two and Three. Through the analysis of settling behavior an optimized set of system parameters were obtained in section Four. After considering the circuit thermal noise in section Five, the optimized parameters were used to solve a series of non-linear equations in section Six, which yielded the best circuit parameters. Finally a design example was reported in section Seven.

2. SMALL SIGNAL ANALYSIS

The proposed two-stage cascode compensated OTA shown in Fig.1 uses a telescopic first stage because of its smaller noise contribution, smaller current consumption, and wider bandwidth in contrast to the folded counterpart. The second stage is a fully differential topology, which eliminates the need for a dynamic level shift between the first stage output and the second stage input. An all NMOS signal path was chosen due to the higher speed performance of NMOS devices versus PMOS ones. The DC-gain of the opamp is in the order of (g,,,ro)?

Mi 1 ei 1

-. I

Figure 1. The Cascode Compensated OTA

In order to analyze the op-amp in closed loop [4,5] a small signal closed lopp equivalent circuit with a feedback factor p was considered (E.ig.2). The circuit is used in closed

4q9

loop small signal analysis for derivation of relationship between the closed loop poles and zeros, and the small signal parameters like system transfer function and settling behavior. In this model the output resistance of MOS transistors has been assumed to be infinite for further simplifications [3]. ,

Figure2. Small Signal Model The parasitic and external capacitances are lumped into three capacitors CI, C2 and CL. where:

' Ji,' .* . , First a closed loop small signal analysis is used to derive a

relationship between the closed l o ~ p poles and zeros, and the small signal parameters of devices. A nodal analysis of the small signal model reveals the circuit transfer function:

(Salgm9 - S 2 c C c 2 ) VfSd CZC?

Where: C: =C& +C& +C,,C,. (3) To 'parameterize poles and zeros the following standard third order transfer function is considered:

As can be noticed from (4) there are four parameters a, y, < (damping factor), and an (natural frequency) describing the cascode compensated OTA's poles and zeros (Fig.3). The coefficients of s are equated in equations (3) and (4), so that the placement of closed-loop poles and zeros are related to the circuit small signal parameters by the following non-linear equations:

Figure 3. The parametric poles and zeros of OTA

In the following sections the best values for a. < and w, that meet the settling requirements of OTA will be chosen. Atter pole positioning these p a q e t e r s are substituted in equations ( 5 ) to yield circuit parameters.

3. SETLLING BEHAVIOR

Settling error is a measure of the deviation of the step response from the value it might attain if there were infinite time to settle. To callcvlate this error the time domain step response of the :systerp must be calculated first via taking a reverse Laplace transfop from the multiplication of OTA frequency domain transfer function and step function (l/s). The time domain step response of the cascode compensated OTA has been calculated in [3] same way:

- According to (6) the step response consists of an exponeptially decaying term due to the on-axis pole and a damped oscillatory term due to complex poles. Defining settling error in equation (7) the settling error percentage at a particula! time t;$ could be found 131:

(7)

This equation is too complicated to see the relationship ..be&wew-settling time and pole positioning parameters. SO

, for better observation it must be explored numerically.

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4. POLE POSITIONING Considering ts as the half of sampling clock period and

w, as a measure of bandwidth, the normalized quantity W,IS was used in a graphical analysis of equation (8) to get a clear understanding of the OTA closed-loop poles placement. The settling error of OTA at the end of amplification phase in pipelined ADCs can be translated to the ADC resolution for which this error is tolerable. The plot in Fig.4 has been generated by measuring the resolution to which OTA settles'as a function of w,is, while varying

Figure 7. OTA thermal noise

6. DERIVATION OF CIRCUIT PARAMETER VALUES

The design process started with development of equations illustrating trade offs and continued with a selection of pole position parameters (a, Z; run). To get final circuit parameters considering minimum power solutions a computer optimization algorithm was developed.

P... lWl

Figure 8. Power Dissipation as a function of Cc and Vem The non-linear equations of (5) were re-written based on process parameters, Veff and aspect ratio ( W L ) of devices. An optimization algorithm developed in MATLAB@ gets the problem inputs: process parameters, pole positioning parameters and best swing meeting the effective voltages of the transistors. Then it solves the non-linear equation set ( 5 ) for the transistor aspect ratios. Important system specifications plots like increase of PDISS as a function of Cc and Veffl increase (Fig.8)* OTA DC- gain increase as a function of Vefil and VeR3 decrease (Fig.9), and DC-gain increase as a function of MI and M9 length increase (Fig.10) were sketched using the optimization algorithm. With the help of such plots the algorithm inputs could be re-assigned to derive transistor specifications, which yielded best OTA specifications.

Figure 9. OTA DC-gain as a function of Veffl and Veff3

Figure 10. OTA DC-gain a 5 a functiop of L5 and L9

7. CIRCUIT SIMULATION Using the system level results Spice simulatipn of thp

OTA in a 0.35pm CMOS process, showed an A x of IOOdB, a IPOMHz GBW, a 62O phase margin. an4 7 nSec settling time from a 3V supply with 2.01 mW dissipation.

8. SUMMARY A complete systematig design procedure of a cascode

compensated OTA was introduced from extraction of equations to selection of parameters and derivation of final circuit specifications using the optimizatipn algorithms.

9. REFERSNCES B.K. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiep,fEEE JSC,

D.B.Ribner, M.A.Copeland, Design Techniques for Cascode CMOS Op Amps, with Improved PSRR aqd Common Mode Input Range, JEEE Journal of Solid- Stare Circuits. Vol. 19. pp629-633, Dec. 1984 A. Feldman, High-speed. Low-Power Sigma-Delta Modulators for RI: Doseband Channel Application, PhD Thepis, UC Berkeley 1997 K. BoorH. Khoo. Progmimable High-Dynamic Range Sigma-Delta A/D Convertem for MultiStandard. Fully Integrated RF Receivers, MSc thesis, UC Berkeley 1998 R.Lotfi, 0.Shoaei. A Low-Voltage, Low-Power Fast- Settting Operational Amplifier for Use in High-speed. High-Resolution Pipelined AID Converters, ISCAS 2002

Vol. 18, pp629-633, Dec. 19831

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